From 18abc435b5b5b962bf7188d76c145167c8aec98c Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Wed, 18 Feb 2015 19:43:28 +0100 Subject: [PATCH] Baseline init problem to be solved, but simulation runs --- ADC/sim/adcprocessor_cfd.mpf | 66 ++++++++++++++++++---------------- ADC/sim/wave_cfd.do | 68 +++++------------------------------- 2 files changed, 43 insertions(+), 91 deletions(-) diff --git a/ADC/sim/adcprocessor_cfd.mpf b/ADC/sim/adcprocessor_cfd.mpf index aeb0ad0..2e81f4b 100644 --- a/ADC/sim/adcprocessor_cfd.mpf +++ b/ADC/sim/adcprocessor_cfd.mpf @@ -648,7 +648,7 @@ Resolution = ns UserTimeUnit = default ; Default run length -RunLength = 80 us +RunLength = 10 us ; Maximum iterations that can be run without advancing simulation time IterationLimit = 5000 @@ -1739,47 +1739,51 @@ suppress = 8780 ;an explanation can be had by running: verror 8780 Project_Version = 6 Project_DefaultLib = work Project_SortMethod = unused -Project_Files_Count = 20 +Project_Files_Count = 22 Project_File_0 = ../../base/trb3_components.vhd -Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423225382 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_0 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423225382 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_1 = /home/aneiser/trb3/ADC/sim/dqsinput_dummy.vhd -Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424254306 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 19 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424254306 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 18 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_2 = ../config.vhd -Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423771351 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424271228 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2002 Project_File_3 = ../../../trbnet/trb_net_components.vhd -Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1407152791 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1407152791 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_4 = ../source/adc_processor.vhd Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423486629 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_5 = dummyADC.vhd -Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423329902 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 8 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_6 = /home/aneiser/trb3/base/cores/dqsinput_5x5.vhd -Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393410143 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_7 = ../cores/mulacc2.vhd -Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423224716 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_8 = tb_adcprocessor.vhd -Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424252624 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 2 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_5 = /home/aneiser/trb3/ADC/source/adc_processor_cfd_ch.vhd +Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424284817 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 20 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_6 = dummyADC.vhd +Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423329902 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 7 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_7 = /home/aneiser/trb3/base/cores/dqsinput_5x5.vhd +Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393410143 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 15 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_8 = ../cores/mulacc2.vhd +Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423224716 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_9 = /home/aneiser/trb3/base/cores/dqsinput_7x5.vhd -Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1391588655 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 17 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_10 = /home/aneiser/trb3/base/cores/fifo_cdt_200_50.vhd -Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423755971 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 18 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1391588655 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 16 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_10 = ../../../trbnet/trb_net_std.vhd +Project_File_P_10 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1413795496 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_11 = /home/aneiser/trb3/base/cores/pll_in200_out40.vhd -Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393571792 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_12 = ../../../trbnet/trb_net_std.vhd -Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1413795496 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393571792 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_12 = /home/aneiser/trb3/base/cores/fifo_cdt_200_50.vhd +Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423755971 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 17 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_13 = /home/aneiser/trb3/ADC/source/adc_ad9219.vhd -Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424253035 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 11 dont_compile 0 cover_nosub 0 vhdl_use93 2002 -Project_File_14 = /home/aneiser/trb3/base/cores/pll_adc10bit_80.vhd -Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423771155 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 13 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_15 = /home/aneiser/trb3/base/cores/pll_adc10bit.vhd -Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393571792 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424269612 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 10 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_14 = /home/aneiser/trb3/ADC/source/adc_processor_cfd.vhd +Project_File_P_14 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424284238 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 21 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_15 = /home/aneiser/trb3/base/cores/pll_adc10bit_80.vhd +Project_File_P_15 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423771155 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 12 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_16 = /home/aneiser/trb3/base/cores/pll_in200_out80.vhd -Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423771269 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 15 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_17 = txt_util.vhd -Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1410506555 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 9 cover_nosub 0 dont_compile 0 vhdl_use93 2002 -Project_File_18 = ../source/adc_package.vhd -Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423329902 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 0 dont_compile 0 cover_nosub 0 vhdl_use93 2002 +Project_File_P_16 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1423771269 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 14 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_17 = /home/aneiser/trb3/base/cores/pll_adc10bit.vhd +Project_File_P_17 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1393571792 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_18 = txt_util.vhd +Project_File_P_18 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1410506555 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_File_19 = version.vhd -Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1420726258 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_P_19 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1420726258 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_20 = ../source/adc_package.vhd +Project_File_P_20 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424284238 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2002 +Project_File_21 = /home/aneiser/trb3/ADC/sim/tb_adcprocessor_cfd.vhd +Project_File_P_21 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder {Top Level} last_compile 1424284238 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 19 cover_nosub 0 dont_compile 0 vhdl_use93 2002 Project_Sim_Count = 0 Project_Folder_Count = 0 Echo_Compile_Output = 0 diff --git a/ADC/sim/wave_cfd.do b/ADC/sim/wave_cfd.do index 682abb1..5ca9b80 100644 --- a/ADC/sim/wave_cfd.do +++ b/ADC/sim/wave_cfd.do @@ -4,81 +4,29 @@ quietly virtual signal -install /tb { /tb/adc_data(19 downto 10)} adc_data_1 quietly virtual signal -install /tb { /tb/adc_data(29 downto 20)} adc_data_2 quietly virtual signal -install /tb { /tb/adc_data(39 downto 30)} adc_data_3 quietly WaveActivateNextPane {} 0 -add wave -noupdate -radix hexadecimal /tb/clock add wave -noupdate -format Analog-Step -height 84 -max 1023.0 -radix hexadecimal -childformat {{/tb/adc_data_0(9) -radix hexadecimal} {/tb/adc_data_0(8) -radix hexadecimal} {/tb/adc_data_0(7) -radix hexadecimal} {/tb/adc_data_0(6) -radix hexadecimal} {/tb/adc_data_0(5) -radix hexadecimal} {/tb/adc_data_0(4) -radix hexadecimal} {/tb/adc_data_0(3) -radix hexadecimal} {/tb/adc_data_0(2) -radix hexadecimal} {/tb/adc_data_0(1) -radix hexadecimal} {/tb/adc_data_0(0) -radix hexadecimal}} -subitemconfig {/tb/adc_data(9) {-radix hexadecimal} /tb/adc_data(8) {-radix hexadecimal} /tb/adc_data(7) {-radix hexadecimal} /tb/adc_data(6) {-radix hexadecimal} /tb/adc_data(5) {-radix hexadecimal} /tb/adc_data(4) {-radix hexadecimal} /tb/adc_data(3) {-radix hexadecimal} /tb/adc_data(2) {-radix hexadecimal} /tb/adc_data(1) {-radix hexadecimal} /tb/adc_data(0) {-radix hexadecimal}} /tb/adc_data_0 add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal -childformat {{/tb/adc_data_1(19) -radix hexadecimal} {/tb/adc_data_1(18) -radix hexadecimal} {/tb/adc_data_1(17) -radix hexadecimal} {/tb/adc_data_1(16) -radix hexadecimal} {/tb/adc_data_1(15) -radix hexadecimal} {/tb/adc_data_1(14) -radix hexadecimal} {/tb/adc_data_1(13) -radix hexadecimal} {/tb/adc_data_1(12) -radix hexadecimal} {/tb/adc_data_1(11) -radix hexadecimal} {/tb/adc_data_1(10) -radix hexadecimal}} -subitemconfig {/tb/adc_data(19) {-radix hexadecimal} /tb/adc_data(18) {-radix hexadecimal} /tb/adc_data(17) {-radix hexadecimal} /tb/adc_data(16) {-radix hexadecimal} /tb/adc_data(15) {-radix hexadecimal} /tb/adc_data(14) {-radix hexadecimal} /tb/adc_data(13) {-radix hexadecimal} /tb/adc_data(12) {-radix hexadecimal} /tb/adc_data(11) {-radix hexadecimal} /tb/adc_data(10) {-radix hexadecimal}} /tb/adc_data_1 add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/adc_data_2 add wave -noupdate -clampanalog 1 -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/adc_data_3 -add wave -noupdate -radix hexadecimal /tb/adc_valid add wave -noupdate -divider {Buffer Input} -add wave -noupdate -radix hexadecimal /tb/UUT/ram_data_in -add wave -noupdate -radix hexadecimal /tb/UUT/ram_write -add wave -noupdate -radix hexadecimal /tb/UUT/stop_writing add wave -noupdate -divider Buffers -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/ram_wr_pointer(9) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(8) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(7) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(6) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(5) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(4) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(3) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(2) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(1) -radix hexadecimal} {/tb/UUT/ram_wr_pointer(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/ram_wr_pointer(9) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(8) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(7) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(6) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(5) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(4) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(3) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(2) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(1) {-height 14 -radix hexadecimal} /tb/UUT/ram_wr_pointer(0) {-height 14 -radix hexadecimal}} /tb/UUT/ram_wr_pointer -add wave -noupdate -radix hexadecimal /tb/UUT/ram_rd_pointer(0) -add wave -noupdate -radix hexadecimal /tb/UUT/ram_count(0) add wave -noupdate -divider Reader -add wave -noupdate -radix hexadecimal /tb/UUT/ram_remove -add wave -noupdate -radix hexadecimal /tb/UUT/reg2_ram_remove -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/ram_data_out(0)(17) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(16) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(15) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(14) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(13) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(12) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(11) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(10) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(9) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(8) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(7) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(6) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(5) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(4) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(3) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(2) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(1) -radix hexadecimal} {/tb/UUT/ram_data_out(0)(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/ram_data_out(0)(17) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(16) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(15) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(14) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(13) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(12) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(11) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(10) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(9) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(8) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(7) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(6) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(5) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(4) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(3) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(2) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(1) {-height 15 -radix hexadecimal} /tb/UUT/ram_data_out(0)(0) {-height 15 -radix hexadecimal}} /tb/UUT/ram_data_out(0) add wave -noupdate -divider Baseline -add wave -noupdate /tb/UUT/ram_read -add wave -noupdate /tb/UUT/baseline_reset -add wave -noupdate -format Analog-Step -height 80 -max 1024.0 -radix hexadecimal /tb/UUT/baseline(0) -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline(0) -radix hexadecimal} {/tb/UUT/baseline(1) -radix hexadecimal} {/tb/UUT/baseline(2) -radix hexadecimal} {/tb/UUT/baseline(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline(0) {-height 15 -radix hexadecimal} /tb/UUT/baseline(1) {-height 15 -radix hexadecimal} /tb/UUT/baseline(2) {-height 15 -radix hexadecimal} /tb/UUT/baseline(3) {-height 15 -radix hexadecimal}} /tb/UUT/baseline -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/baseline_averages(0) -radix hexadecimal} {/tb/UUT/baseline_averages(1) -radix hexadecimal} {/tb/UUT/baseline_averages(2) -radix hexadecimal} {/tb/UUT/baseline_averages(3) -radix hexadecimal}} -subitemconfig {/tb/UUT/baseline_averages(0) {-height 14 -radix hexadecimal} /tb/UUT/baseline_averages(1) {-height 14 -radix hexadecimal} /tb/UUT/baseline_averages(2) {-height 14 -radix hexadecimal} /tb/UUT/baseline_averages(3) {-height 14 -radix hexadecimal}} /tb/UUT/baseline_averages -add wave -noupdate /tb/UUT/readout_flag -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/thresh_counter(3) -radix hexadecimal} {/tb/UUT/thresh_counter(2) -radix hexadecimal} {/tb/UUT/thresh_counter(1) -radix hexadecimal} {/tb/UUT/thresh_counter(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/thresh_counter(3) {-height 14 -radix hexadecimal} /tb/UUT/thresh_counter(2) {-height 14 -radix hexadecimal} /tb/UUT/thresh_counter(1) {-height 14 -radix hexadecimal} /tb/UUT/thresh_counter(0) {-height 14 -radix hexadecimal}} /tb/UUT/thresh_counter +add wave -noupdate /tb/UUT/gen_cfd(0)/THE_CFD/delay_baseline_out.word +add wave -noupdate /tb/UUT/gen_cfd(0)/THE_CFD/delay_baseline_in.word +add wave -noupdate /tb/UUT/gen_cfd(0)/THE_CFD/baseline add wave -noupdate -divider Readout add wave -noupdate /tb/UUT/READOUT_RX.data_valid -add wave -noupdate /tb/UUT/state -add wave -noupdate /tb/UUT/stop_writing_rdo -add wave -noupdate -radix hexadecimal /tb/UUT/after_trg_cnt -add wave -noupdate /tb/UUT/readout_state -add wave -noupdate /tb/UUT/channelselect -add wave -noupdate /tb/UUT/prepare_header -add wave -noupdate /tb/UUT/blockcurrent -add wave -noupdate -radix hexadecimal /tb/UUT/myavg +add wave -noupdate /tb/UUT/READOUT_RX.valid_timing_trg add wave -noupdate -divider {data processor} -add wave -noupdate /tb/UUT/ram_valid -add wave -noupdate /tb/UUT/RDO_write_proc -add wave -noupdate -radix hexadecimal /tb/UUT/RDO_data_proc add wave -noupdate /tb/UUT/READOUT_TX.data_finished add wave -noupdate /tb/UUT/READOUT_TX.busy_release -add wave -noupdate -divider PSA -add wave -noupdate -radix hexadecimal /tb/UUT/psa_adcdata -add wave -noupdate -radix hexadecimal /tb/UUT/psa_ram_out -add wave -noupdate -radix hexadecimal /tb/UUT/psa_output -add wave -noupdate /tb/UUT/ram_read_psa -add wave -noupdate -radix hexadecimal /tb/UUT/psa_addr_i -add wave -noupdate -radix hexadecimal /tb/UUT/psa_clear -add wave -noupdate -radix hexadecimal /tb/UUT/psa_data_i -add wave -noupdate -radix hexadecimal /tb/UUT/psa_enable -add wave -noupdate -radix hexadecimal /tb/UUT/psa_pointer -add wave -noupdate /tb/UUT/psa_state -add wave -noupdate -divider CFD -add wave -noupdate /tb/UUT/READOUT_RX.valid_timing_trg -add wave -noupdate /tb/UUT/ram_read -add wave -noupdate -radix decimal /tb/UUT/ram_rd_pointer(1) -add wave -noupdate -radix hexadecimal /tb/UUT/ram_data_out(1) -add wave -noupdate -radix hexadecimal /tb/UUT/reg_ram_data_out(1) -add wave -noupdate /tb/UUT/ram_read_cfd -add wave -noupdate /tb/UUT/RDO_write_cfd -add wave -noupdate -radix hexadecimal /tb/UUT/RDO_data_cfd -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/reg_ram_data_out(0)(17) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(16) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(15) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(14) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(13) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(12) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(11) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(10) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(9) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(8) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(7) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(6) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(5) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(4) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(3) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(2) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(1) -radix hexadecimal} {/tb/UUT/reg_ram_data_out(0)(0) -radix hexadecimal}} -subitemconfig {/tb/UUT/reg_ram_data_out(0)(17) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(16) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(15) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(14) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(13) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(12) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(11) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(10) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(9) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(8) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(7) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(6) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(5) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(4) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(3) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(2) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(1) {-height 14 -radix hexadecimal} /tb/UUT/reg_ram_data_out(0)(0) {-height 14 -radix hexadecimal}} /tb/UUT/reg_ram_data_out(0) -add wave -noupdate /tb/UUT/cfd_state -add wave -noupdate -radix decimal /tb/UUT/cfd_integral_sum -add wave -noupdate -format Analog-Step -height 100 -max 1000.0 -min -1000.0 -radix decimal /tb/UUT/cfd_subtracted(1) -add wave -noupdate -radix decimal -childformat {{/tb/UUT/cfd_delay_ram(1)(2)(16) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(15) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(14) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(13) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(12) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(11) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(10) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(9) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(8) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(7) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(6) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(5) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(4) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(3) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(2) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(1) -radix decimal} {/tb/UUT/cfd_delay_ram(1)(2)(0) -radix decimal}} -subitemconfig {/tb/UUT/cfd_delay_ram(1)(2)(16) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(15) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(14) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(13) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(12) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(11) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(10) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(9) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(8) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(7) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(6) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(5) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(4) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(3) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(2) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(1) {-height 14 -radix decimal} /tb/UUT/cfd_delay_ram(1)(2)(0) {-height 14 -radix decimal}} /tb/UUT/cfd_delay_ram(1)(2) -add wave -noupdate -format Analog-Step -height 100 -max 1000.0 -min -1000.0 -radix decimal /tb/UUT/cfd(1) add wave -noupdate -divider Config -add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/CONFIG.processing_mode -radix hexadecimal} {/tb/UUT/CONFIG.buffer_depth -radix decimal} {/tb/UUT/CONFIG.samples_after -radix hexadecimal} {/tb/UUT/CONFIG.block_count -radix hexadecimal} {/tb/UUT/CONFIG.trigger_threshold -radix decimal} {/tb/UUT/CONFIG.readout_threshold -radix decimal} {/tb/UUT/CONFIG.presum -radix hexadecimal} {/tb/UUT/CONFIG.averaging -radix hexadecimal} {/tb/UUT/CONFIG.trigger_enable -radix hexadecimal} {/tb/UUT/CONFIG.channel_disable -radix hexadecimal} {/tb/UUT/CONFIG.baseline_always_on -radix hexadecimal} {/tb/UUT/CONFIG.baseline_reset_value -radix hexadecimal} {/tb/UUT/CONFIG.block_avg -radix hexadecimal} {/tb/UUT/CONFIG.block_sums -radix hexadecimal} {/tb/UUT/CONFIG.block_scale -radix hexadecimal} {/tb/UUT/CONFIG.check_word1 -radix hexadecimal} {/tb/UUT/CONFIG.check_word2 -radix hexadecimal} {/tb/UUT/CONFIG.check_word_enable -radix hexadecimal} {/tb/UUT/CONFIG.cfd_window -radix hexadecimal} {/tb/UUT/CONFIG.cfd_delay -radix hexadecimal}} -expand -subitemconfig {/tb/UUT/CONFIG.processing_mode {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.buffer_depth {-height 15 -radix decimal} /tb/UUT/CONFIG.samples_after {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.block_count {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.trigger_threshold {-height 15 -radix decimal} /tb/UUT/CONFIG.readout_threshold {-height 15 -radix decimal} /tb/UUT/CONFIG.presum {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.averaging {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.trigger_enable {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.channel_disable {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.baseline_always_on {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.baseline_reset_value {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.block_avg {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.block_sums {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.block_scale {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.check_word1 {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.check_word2 {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.check_word_enable {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.cfd_window {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.cfd_delay {-height 15 -radix hexadecimal}} /tb/UUT/CONFIG +add wave -noupdate -radix hexadecimal -childformat {{/tb/UUT/CONFIG.InputThreshold -radix hexadecimal} {/tb/UUT/CONFIG.PolarityInvert -radix hexadecimal} {/tb/UUT/CONFIG.BaselineAverage -radix hexadecimal} {/tb/UUT/CONFIG.BaselineAlwaysOn -radix hexadecimal} {/tb/UUT/CONFIG.CFDDelay -radix hexadecimal} {/tb/UUT/CONFIG.CFDMult -radix hexadecimal} {/tb/UUT/CONFIG.CFDMultDly -radix hexadecimal} {/tb/UUT/CONFIG.IntegrateWindow -radix hexadecimal} {/tb/UUT/CONFIG.TriggerDelay -radix hexadecimal} {/tb/UUT/CONFIG.check_word1 -radix hexadecimal} {/tb/UUT/CONFIG.check_word2 -radix hexadecimal} {/tb/UUT/CONFIG.check_word_enable -radix hexadecimal}} -subitemconfig {/tb/UUT/CONFIG.InputThreshold {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.PolarityInvert {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.BaselineAverage {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.BaselineAlwaysOn {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.CFDDelay {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.CFDMult {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.CFDMultDly {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.IntegrateWindow {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.TriggerDelay {-height 14 -radix hexadecimal} /tb/UUT/CONFIG.check_word1 {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.check_word2 {-height 15 -radix hexadecimal} /tb/UUT/CONFIG.check_word_enable {-height 15 -radix hexadecimal}} /tb/UUT/CONFIG add wave -noupdate /tb/UUT/TRIGGER_OUT -add wave -noupdate /tb/UUT/trigger_gen TreeUpdate [SetDefaultTree] -WaveRestoreCursors {{Cursor 1} {74100 ns} 0} -configure wave -namecolwidth 232 +WaveRestoreCursors {{Cursor 1} {308824 ps} 0} +configure wave -namecolwidth 150 configure wave -valuecolwidth 107 configure wave -justifyvalue left configure wave -signalnamewidth 1 @@ -92,4 +40,4 @@ configure wave -griddelta 40 configure wave -timeline 0 configure wave -timelineunits ns update -WaveRestoreZoom {72552 ns} {75048 ns} +WaveRestoreZoom {0 ps} {11001838 ps} -- 2.43.0