From 19df87c51c04ee0923e35e42409938f377e68632 Mon Sep 17 00:00:00 2001 From: HADES DAQ Date: Mon, 17 Oct 2022 20:25:43 +0200 Subject: [PATCH] added correct PLL for 200MHz calibration oscillator, mt --- dirich5s/config_compile_giessen.pl | 1 - dirich5s/config_compile_gsi.pl | 2 +- dirich5s/dirich5s.prj | 5 ++++- dirich5s/dirich5s.vhd | 3 ++- dirich5s/nodelist_hades69.txt | 7 +++++++ dirich5s/par.p2t | 4 ++-- 6 files changed, 16 insertions(+), 6 deletions(-) create mode 100644 dirich5s/nodelist_hades69.txt diff --git a/dirich5s/config_compile_giessen.pl b/dirich5s/config_compile_giessen.pl index b692b37..9a42f04 100644 --- a/dirich5s/config_compile_giessen.pl +++ b/dirich5s/config_compile_giessen.pl @@ -3,7 +3,6 @@ Devicename => 'LFE5UM-85F', Package => 'CABGA381', Speedgrade => '8', - TOPNAME => "dirich5s", lm_license_file_for_synplify => "7788\@fb07pc-u102325", lm_license_file_for_par => "7788\@fb07pc-u102325", diff --git a/dirich5s/config_compile_gsi.pl b/dirich5s/config_compile_gsi.pl index 902dc11..1af88c9 100644 --- a/dirich5s/config_compile_gsi.pl +++ b/dirich5s/config_compile_gsi.pl @@ -1,6 +1,6 @@ Familyname => 'ECP5UM', Devicename => 'LFE5UM-85F', -Package => 'CABGA756', +Package => 'CABGA381', Speedgrade => '8', TOPNAME => "dirich5s", diff --git a/dirich5s/dirich5s.prj b/dirich5s/dirich5s.prj index 8de4dd8..0f11128 100644 --- a/dirich5s/dirich5s.prj +++ b/dirich5s/dirich5s.prj @@ -213,8 +213,11 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_DC_36x32_OutReg/FI add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x128_OutReg/FIFO_36x128_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x64_OutReg/FIFO_36x64_OutReg.vhd" add_file -vhdl -lib work "../../tdc/base/cores/ecp5/FIFO/FIFO_36x32_OutReg/FIFO_36x32_OutReg.vhd" +add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in200_out50/pll_in200_out50.vhd" #add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out33/pll_in125_out33.vhd" -add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd" +#add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in125_out50/pll_in125_out50.vhd" + ### Triggering add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd" diff --git a/dirich5s/dirich5s.vhd b/dirich5s/dirich5s.vhd index 1628bee..085878e 100644 --- a/dirich5s/dirich5s.vhd +++ b/dirich5s/dirich5s.vhd @@ -166,7 +166,8 @@ begin -- end if; -- end process; -THE_CAL_PLL : entity work.pll_in3125_out50 +--THE_CAL_PLL : entity work.pll_in3125_out50 +THE_CAL_PLL : entity work.pll_in200_out50 port map( CLKI => CLOCK_CAL, CLKOP => clk_cal diff --git a/dirich5s/nodelist_hades69.txt b/dirich5s/nodelist_hades69.txt new file mode 100644 index 0000000..44b6ae0 --- /dev/null +++ b/dirich5s/nodelist_hades69.txt @@ -0,0 +1,7 @@ +// nodes file for parallel place&route + +[localhost] +SYSTEM = linux +CORENUM = 12 +ENV = /home/hadaq/bin/diamond_env +WORKDIR = /home/hadaq/vhdl/dirich/dirich5s/workdir diff --git a/dirich5s/par.p2t b/dirich5s/par.p2t index edb14a5..fae8f59 100644 --- a/dirich5s/par.p2t +++ b/dirich5s/par.p2t @@ -5,7 +5,7 @@ #-n 2 # Controlled by the compile.pl script. -s 10 #-t 96 --t 70 +-t 60 -c 2 -e 2 -i 10 @@ -68,4 +68,4 @@ # parHold. # parPlcInLimit Cannot find in the online help # parPlcInNeighborSize Cannot find in the online help --exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=OFF:paruseNBR=1 +-exp parHold=ON:parHoldLimit=10000:parCDP=1:parCDR=1:parPathBased=ON:paruseNBR=1 -- 2.43.0