From 1b630db6cf75c693d98d72eebddd1b2064c4e29a Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 13 Jun 2022 11:02:42 +0200 Subject: [PATCH] add register for address setting to hub --- trb_net16_hub_base.vhd | 50 +++++++++++++++++++++++++++++++++++++----- 1 file changed, 45 insertions(+), 5 deletions(-) diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 3f3416f..ded5c7d 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -305,6 +305,14 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal stat_busycntexcl_ack : std_logic; signal stat_busycntexcl_unknown : std_logic; + signal busaddr_addr : std_logic_vector(15 downto 0); + signal busaddr_read : std_logic; + signal busaddr_write : std_logic; + signal busaddr_datarx : std_logic_vector(31 downto 0); + signal busaddr_datatx : std_logic_vector(31 downto 0); + signal busaddr_rack : std_logic; + signal busaddr_wack : std_logic; + signal stat_globaltime_read : std_logic; signal stat_globaltime_write : std_logic; signal last_stat_globaltime_read : std_logic; @@ -354,6 +362,8 @@ architecture trb_net16_hub_base_arch of trb_net16_hub_base is signal dummy : std_logic_vector(270 downto 0); signal tmp_buf_to_hub_REPLY_DATA_ctrl : std_logic_vector(15 downto 0); + signal CONF_addresses : std_logic_vector(31 downto 0); + signal CONF_generic : std_logic_vector(7 downto 0); attribute syn_preserve : boolean; attribute syn_keep : boolean; @@ -1086,6 +1096,7 @@ end generate; API_RUN_IN => HC_RUN_OUT, API_SEQNR_IN => HC_SEQNR_OUT, MY_ADDRESS_OUT => HUB_ADDRESS, + CONF_ADDRESSES => CONF_addresses, TRIGGER_MONITOR => '0', GLOBAL_TIME => global_time, LOCAL_TIME => local_time, @@ -1121,9 +1132,9 @@ end generate; --Fucking Modelsim wants it like this... THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"0000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", others => x"0000"), - PORT_ADDR_MASK => (0 => 16, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, others => 0), + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"0000", 1 => x"4000", 2 => x"4020", 3 => x"4030", 4 => x"4040", 5 => x"4050", 6 => x"4060", 7 => x"7000", others => x"0000"), + PORT_ADDR_MASK => (0 => 16, 1 => 5, 2 => 4, 3 => 4, 4 => 4, 5 => 0, 6 => 4, 7 => 1, others => 0), PORT_MASK_ENABLE => 0 ) port map( @@ -1154,6 +1165,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_ADDR_OUT(95 downto 80) => dummy(60 downto 45), BUS_ADDR_OUT(99 downto 96) => lsm_addr, BUS_ADDR_OUT(111 downto 100) => dummy(72 downto 61), + BUS_ADDR_OUT(112 downto 112) => busaddr_addr(0 downto 0), BUS_DATA_IN(31 downto 0) => REGIO_DATA_IN, BUS_DATA_IN(63 downto 32) => stat_packets_data, BUS_DATA_IN(95 downto 64) => stat_errorbits_data, @@ -1161,6 +1173,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_DATA_IN(159 downto 128) => stat_busycntexcl_data, BUS_DATA_IN(191 downto 160) => global_time, BUS_DATA_IN(223 downto 192) => lsm_data, + BUS_DATA_IN(255 downto 224) => busaddr_datatx, BUS_DATA_OUT(31 downto 0) => REGIO_DATA_OUT, BUS_DATA_OUT(63 downto 32) => dummy(104 downto 73), BUS_DATA_OUT(95 downto 64) => dummy(136 downto 105), @@ -1168,6 +1181,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_DATA_OUT(159 downto 128) => dummy(200 downto 169), BUS_DATA_OUT(191 downto 160) => dummy(232 downto 201), BUS_DATA_OUT(223 downto 192) => dummy(264 downto 233), + BUS_DATA_OUT(255 downto 224) => busaddr_datarx, BUS_DATAREADY_IN(0) => REGIO_DATAREADY_IN, BUS_DATAREADY_IN(1) => stat_packets_ready, BUS_DATAREADY_IN(2) => stat_errorbits_ready, @@ -1175,6 +1189,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_DATAREADY_IN(4) => stat_busycntexcl_ready, BUS_DATAREADY_IN(5) => last_stat_globaltime_read, BUS_DATAREADY_IN(6) => last_lsm_read, + BUS_DATAREADY_IN(7) => busaddr_rack, BUS_NO_MORE_DATA_IN(0) => REGIO_NO_MORE_DATA_IN, BUS_NO_MORE_DATA_IN(1) => '0', BUS_NO_MORE_DATA_IN(2) => '0', @@ -1182,6 +1197,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(4) => '0', BUS_NO_MORE_DATA_IN(5) => '0', BUS_NO_MORE_DATA_IN(6) => '0', + BUS_NO_MORE_DATA_IN(7) => '0', BUS_READ_ENABLE_OUT(0) => REGIO_READ_ENABLE_OUT, BUS_READ_ENABLE_OUT(1) => stat_packets_read, BUS_READ_ENABLE_OUT(2) => stat_errorbits_read, @@ -1189,6 +1205,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_READ_ENABLE_OUT(4) => stat_busycntexcl_read, BUS_READ_ENABLE_OUT(5) => stat_globaltime_read, BUS_READ_ENABLE_OUT(6) => lsm_read, + BUS_READ_ENABLE_OUT(7) => busaddr_read, BUS_TIMEOUT_OUT(0) => REGIO_TIMEOUT_OUT, BUS_TIMEOUT_OUT(1) => dummy(265), BUS_TIMEOUT_OUT(2) => dummy(266), @@ -1203,6 +1220,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_UNKNOWN_ADDR_IN(4) => stat_busycntexcl_unknown, BUS_UNKNOWN_ADDR_IN(5) => last_stat_globaltime_write, BUS_UNKNOWN_ADDR_IN(6) => lsm_write, + BUS_UNKNOWN_ADDR_IN(7) => '0', BUS_WRITE_ACK_IN(0) => REGIO_WRITE_ACK_IN, BUS_WRITE_ACK_IN(1) => stat_packets_ack, BUS_WRITE_ACK_IN(2) => '0', @@ -1210,6 +1228,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_WRITE_ACK_IN(4) => stat_busycntexcl_ack, BUS_WRITE_ACK_IN(5) => '0', BUS_WRITE_ACK_IN(6) => '0', + BUS_WRITE_ACK_IN(7) => busaddr_wack, BUS_WRITE_ENABLE_OUT(0) => REGIO_WRITE_ENABLE_OUT, BUS_WRITE_ENABLE_OUT(1) => stat_packets_write, BUS_WRITE_ENABLE_OUT(2) => stat_errorbits_write, @@ -1217,7 +1236,7 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_WRITE_ENABLE_OUT(4) => stat_busycntexcl_write, BUS_WRITE_ENABLE_OUT(5) => stat_globaltime_write, BUS_WRITE_ENABLE_OUT(6) => lsm_write, - + BUS_WRITE_ENABLE_OUT(7) => busaddr_write, STAT_DEBUG => open ); @@ -1327,7 +1346,28 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --------------------------------------------------------------------- --Status and Control Registers --------------------------------------------------------------------- - + proc_addresses : process begin + wait until rising_edge(CLK); + CONF_addresses(31) <= '0'; + busaddr_rack <= '0'; + busaddr_wack <= '0'; + if busaddr_write = '1' then + busaddr_wack <= '1'; + if busaddr_addr(0) = '0' then + CONF_generic <= busaddr_datarx(7 downto 0); + else + CONF_addresses <= busaddr_datarx; + end if; + elsif busaddr_read = '1' then + busaddr_rack <= '1'; + if busaddr_addr(0) = '0' then + busaddr_datatx <= X"000000" & CONF_generic; + else + busaddr_datatx <= CONF_addresses; + end if; + end if; + end process; + gen_timeout_values : for k in 0 to 3 generate proc_get_timeout_value : process(CLK) begin -- 2.43.0