From 1b78ae7e5d2e1bc6f14ece0056f0ecdd430c1516 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 28 Oct 2015 14:51:16 +0100 Subject: [PATCH] Adding input monitor and trigger generation to trb3sc_tools. Code added to most TRB3sc designs. --- adcaddon/trb3sc_adc.prj | 2 + adcaddon/trb3sc_adc.vhd | 11 ++-- backplanemaster/config.vhd | 11 +++- backplanemaster/config_compile_gsi.pl | 13 +++++ backplanemaster/trb3sc_master.prj | 2 + backplanemaster/trb3sc_master.vhd | 20 +++++-- code/trb3sc_tools.vhd | 79 +++++++++++++++++++++++++-- hubaddon/config.vhd | 11 +++- padiwa/config.vhd | 10 +++- padiwa/trb3sc_padiwa.prj | 2 + padiwa/trb3sc_padiwa.vhd | 12 +++- pinout/trb3sc_master.lpf | 42 +++++++------- pulser/config.vhd | 9 ++- tdctemplate/config.vhd | 8 ++- tdctemplate/trb3sc_tdctemplate.prj | 2 + tdctemplate/trb3sc_tdctemplate.vhd | 17 +++++- template/config.vhd | 9 ++- template/trb3sc_basic.prj | 2 + template/trb3sc_basic.vhd | 4 ++ 19 files changed, 215 insertions(+), 51 deletions(-) create mode 100644 backplanemaster/config_compile_gsi.pl diff --git a/adcaddon/trb3sc_adc.prj b/adcaddon/trb3sc_adc.prj index 0939a95..62b1e9e 100644 --- a/adcaddon/trb3sc_adc.prj +++ b/adcaddon/trb3sc_adc.prj @@ -109,6 +109,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/adcaddon/trb3sc_adc.vhd b/adcaddon/trb3sc_adc.vhd index 0dac757..1b4e319 100644 --- a/adcaddon/trb3sc_adc.vhd +++ b/adcaddon/trb3sc_adc.vhd @@ -160,7 +160,7 @@ architecture trb3sc_adc_arch of trb3sc_adc is signal lcd_data : std_logic_vector(511 downto 0); signal sfp_los_i, sfp_txdis_i, sfp_prsnt_i : std_logic; - + signal trig_gen_out_i : std_logic_vector(3 downto 0); signal adcspi_ctrl : std_logic_vector(7 downto 0); @@ -312,7 +312,7 @@ gen_reallogic : if USE_DUMMY_READOUT = 0 generate ADC_DATA(54 downto 50) => ADC11_CH, ADC_DATA(59 downto 55) => ADC12_CH, ADC_DCO => ADC_DCO, - TRIGGER_FLAG_OUT => open, + TRIGGER_FLAG_OUT => trig_gen_out_i(0), TRIGGER_IN => TRIG_LEFT, READOUT_RX => readout_rx, @@ -478,9 +478,12 @@ end generate; -- I/O --------------------------------------------------------------------------- - RJ_IO <= "0000"; + RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0); + + + BACK_GPIO(1 downto 0) <= (others => 'Z'); + BACK_GPIO(3 downto 2) <= trig_gen_out_i(1 downto 0); - BACK_GPIO <= (others => 'Z'); -- BACK_LVDS <= (others => '0'); -- BACK_3V3 <= (others => 'Z'); diff --git a/backplanemaster/config.vhd b/backplanemaster/config.vhd index 38ea0fe..a01e403 100644 --- a/backplanemaster/config.vhd +++ b/backplanemaster/config.vhd @@ -26,9 +26,16 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 18; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 22; constant INCLUDE_GBE : integer := c_YES; - + ------------------------------------------------------------------------------ --End of design configuration @@ -97,7 +104,7 @@ function generateIncludedFeatures return std_logic_vector is begin t := (others => '0'); t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 - t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1)); +-- t(16 downto 16) := std_logic_vector(to_unsigned(USE_ETHERNET,1)); t(17 downto 17) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); --sctrl via GbE t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); t(26 downto 24) := std_logic_vector(to_unsigned(1,3)); --num SFPs with TrbNet diff --git a/backplanemaster/config_compile_gsi.pl b/backplanemaster/config_compile_gsi.pl new file mode 100644 index 0000000..29d7ee3 --- /dev/null +++ b/backplanemaster/config_compile_gsi.pl @@ -0,0 +1,13 @@ +TOPNAME => "trb3sc_basic", +lm_license_file_for_synplify => "27000\@lxcad01.gsi.de", +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/opt/lattice/diamond/3.4_x64/', +synplify_path => '/opt/synplicity/J-2014.09-SP2', +#synplify_command => "/opt/lattice/diamond/3.4_x64/bin/lin64/synpwrap -fg -options", +synplify_command => "/opt/synplicity/K-2015.09/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_gsi_template.txt', + +firefox_open => 0, + + diff --git a/backplanemaster/trb3sc_master.prj b/backplanemaster/trb3sc_master.prj index 053a16d..764e2ab 100644 --- a/backplanemaster/trb3sc_master.prj +++ b/backplanemaster/trb3sc_master.prj @@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/backplanemaster/trb3sc_master.vhd b/backplanemaster/trb3sc_master.vhd index 52445b0..22b2f49 100644 --- a/backplanemaster/trb3sc_master.vhd +++ b/backplanemaster/trb3sc_master.vhd @@ -22,7 +22,7 @@ entity trb3sc_master is TRIG_LEFT : in std_logic; --Additional IO HDR_IO : inout std_logic_vector(10 downto 1); --- RJ_IO : inout std_logic_vector( 3 downto 0); + RJ_IO : inout std_logic_vector( 3 downto 0); -- SPARE_IN : in std_logic_vector( 1 downto 0); BACK_LVDS : inout std_logic_vector( 1 downto 0); BACK_3V3 : inout std_logic_vector( 3 downto 0); @@ -30,8 +30,8 @@ entity trb3sc_master is --Lines to slaves BACK_MASTER_READY : out std_logic_vector(8 downto 0); BACK_SLAVE_READY : in std_logic_vector(8 downto 0); - BACK_SPARE1 : in std_logic_vector(8 downto 0); - BACK_SPARE2 : in std_logic_vector(8 downto 0); + BACK_TRIG1 : in std_logic_vector(8 downto 0); + BACK_TRIG2 : in std_logic_vector(8 downto 0); --LED LED_GREEN : out std_logic; @@ -153,6 +153,9 @@ architecture trb3sc_arch of trb3sc_master is signal mc_unique_id : std_logic_vector(63 downto 0); signal reset_via_gbe : std_logic; + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(17 downto 0); + signal backplane_rx_present, backplane_tx_present : std_logic_vector(8 downto 0); attribute syn_keep of GSR_N : signal is true; @@ -338,6 +341,8 @@ THE_MEDIA_4_DOWN2 : entity work.med_ecp3_sfp_sync_4 --PCSC gen_ready_signals : for i in 0 to 8 generate backplane_rx_present(i) <= BACK_SLAVE_READY(i); BACK_MASTER_READY(i) <= backplane_tx_present(i); + + monitor_inputs_i(i*2+1 downto i*2) <= BACK_TRIG2(i) & BACK_TRIG1(i); end generate; --------------------------------------------------------------------------- @@ -583,6 +588,11 @@ end generate; ADC_MOSI => ADC_DIN, ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS(17 downto 0) => monitor_inputs_i, + MONITOR_INPUTS(21 downto 18) => trig_gen_out_i, + TRIG_GEN_INPUTS => monitor_inputs_i, + TRIG_GEN_OUTPUTS => trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -594,7 +604,6 @@ end generate; BUS_MASTER_ACTIVE => bus_master_active, DEBUG_OUT => open ); - --------------------------------------------------------------------------- -- Switches @@ -632,7 +641,8 @@ end generate; --------------------------------------------------------------------------- BACK_LVDS(0) <= clk_full; BACK_LVDS(1) <= clk_sys; - + + RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0); --------------------------------------------------------------------------- -- Test Circuits diff --git a/code/trb3sc_tools.vhd b/code/trb3sc_tools.vhd index 24286b5..b0bdb24 100644 --- a/code/trb3sc_tools.vhd +++ b/code/trb3sc_tools.vhd @@ -39,6 +39,10 @@ entity trb3sc_tools is ADC_MISO : in std_logic := '0'; ADC_CLK : out std_logic := '0'; + --Trigger & Monitor + MONITOR_INPUTS : in std_logic_vector(MONITOR_INPUT_NUM-1 downto 0) := (others => '0'); + TRIG_GEN_INPUTS : in std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0) := (others => '0'); + TRIG_GEN_OUTPUTS : out std_logic_vector(TRIG_GEN_OUTPUT_NUM-1 downto 0); --SED SED_ERROR_OUT : out std_logic; @@ -59,8 +63,8 @@ end entity; architecture trb3sc_tools_arch of trb3sc_tools is -signal busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx, busflashset_rx : CTRLBUS_RX; -signal busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx, busflashset_tx : CTRLBUS_TX; +signal busflash_rx, busspi_rx, busadc_rx, bussed_rx, busuart_rx, busflashset_rx, busmon_rx, bustrig_rx : CTRLBUS_RX; +signal busflash_tx, busspi_tx, busadc_tx, bussed_tx, busuart_tx, busflashset_tx, busmon_tx, bustrig_tx : CTRLBUS_TX; signal spi_sdi, spi_sdo, spi_sck : std_logic; signal spi_cs : std_logic_vector(15 downto 0); @@ -70,7 +74,6 @@ signal uart_rx, uart_tx : std_logic; signal flashset_active : std_logic; signal flash_cs_i, flash_clk_i, flash_out_i : std_logic; signal flash_cs_s, flash_clk_s, flash_out_s : std_logic; - begin @@ -79,9 +82,9 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 6, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", 5 => x"0180", others => x"0000"), - PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, 5 => 4, others => 0), + PORT_NUMBER => 8, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0400", 2 => x"0480", 3 => x"0500", 4 => x"0600", 5 => x"0180", 6 => x"0f00", 7 => x"0f80", others => x"0000"), + PORT_ADDR_MASK => (0 => 9, 1 => 5, 2 => 5, 3 => 1, 4 => 2, 5 => 4, 6 => 7, 7 => 7, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -97,12 +100,16 @@ begin BUS_RX(3) => bussed_rx, BUS_RX(4) => busuart_rx, BUS_RX(5) => busflashset_rx, + BUS_RX(6) => bustrig_rx, + BUS_RX(7) => busmon_rx, BUS_TX(0) => busflash_tx, BUS_TX(1) => busspi_tx, BUS_TX(2) => busadc_tx, BUS_TX(3) => bussed_tx, BUS_TX(4) => busuart_tx, BUS_TX(5) => busflashset_tx, + BUS_TX(6) => bustrig_tx, + BUS_TX(7) => busmon_tx, STAT_DEBUG => open ); @@ -254,7 +261,67 @@ end generate; BUS_TX => busuart_tx ); end generate; + + +--------------------------------------------------------------------------- +-- Trigger logic +--------------------------------------------------------------------------- +gen_TRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate + THE_TRIG_LOGIC : input_to_trigger_logic + generic map( + INPUTS => TRIG_GEN_INPUT_NUM, + OUTPUTS => TRIG_GEN_OUTPUT_NUM + ) + port map( + CLK => CLK, + + INPUT => TRIG_GEN_INPUTS, + OUTPUT => TRIG_GEN_OUTPUTS, + + DATA_IN => bustrig_rx.data, + DATA_OUT => bustrig_tx.data, + WRITE_IN => bustrig_rx.write, + READ_IN => bustrig_rx.read, + ACK_OUT => bustrig_tx.ack, + NACK_OUT => bustrig_tx.nack, + ADDR_IN => bustrig_rx.addr + ); + +end generate; + +gen_noTRIG_LOGIC : if INCLUDE_TRIGGER_LOGIC = 0 generate + bustrig_tx.unknown <= bustrig_rx.read or bustrig_rx.write; +end generate; + +--------------------------------------------------------------------------- +-- Input Statistics +--------------------------------------------------------------------------- +gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate + + THE_STAT_LOGIC : entity work.input_statistics + generic map( + INPUTS => MONITOR_INPUT_NUM, + SINGLE_FIFO_ONLY => c_YES + ) + port map( + CLK => CLK, + INPUT => MONITOR_INPUTS, + + DATA_IN => busmon_rx.data, + DATA_OUT => busmon_tx.data, + WRITE_IN => busmon_rx.write, + READ_IN => busmon_rx.read, + ACK_OUT => busmon_tx.ack, + NACK_OUT => busmon_tx.nack, + ADDR_IN => busmon_rx.addr + ); +end generate; + +gen_noSTATISTICS : if INCLUDE_STATISTICS = 0 generate + busmon_tx.unknown <= busmon_rx.read or busmon_rx.write; +end generate; + --------------------------------------------------------------------------- -- HEADER_IO --------------------------------------------------------------------------- diff --git a/hubaddon/config.vhd b/hubaddon/config.vhd index 5819d13..41269f7 100644 --- a/hubaddon/config.vhd +++ b/hubaddon/config.vhd @@ -27,6 +27,13 @@ package config is constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 0; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ @@ -99,8 +106,8 @@ function generateIncludedFeatures return std_logic_vector is t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); --- t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); --- t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); diff --git a/padiwa/config.vhd b/padiwa/config.vhd index 36735ce..08be6f0 100644 --- a/padiwa/config.vhd +++ b/padiwa/config.vhd @@ -40,8 +40,14 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; - constant INCLUDE_STATISTICS : integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/padiwa/trb3sc_padiwa.prj b/padiwa/trb3sc_padiwa.prj index 4880165..912d140 100644 --- a/padiwa/trb3sc_padiwa.prj +++ b/padiwa/trb3sc_padiwa.prj @@ -114,6 +114,8 @@ add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/padiwa/trb3sc_padiwa.vhd b/padiwa/trb3sc_padiwa.vhd index ab61d7d..6bcea6c 100644 --- a/padiwa/trb3sc_padiwa.vhd +++ b/padiwa/trb3sc_padiwa.vhd @@ -144,7 +144,7 @@ architecture trb3sc_arch of trb3sc_padiwa is signal timer : TIMERS; signal lcd_data : std_logic_vector(511 downto 0); - + signal trig_gen_out_i : std_logic_vector(3 downto 0); --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -346,6 +346,10 @@ begin ADC_MOSI => ADC_DIN, ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS(31 downto 0) => INP(31 downto 0), + TRIG_GEN_INPUTS => INP(31 downto 0), + TRIG_GEN_OUTPUTS => trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -372,7 +376,11 @@ begin -- I/O --------------------------------------------------------------------------- - RJ_IO <= "0000"; + RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0); + + + BACK_GPIO(1 downto 0) <= (others => 'Z'); + BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2); -- BACK_GPIO <= (others => 'Z'); -- BACK_LVDS <= (others => '0'); diff --git a/pinout/trb3sc_master.lpf b/pinout/trb3sc_master.lpf index b15fca9..823c466 100644 --- a/pinout/trb3sc_master.lpf +++ b/pinout/trb3sc_master.lpf @@ -15,25 +15,25 @@ IOBUF GROUP "TRIG_group" IO_TYPE=LVDS25 DIFFRESISTOR=100; # Backplane I/O ################################################################# -LOCATE COMP "BACK_SPARE1_0" SITE "B27"; -LOCATE COMP "BACK_SPARE1_1" SITE "B28"; -LOCATE COMP "BACK_SPARE1_2" SITE "A29"; -LOCATE COMP "BACK_SPARE1_3" SITE "A31"; -LOCATE COMP "BACK_SPARE1_4" SITE "L32"; #was "DQUR0_1_P" 109 -LOCATE COMP "BACK_SPARE1_5" SITE "L26"; #was "DQUR0_0_P" 105 -LOCATE COMP "BACK_SPARE1_6" SITE "K7"; #was "DQUL1_4_P" 93 -LOCATE COMP "BACK_SPARE1_7" SITE "M8"; #was "DQUL1_3_P" 89 -LOCATE COMP "BACK_SPARE1_8" SITE "K2"; #was "DQUL1_1_P" 77 - -LOCATE COMP "BACK_SPARE2_0" SITE "C27"; -LOCATE COMP "BACK_SPARE2_1" SITE "A28"; -LOCATE COMP "BACK_SPARE2_2" SITE "A30"; -LOCATE COMP "BACK_SPARE2_3" SITE "B31"; -LOCATE COMP "BACK_SPARE2_4" SITE "L31"; #DQUR0_1_N -LOCATE COMP "BACK_SPARE2_5" SITE "M25"; #DQUR0_0_N -LOCATE COMP "BACK_SPARE2_6" SITE "J6"; #DQUL1_4_N -LOCATE COMP "BACK_SPARE2_7" SITE "L7"; #DQUL1_3_N -LOCATE COMP "BACK_SPARE2_8" SITE "K1"; #DQUL1_1_N +LOCATE COMP "BACK_TRIG1_0" SITE "B27"; +LOCATE COMP "BACK_TRIG1_1" SITE "B28"; +LOCATE COMP "BACK_TRIG1_2" SITE "A29"; +LOCATE COMP "BACK_TRIG1_3" SITE "A31"; +LOCATE COMP "BACK_TRIG1_4" SITE "L32"; #was "DQUR0_1_P" 109 +LOCATE COMP "BACK_TRIG1_5" SITE "L26"; #was "DQUR0_0_P" 105 +LOCATE COMP "BACK_TRIG1_6" SITE "K7"; #was "DQUL1_4_P" 93 +LOCATE COMP "BACK_TRIG1_7" SITE "M8"; #was "DQUL1_3_P" 89 +LOCATE COMP "BACK_TRIG1_8" SITE "K2"; #was "DQUL1_1_P" 77 + +LOCATE COMP "BACK_TRIG2_0" SITE "C27"; +LOCATE COMP "BACK_TRIG2_1" SITE "A28"; +LOCATE COMP "BACK_TRIG2_2" SITE "A30"; +LOCATE COMP "BACK_TRIG2_3" SITE "B31"; +LOCATE COMP "BACK_TRIG2_4" SITE "L31"; #DQUR0_1_N +LOCATE COMP "BACK_TRIG2_5" SITE "M25"; #DQUR0_0_N +LOCATE COMP "BACK_TRIG2_6" SITE "J6"; #DQUL1_4_N +LOCATE COMP "BACK_TRIG2_7" SITE "L7"; #DQUL1_3_N +LOCATE COMP "BACK_TRIG2_8" SITE "K1"; #DQUL1_1_N LOCATE COMP "BACK_SLAVE_READY_0" SITE "C26"; LOCATE COMP "BACK_SLAVE_READY_1" SITE "D27"; @@ -56,11 +56,11 @@ LOCATE COMP "BACK_MASTER_READY_7" SITE "M3"; #DQUL0_1_N LOCATE COMP "BACK_MASTER_READY_8" SITE "H2"; #DQUL2_4_N -DEFINE PORT GROUP "BACK_SPARE_group" "BACK_SPARE*" ; +DEFINE PORT GROUP "BACK_TRIG_group" "BACK_TRIG*" ; DEFINE PORT GROUP "BACK_SLAVE_group" "BACK_SLAVE*" ; DEFINE PORT GROUP "BACK_MASTER_group" "BACK_MASTER*" ; -IOBUF GROUP "BACK_SPARE_group" IO_TYPE=LVCMOS25 PULLMODE=UP; +IOBUF GROUP "BACK_TRIG_group" IO_TYPE=LVCMOS25 PULLMODE=UP; IOBUF GROUP "BACK_SLAVE_group" IO_TYPE=LVCMOS25 PULLMODE=UP; IOBUF GROUP "BACK_MASTER_group" IO_TYPE=LVCMOS25 DRIVE=4; diff --git a/pulser/config.vhd b/pulser/config.vhd index 6881b71..a56d795 100644 --- a/pulser/config.vhd +++ b/pulser/config.vhd @@ -25,7 +25,14 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; - + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 0; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/tdctemplate/config.vhd b/tdctemplate/config.vhd index 224296b..fc6333b 100644 --- a/tdctemplate/config.vhd +++ b/tdctemplate/config.vhd @@ -41,8 +41,12 @@ package config is constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; - constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; - constant INCLUDE_STATISTICS : integer := c_YES; + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_YES; + constant INCLUDE_STATISTICS : integer := c_YES; + constant TRIG_GEN_INPUT_NUM : integer := 20; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 24; ------------------------------------------------------------------------------ --End of design configuration diff --git a/tdctemplate/trb3sc_tdctemplate.prj b/tdctemplate/trb3sc_tdctemplate.prj index 128a7f8..80c3505 100644 --- a/tdctemplate/trb3sc_tdctemplate.prj +++ b/tdctemplate/trb3sc_tdctemplate.prj @@ -116,6 +116,8 @@ add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index 6e6521e..b06befd 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -145,7 +145,8 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal timer : TIMERS; signal lcd_data : std_logic_vector(511 downto 0); - + signal trig_gen_out_i : std_logic_vector(3 downto 0); + --TDC signal hit_in_i : std_logic_vector(64 downto 1); signal logic_analyser_i : std_logic_vector(15 downto 0); @@ -346,6 +347,11 @@ begin ADC_MOSI => ADC_DIN, ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS(19 downto 0) => KEL(20 downto 1), + MONITOR_INPUTS(23 downto 20) => trig_gen_out_i, + TRIG_GEN_INPUTS => KEL(20 downto 1), + TRIG_GEN_OUTPUTS => trig_gen_out_i, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol @@ -371,9 +377,14 @@ begin -- I/O --------------------------------------------------------------------------- - RJ_IO <= "0000"; + RJ_IO(1 downto 0) <= "00"; + RJ_IO(3 downto 2) <= trig_gen_out_i(1 downto 0); + - BACK_GPIO <= (others => 'Z'); + BACK_GPIO(1 downto 0) <= (others => 'Z'); + BACK_GPIO(3 downto 2) <= trig_gen_out_i(3 downto 2); + BACK_GPIO(15 downto 4) <= (others => 'Z'); + BACK_LVDS <= (others => '0'); BACK_3V3 <= (others => 'Z'); diff --git a/template/config.vhd b/template/config.vhd index b3d9f92..60e0801 100644 --- a/template/config.vhd +++ b/template/config.vhd @@ -27,7 +27,14 @@ package config is constant INCLUDE_UART : integer := c_YES; constant INCLUDE_SPI : integer := c_YES; constant INCLUDE_LCD : integer := c_YES; - + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 0; + ------------------------------------------------------------------------------ --End of design configuration ------------------------------------------------------------------------------ diff --git a/template/trb3sc_basic.prj b/template/trb3sc_basic.prj index dbda519..2c7e60a 100644 --- a/template/trb3sc_basic.prj +++ b/template/trb3sc_basic.prj @@ -114,6 +114,8 @@ add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" #SlowControl files add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" diff --git a/template/trb3sc_basic.vhd b/template/trb3sc_basic.vhd index 23e5889..216dc8c 100644 --- a/template/trb3sc_basic.vhd +++ b/template/trb3sc_basic.vhd @@ -341,6 +341,10 @@ THE_ENDPOINT : entity work.trb_net16_endpoint_hades_full_handler_record ADC_MOSI => ADC_DIN, ADC_MISO => ADC_DOUT, ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => (others => '0'), + TRIG_GEN_INPUTS => (others => '0'), + TRIG_GEN_OUTPUTS => open, --SED SED_ERROR_OUT => sed_error_i, --Slowcontrol -- 2.43.0