From 1b9d2e5c7398d13fd19fd81e4362a98ed09d05da Mon Sep 17 00:00:00 2001
From: Peter Lemmens <p.j.j.lemmens@rug.nl>
Date: Tue, 21 Jan 2014 14:15:38 +0100
Subject: [PATCH] Source TX-FIFO removed; mostly stable: when it works, it
 keeps on working

Observed calibration delays (clocks): x3e, x3f and x40
---
 source/serdes_sync_downstream.ipx | 14 +++++++-------
 source/serdes_sync_downstream.lpc |  6 +++---
 source/serdes_sync_downstream.txt |  2 +-
 3 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/source/serdes_sync_downstream.ipx b/source/serdes_sync_downstream.ipx
index b1e4559..d3573a3 100644
--- a/source/serdes_sync_downstream.ipx
+++ b/source/serdes_sync_downstream.ipx
@@ -1,11 +1,11 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 16 15:03:46.952" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
+<DiamondModule name="serdes_sync_downstream" module="serdes_sync_downstream" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2014 01 21 12:02:05.297" version="8.1" type="Module" synthesis="synplify" source_format="VHDL">
   <Package>
-		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 16 15:03:44.000"/>
-		<File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 16 15:03:44.000"/>
-		<File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 16 15:03:44.000"/>
-		<File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 16 15:02:59.000"/>
-		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 16 15:03:44.000"/>
-		<File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 16 15:02:59.000"/>
+		<File name="serdes_sync_downstream.lpc" type="lpc" modified="2014 01 21 12:02:01.000"/>
+		<File name="serdes_sync_downstream.pp" type="pp" modified="2014 01 21 12:02:01.000"/>
+		<File name="serdes_sync_downstream.sym" type="sym" modified="2014 01 21 12:02:01.000"/>
+		<File name="serdes_sync_downstream.tft" type="tft" modified="2014 01 21 12:02:01.000"/>
+		<File name="serdes_sync_downstream.txt" type="pcs_module" modified="2014 01 21 12:02:01.000"/>
+		<File name="serdes_sync_downstream.vhd" type="top_level_vhdl" modified="2014 01 21 12:02:01.000"/>
   </Package>
 </DiamondModule>
diff --git a/source/serdes_sync_downstream.lpc b/source/serdes_sync_downstream.lpc
index 34c8b34..9f4ab45 100644
--- a/source/serdes_sync_downstream.lpc
+++ b/source/serdes_sync_downstream.lpc
@@ -16,8 +16,8 @@ CoreRevision=8.1
 ModuleName=serdes_sync_downstream
 SourceFormat=VHDL
 ParameterFileVersion=1.0
-Date=01/16/2014
-Time=15:03:44
+Date=01/21/2014
+Time=12:02:01
 
 [Parameters]
 Verilog=0
@@ -55,7 +55,7 @@ _tx_data_width0=8
 _tx_data_width1=8
 _tx_data_width2=8
 _tx_data_width3=8
-_tx_fifo0=ENABLED
+_tx_fifo0=DISABLED
 _tx_fifo1=ENABLED
 _tx_fifo2=ENABLED
 _tx_fifo3=ENABLED
diff --git a/source/serdes_sync_downstream.txt b/source/serdes_sync_downstream.txt
index 4432978..ec77632 100644
--- a/source/serdes_sync_downstream.txt
+++ b/source/serdes_sync_downstream.txt
@@ -19,7 +19,7 @@ CH0_RX_DATA_RATE        "FULL"
 CH0_TX_DATA_RATE        "FULL"
 CH0_TX_DATA_WIDTH       "8"
 CH0_RX_DATA_WIDTH        "8"
-CH0_TX_FIFO       "ENABLED"
+CH0_TX_FIFO       "DISABLED"
 CH0_RX_FIFO        "DISABLED"
 CH0_TDRV      "0"
 #CH0_TX_FICLK_RATE      200
-- 
2.43.0