From 1bc2040a4d3a51a2d42d56aaebd0dc5258a40e8a Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 23 Apr 2012 19:01:19 +0000
Subject: [PATCH] *** empty log message ***

---
 trb3/Trb3KnownBugs.tex |  4 ++--
 trb3/main.tex          | 23 +++++++++++++++++++----
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/trb3/Trb3KnownBugs.tex b/trb3/Trb3KnownBugs.tex
index 8beb092..b8fc26d 100644
--- a/trb3/Trb3KnownBugs.tex
+++ b/trb3/Trb3KnownBugs.tex
@@ -1,4 +1,4 @@
-\begin{itemize}
+\begin{itemize*}
 \item    The SFPs are missing LEDs - so no information about link status
 \item    The outputs of the CLK5410 chips are not independent: Two outputs share some settings - regarding this the connection is far from optimal, e.g. the clock to the serdes from FPGA1 is not independent from clock to GPLL input on FPGA4 etc.
 \item    SFP cages could have been distributed differently. Now, all TrbNet links (SFP1-4) are on one side and all GbE capable links on the other two (SFP5-8). Usually only few ports are in use, so a mix would be better.
@@ -9,5 +9,5 @@
 \item    Both GPLL inputs to peripheral FPGA are not usable - they are connected to Feedback input instead of normal input of PLL. They can still be used through normal routing, but source synchronous operation is not possible.
 \item    The JTAG Connector is wrong. The line labeled TDI is TDO and vice versa. 
 \item    The 48V-to-6V converter gets quite hot without air-flow. When AddOns are mounted, the fan must be installed on the short side of the TRB, not on the long one.
-\end{itemize}
+\end{itemize*}
 
diff --git a/trb3/main.tex b/trb3/main.tex
index f0bff2e..70382e0 100755
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -50,13 +50,22 @@
 %\usepackage{mathptmx}
 %\usepackage{pslatex}
 
+\newenvironment{itemize*}%
+  {\begin{itemize}%
+    \setlength{\itemsep}{0pt}%
+    \setlength{\parskip}{0pt}%
+    \setlength{\topsep}{1pt}%
+    \setlength{\partopsep}{1pt}}%
+  {\end{itemize}}
+
+
 \title{A Users Guide\\to the TRB3 \\and FPGA-TDC Based Platforms}
 \date{\today ~-~\thistime}
 \author{Grzegorz Korcyl, Ludwig Maier, Jan Michel, Marek Palka, \\Pawel Strzempek, Michael Traxler, Cahit Ugur}
 
 
 \newcommand{\filename}[1]{\textit{#1}}
-\newcommand{\portname}[1]{\textsc{#1}}
+\newcommand{\signal}[1]{\textsc{#1}}
 \newcommand{\genericname}[1]{\textsc{#1}}
 \newcommand{\constname}[1]{\textsc{#1}}
 \newcommand{\netname}[1]{\textsc{#1}}
@@ -86,19 +95,25 @@
 \clearpage
 \tableofcontents
 
+\cleardoublepage
+\part{Ressources}
+  \section{Code Repository}
+    \input{CodeRepository}
 
 \cleardoublepage
 \part{Hardware}
   \section{Measurements}
     \subsection{FPGA I/O Performance}
-
+    \clearpage
   \section{TRB3 Platform}
+    \subsection{General Remarks}
+      \input{Trb3GeneralRemarks}
     \subsection{Known Bugs and Limitations}
       \input{Trb3KnownBugs}
     \subsection{Clock and Trigger Distribution}
       \input{Trb3ClockTriggerDistribution}
-
-  \clearpage
+    \clearpage
+  
   \section{AddOns}
     \subsection{TDC AddOn}
       \input{TdcAddOn}
-- 
2.43.0