From 1c81a9efaa68f9c8e79572c4a78178207820662b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 14 Sep 2007 11:35:58 +0000 Subject: [PATCH] small changes to various files, Jan --- trb_net_active_apimbuf.vhd | 2 +- trb_net_med_8bit_fast.vhd | 201 ++++++++--------------------------- trb_net_obuf.vhd | 8 +- trb_net_priority_encoder.vhd | 3 +- 4 files changed, 50 insertions(+), 164 deletions(-) diff --git a/trb_net_active_apimbuf.vhd b/trb_net_active_apimbuf.vhd index af2e819..1bb8346 100644 --- a/trb_net_active_apimbuf.vhd +++ b/trb_net_active_apimbuf.vhd @@ -212,7 +212,7 @@ component trb_net_active_api is STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0) ); -END component; +end component; component trb_net_io_multiplexer is diff --git a/trb_net_med_8bit_fast.vhd b/trb_net_med_8bit_fast.vhd index 642b22b..cd51bd1 100644 --- a/trb_net_med_8bit_fast.vhd +++ b/trb_net_med_8bit_fast.vhd @@ -24,7 +24,7 @@ --If the timing seems to be correct but the trbnet trb_net doesn't react, try --shifting the clock by 180 degrees. - +--Version with spare bits at end, using 18_to16 was 1.8 -- -- Constraints for timing on hadcom dev board: -- NET "LVDS_IN<13>" TNM_NET = LVDS_IN_CLK_GRP; @@ -33,8 +33,8 @@ -- INST "LVDS_OUT<*>" TNM = "OUT_DDR"; -- INST lvds1/buf_MED_IN_fal* TNM = "falling_reg"; -- TIMEGRP "OUT_DDR" OFFSET = OUT 8 ns AFTER "CLK_IN"; --- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>"; --- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg"; +-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 BEFORE "LVDS_IN<13>"; +-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 BEFORE "LVDS_IN<13>" TIMEGRP "falling_reg"; --Constraints for timing on acromag: @@ -46,8 +46,8 @@ -- INST "io*_*n" TNM = "OUT_DDR"; -- INST trbnetendpoint1/lvds1/buf_MED_IN_fal* TNM = "falling_reg"; -- --- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P"; --- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg"; +-- TIMEGRP "IN_DDR" OFFSET = IN -2 ns VALID 1 ns BEFORE "IO59_29P"; +-- TIMEGRP "IN_DDR" OFFSET = IN -7 ns VALID 1 ns BEFORE "IO59_29P" TIMEGRP "falling_reg"; -- TIMEGRP "OUT_DDR" OFFSET = OUT 6.7 ns AFTER "FPGA_CLK"; @@ -136,68 +136,6 @@ component trb_net_fifo_16bit_bram_dualport end component trb_net_fifo_16bit_bram_dualport; -component trb_net_18_to_16_converter - generic ( VERSION : integer := 1); --Version of included sbufs - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - - D18_DATAREADY_IN: in STD_LOGIC; - D18_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0); - D18_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - D18_READ_OUT: out STD_LOGIC; - - D16_DATAREADY_OUT: out STD_LOGIC; - D16_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - D16_READ_IN: in STD_LOGIC; - D16_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0); - - D18_DATAREADY_OUT: out STD_LOGIC; - D18_PACKET_NUM_OUT: out STD_LOGIC_VECTOR(1 downto 0); - D18_DATA_OUT: out STD_LOGIC_VECTOR (15 downto 0); -- Data word - D18_READ_IN: in STD_LOGIC; - - D16_DATAREADY_IN: in STD_LOGIC; - D16_DATA_IN: in STD_LOGIC_VECTOR (15 downto 0); -- Data word - D16_READ_OUT: out STD_LOGIC; - D16_PACKET_NUM_IN: in STD_LOGIC_VECTOR(1 downto 0) - ); -end component; - ---component DCM ----- --- generic ( --- DFS_FREQUENCY_MODE : string := "LOW"; --- CLKFX_DIVIDE : integer := 4; -- Min 1 Max 32 (25MHz 3/4 M/D) --- CLKFX_MULTIPLY : integer := 2 ; -- Min 2 Max 32 (60MHz 20/11 M/D) ----- CLKFX_MULTIPLY : integer := 3 ; -- Min 2 Max 32 (63MHz 19/10 M/D) --- CLKIN_PERIOD : real := 10.0 ; -- 30.30ns --- STARTUP_WAIT : boolean := FALSE --- ); --- --- port ( CLKIN : in std_logic; --- CLKFB : in std_logic; --- DSSEN : in std_logic; --- PSINCDEC : in std_logic; --- PSEN : in std_logic; --- PSCLK : in std_logic; --- RST : in std_logic; --- CLK0 : out std_logic; --- CLK90 : out std_logic; --- CLK180 : out std_logic; --- CLK270 : out std_logic; --- CLK2X : out std_logic; --- CLK2X180 : out std_logic; --- CLKDV : out std_logic; --- CLKFX : out std_logic; --- CLKFX180 : out std_logic; --- LOCKED : out std_logic; --- PSDONE : out std_logic; --- STATUS : out std_logic_vector(7 downto 0) --- ); ---end component; component trb_net_sbuf generic (DATA_WIDTH : integer := 16; VERSION: integer := 0); @@ -260,11 +198,7 @@ signal next_send_packet1, send_packet1 : std_logic; signal fifo_data_ready : std_logic; signal buf_int_error_out, next_INT_ERROR_OUT : std_logic_vector(2 downto 0); - -signal CONV_DATAREADY_OUT : std_logic; -signal CONV_DATA_OUT : std_logic_vector(15 downto 0); -signal CONV_READ_IN: std_logic; -signal CONV_PACKET_NR_OUT: std_logic_vector(1 downto 0); +signal buf_INT_READ_OUT : std_logic; signal FB_CLK, CLK_FB_Out, CLK_RECV_Out : std_logic; signal sbuff_status : std_logic; signal sbuff_next_read_out : std_logic; @@ -292,53 +226,11 @@ begin -CONV16to18 : trb_net_18_to_16_converter - generic map( - VERSION => 0 - ) - port map( - -- Misc - CLK => CLK, - RESET => RESET_RECV, - CLK_EN => CLK_EN, - - D18_DATAREADY_IN => INT_DATAREADY_IN, - D18_PACKET_NUM_IN => INT_PACKET_NR_IN, - D18_DATA_IN => INT_DATA_IN, - D18_READ_OUT => INT_READ_OUT, - - D16_DATAREADY_OUT => CONV_DATAREADY_OUT, - D16_DATA_OUT => CONV_DATA_OUT, - D16_READ_IN => CONV_READ_IN, - D16_PACKET_NUM_OUT => CONV_PACKET_NR_OUT, - - D18_DATAREADY_OUT => open, - D18_PACKET_NUM_OUT => open, - D18_DATA_OUT => open, - D18_READ_IN => '0', - - D16_DATAREADY_IN => '0', - D16_DATA_IN => (others => '0'), - D16_READ_OUT => open, - D16_PACKET_NUM_IN => "00" - ); - - ----------------------------------------------------------------------- -- Getting clock from LVDS ----------------------------------------------------------------------- --- CLK_TRANS <= not MED_TRANSMISSION_CLK_IN; --- DCM_LOCKED <= '1'; - --- U5_BUFG: BUFG --- port map ( --- I => MED_TRANSMISSION_CLK_IN, --- O => buf_MED_TRANSMISSION_CLK_IN --- ); ---the inverted clock is not really necessary,but helps sorting the data! - U_DCM_RECV: DCM generic map( @@ -362,8 +254,8 @@ U_DCM_RECV: DCM ); -- U3_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK); -U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS); ---CLK_TRANS <= FB_CLK; +--U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS); +CLK_TRANS <= FB_CLK; ----------------------------------------------------------------------- -- Preparing incoming data for fifo @@ -468,24 +360,23 @@ U4_BUFG: BUFG port map (I => CLK_RECV_Out, O => CLK_TRANS); process(CLK,RESET_RECV) begin - if RESET_RECV = '1' then - last_fifo_read_enable <= '0'; - buf_int_error_out <= ERROR_NC; - buf_int_packet_nr_out <= "11"; - elsif rising_edge(CLK) then - last_fifo_read_enable <= fifo_read_enable; - buf_int_error_out <= next_int_error_out; - buf_int_packet_nr_out <= next_int_packet_nr_out; - else - last_fifo_read_enable <= last_fifo_read_enable; - buf_int_error_out <= buf_int_error_out; - buf_int_packet_nr_out <= buf_int_packet_nr_out; + if rising_edge(CLK) then + if RESET_RECV = '1' then + last_fifo_read_enable <= '0'; + buf_int_error_out <= ERROR_NC; + buf_int_packet_nr_out <= "00"; + else + last_fifo_read_enable <= fifo_read_enable; + buf_int_error_out <= next_int_error_out; + buf_int_packet_nr_out <= next_int_packet_nr_out; + end if; end if; end process; buf_comb_data_in(15 downto 0) <= fifo_data_out(15 downto 0); buf_comb_data_in(17 downto 16) <= next_int_packet_nr_out; + SBUF_fifo_to_int : trb_net_sbuf generic map(DATA_WIDTH => 18, VERSION => 0) port map ( @@ -515,7 +406,8 @@ INT_ERROR_OUT <= buf_int_error_out; -- Sending data ----------------------------------------------------------------------- -CONV_READ_IN <= DCM_LOCKED; +buf_INT_READ_OUT <= not RESET_RECV; +INT_READ_OUT <= buf_INT_READ_OUT; --RESET_RECV <= RESET or not DCM_LOCKED or not MED_DATA_IN(11); process(RESET,DCM_LOCKED,MED_DATA_IN(11)) @@ -539,7 +431,7 @@ CONV_READ_IN <= DCM_LOCKED; end process; - process(CONV_DATAREADY_OUT, CONV_DATA_OUT, CONV_PACKET_NR_OUT, CONV_READ_IN, + process(INT_DATAREADY_IN, INT_DATA_IN, INT_PACKET_NR_IN, buf_INT_READ_OUT, send_data_byte1, send_data_byte2, send_packet1) begin @@ -549,43 +441,38 @@ CONV_READ_IN <= DCM_LOCKED; next_send_data_byte1_parity <= '0'; --send_data_byte1_parity; next_send_data_byte2_parity <= '0'; --send_data_byte2_parity; next_send_packet1 <= '0'; - if CONV_DATAREADY_OUT = '1' and CONV_READ_IN = '1' then - if CONV_PACKET_NR_OUT = "00" and send_packet1 = '0' then + if INT_DATAREADY_IN = '1' and buf_INT_READ_OUT = '1' then + if INT_PACKET_NR_IN = "00" and send_packet1 = '0' then next_send_packet1 <= '1'; else next_send_packet1 <= '0'; end if; - next_send_data_byte1 <= CONV_DATA_OUT(15 downto 8); - next_send_data_byte2 <= CONV_DATA_OUT(7 downto 0); + next_send_data_byte1 <= INT_DATA_IN(15 downto 8); + next_send_data_byte2 <= INT_DATA_IN(7 downto 0); next_send_dataready <= '1'; - next_send_data_byte2_parity <= xor_all(CONV_DATA_OUT(7 downto 0)); - next_send_data_byte1_parity <= xor_all(CONV_DATA_OUT(15 downto 8)); + next_send_data_byte2_parity <= xor_all(INT_DATA_IN(7 downto 0)); + next_send_data_byte1_parity <= xor_all(INT_DATA_IN(15 downto 8)); end if; end process; process(CLK, RESET_RECV) begin - if RESET_RECV = '1' then - send_data_byte1 <= (others => '0'); - send_data_byte2 <= (others => '0'); - send_data_byte1_parity <= '0'; - send_data_byte2_parity <= '0'; - send_dataready <= '0'; - send_packet1 <= '0'; - elsif rising_edge(CLK) then - send_data_byte1 <= next_send_data_byte1 after 1 ns; - send_data_byte2 <= next_send_data_byte2 after 1 ns; - send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns; - send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns; - send_dataready <= next_send_dataready after 1 ns; - send_packet1 <= next_send_packet1 after 1 ns; - else - send_data_byte1 <= send_data_byte1; - send_data_byte2 <= send_data_byte2; - send_data_byte1_parity <= send_data_byte1_parity; - send_data_byte2_parity <= send_data_byte2_parity; - send_dataready <= send_dataready; - send_packet1 <= send_packet1; + if rising_edge(CLK) then + if RESET_RECV = '1' then + send_data_byte1 <= (others => '0'); + send_data_byte2 <= (others => '0'); + send_data_byte1_parity <= '0'; + send_data_byte2_parity <= '0'; + send_dataready <= '0'; + send_packet1 <= '0'; + else + send_data_byte1 <= next_send_data_byte1 after 1 ns; + send_data_byte2 <= next_send_data_byte2 after 1 ns; + send_data_byte1_parity <= next_send_data_byte1_parity after 1 ns; + send_data_byte2_parity <= next_send_data_byte2_parity after 1 ns; + send_dataready <= next_send_dataready after 1 ns; + send_packet1 <= next_send_packet1 after 1 ns; + end if; end if; end process; diff --git a/trb_net_obuf.vhd b/trb_net_obuf.vhd index 0e92c71..d2fbbf6 100644 --- a/trb_net_obuf.vhd +++ b/trb_net_obuf.vhd @@ -157,13 +157,13 @@ architecture trb_net_obuf_arch of trb_net_obuf is next_DATA_COUNT <= (others => '0'); increase_TRANSMITTED_BUFFERS <= '1'; comb_dataready <= '1'; - next_INT_READ_OUT <= '0'; --stop activity to be on the safe side + next_INT_READ_OUT <= '0'; --stop activity to be on the safe side end if; --finally, block data read if the rec buffer is full if sent_data = '0' or - ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0))) - and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' and INT_DATA_IN(TYPE_POSITION) = TYPE_TRM) + ((current_DATA_COUNT(DATA_COUNT_WIDTH-1 downto 0) = (max_DATA_COUNT_minus_two(DATA_COUNT_WIDTH-1 downto 0))) + and reg_INT_READ_OUT = '1' and INT_DATAREADY_IN = '1' ) --and INT_DATA_IN(TYPE_POSITION) = TYPE_TRM --long version of (next_count = max_count-1) or (next_TRANSMITTED_BUFFERS(1) = '1' and SWITCH_OFF_BUFFER_CHECK = 0) then @@ -216,7 +216,7 @@ architecture trb_net_obuf_arch of trb_net_obuf is current_EOB_word(47 downto 0) <= (others => '0'); gen_sent_EOB : process (CURRENT_DATA_COUNT, max_DATA_COUNT_minus_one) begin - if (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) then + if (CURRENT_DATA_COUNT = max_DATA_COUNT_minus_one) then sent_EOB <= '1'; else sent_EOB <= '0'; diff --git a/trb_net_priority_encoder.vhd b/trb_net_priority_encoder.vhd index 4487760..e2a3c57 100755 --- a/trb_net_priority_encoder.vhd +++ b/trb_net_priority_encoder.vhd @@ -14,7 +14,7 @@ entity trb_net_priority_encoder is RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); PATTERN_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0) ); -END trb_net_priority_encoder; +end trb_net_priority_encoder; architecture trb_net_priority_encoder_arch of trb_net_priority_encoder is @@ -24,7 +24,6 @@ architecture trb_net_priority_encoder_arch of trb_net_priority_encoder is begin G1: for i in 0 to WIDTH-1 generate - G2: if i = 0 generate fixed_pattern(0) <= INPUT_IN(0); leading_pattern(0) <= INPUT_IN(0); -- 2.43.0