From 1cf3d2886a3bb609c471de9bf6b3df6026c84ef3 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Wed, 3 Mar 2010 18:11:52 +0000
Subject: [PATCH] *** empty log message ***

---
 rich.tex | 107 ++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 106 insertions(+), 1 deletion(-)

diff --git a/rich.tex b/rich.tex
index 3d74f01..fb0128e 100755
--- a/rich.tex
+++ b/rich.tex
@@ -140,5 +140,110 @@ This may change in the future.
 \end{center}
 \end{table}
 
-\subsubsection{Pedestals}
+\subsubsection{Pedestals and thresholds}
+
+Each APV frontend card has its own pedestal memory, with 128 channels each.
+The pedestal value is stored in the lower 12bit. Single channels can be 
+switched off by setting bit~16 to one.
+
+\subsubsection{I2C master}
+
+For configuration and slow control of APV chips a complete I2C master is
+implemented.
+ 
+\noindent Please use the \textbf{trb\_i2c} command for handling I2C 
+transactions on this interface.
+
+\subsubsection{1Wire master}
+
+For simple hardware identification and temperature logging all RICH hardware
+modules have an 1Wire ID chip implemented. Readout of those sensors is handled
+by a dedicated 1Wire master.
+
+\noindent Please use the \textbf{trbrichcmd} command for reading out the 
+values.
+
+\noindent The first readout will trigger a temperatur conversion, so no
+results will be given the first time. Next readout will give the results from
+the previous conversion. To avoid noise induction on the frontend cards, 
+temperature conversions must always be started by explicit command and are
+not automatically started by the FPGA.
+
+\noindent The first 15~IDs are from the attached frontend cards, the 16th is
+from the backplane module.
+
+\subsubsection{SPI master}
+
+This SPI master controls the FPGA boot SPI ROM. 
+
+\noindent It is strongly recommended to use the \textbf{trbflash} command
+for updating FlashROM contents.
+
+\subsubsection{ADC SPI slowcontrol}
+
+For each of the two ADCs on the ADCMv3 a dedicated simple SPI controller is 
+implemented. One single 32bit register controls both the SPI controller and 
+other signals for the ADC (see table~\ref{richadcspi}), as well as for low
+level reset of the APV frontend cards attached to this ADC. 
+
+\noindent Please check the ADS5271 data sheet for detailed information on
+available SPI commands. Under normal operating conditions no adjustments
+need to be made on the ADCs.
+
+\noindent The ADC PLL must be locked for normal operation, and the input
+delay value for the DDR registers of the ADC data streams be set correctly.
+The powerup values should allow stable operation.
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|X|X|}
+\hline
+\textbf{Bits} & \textbf{write access} & \textbf{read access} \\
+\hline
+\hline
+31 -- 24 & SPI command    & SPI command    \\
+23 -- 9  & ---            & ---            \\
+8        & ---            & ADC PLL locked \\
+7 -- 4   & input delay    & input delay    \\
+3        & start SPI      & ---            \\
+2        & APV reset      & APV reset      \\
+1        & ADC powerdown  & ADC powerdown  \\
+0        & ADC reset      & ADC reset      \\
+\hline
+\end{tabularx}
+\caption{ADC SPI and slow control}
+\label{richadcspi}
+\end{center}
+\end{table}
+
+\subsubsection{APV control register}
+
+For each APV frontend card a control \/ statsu register is implemented. The 
+upper 16bit deliver status information, the lower 16bit are used as control
+register.
+
+\begin{table}
+\begin{center}
+\begin{tabularx}{\textwidth}{|c|c|c|X|}
+\hline
+\textbf{Bits} & \textbf{write access} & \textbf{read access} &
+    \textbf{description} \\
+\hline
+\hline
+31       & ---      & BUF\_GOOD     & 1 if APV is synced correctly        \\
+30       & ---      & BUF\_BROKEN   & 1 if APV is actived, but not synced \\
+29       & ---      & BUF\_IGNORE   & 1 if APV is switched off            \\
+28 -- 24 & ---      & BUF\_LEVEL    & fill level of raw buffers           \\
+23 -- 20 & ---      & APV\_HARD\_ID & hardware APV ID, as in schematics   \\
+19 -- 16 & ---      & APV\_SOFT\_ID & logical APV ID as in sector layout  \\
+15 -- 2  & ---      & ---           & reserved                            \\
+1        & LVDS\_ON & LVDS\_ON      & activate LDVS driver only (debug)   \\
+0        & APV\_ON  & APV\_ON       & activate APV and LVDS driver        \\
+\hline
+\end{tabularx}
+\caption{APV control and status register}
+\label{richadcspi}
+\end{center}
+\end{table}
+
 
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2.43.0