From 1d5cb513c310d9a5d6c476a4c42c751cbc9f11ea Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 27 Jul 2010 19:31:53 +0000 Subject: [PATCH] minor update --- libtrbnet/trbnet.c | 37 ++++++++++++++++--------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 8933c87..7b03adf 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,4 +1,4 @@ -const char trbnet_version[] = "$Revision: 2.74 $"; +const char trbnet_version[] = "$Revision: 2.75 $"; #include #include @@ -404,51 +404,46 @@ static void fifo_flush(uint8_t channel) static int trb_wait_tx_not_busy(uint8_t channel) { uint32_t tmp = 0; - unsigned int timeout = 0; - + if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; return -1; } - while (timeout < MAX_TIMEOUT) { - read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); - if ((tmp & MASK_TX_RUNNING) == 0) { - return 0; - } - timeout++; + read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); + if ((tmp & MASK_TX_RUNNING) != 0) { + trb_errno = TRB_TX_BUSY; + return -1; } - - /* timeout occurred */ - trb_errno = TRB_TX_BUSY; - return -1; + + return 0; } static int trb_init_transfer(uint8_t channel) { uint32_t tmp = 0; - + if (channel >= 4) { trb_errno = TRB_INVALID_CHANNEL; return -1; } - - /* Check for TX not Busy, wait MAX_TIMEOUT */ + + /* Check for TX not Busy */ read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); - if ((tmp & MASK_TX_RUNNING) != 0) { + if (tmp != 0) { trb_errno = TRB_TX_BUSY; return -1; } - + /* Check receiver FIFO empty*/ - read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), + read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), &tmp); if ((tmp & MASK_FIFO_EMPTY) == 0) { fifo_flush(channel); trb_errno = TRB_FIFO_NOT_EMPTY; return -1; } - + /* No Errors */ return 0; } @@ -1693,7 +1688,7 @@ int network_reset() if (trb_debug > 0) { fprintf(stderr, "network_reset started.\n"); } - + write32_to_FPGA(0x10, 0x0000); usleep(1000); write32_to_FPGA(0x10, 0x8000); -- 2.43.0