From 1d697b4b87c960dad8db39bd7e2e527e47ffdb34 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 22 Jun 2009 13:06:12 +0000 Subject: [PATCH] *** empty log message *** --- special/trb2_control_endpoint_tlk.vhd | 2 +- special/trb_net_bridge_etrax_endpoint.vhd | 30 +- trb_net16_endpoint_0_trg_1_api.vhd | 4 + trb_net16_endpoint_hades_cts.vhd | 8 +- trb_net16_hub_base.vhd | 2 +- trb_net16_hub_ipu_logic.vhd | 27 +- trb_net16_hub_logic.vhd | 57 +-- trb_net16_ibuf.vhd | 594 +++++++++------------- trb_net16_iobuf.vhd | 1 - trb_net_components.vhd | 179 ++++--- 10 files changed, 403 insertions(+), 501 deletions(-) diff --git a/special/trb2_control_endpoint_tlk.vhd b/special/trb2_control_endpoint_tlk.vhd index a64ef01..fd694a9 100644 --- a/special/trb2_control_endpoint_tlk.vhd +++ b/special/trb2_control_endpoint_tlk.vhd @@ -283,7 +283,7 @@ begin the_bridge: trb_net_bridge_etrax_endpoint generic map( USE_CHANNELS => (c_YES, c_YES, c_NO, c_YES), - AUTO_ANSWER_INCOMING_REQUESTS => (c_YES,c_YES,c_YES,c_YES) + AUTO_ANSWER_INCOMING_REQUESTS => (c_NO,c_NO,c_NO,c_NO) ) port map( RESET => RESET, diff --git a/special/trb_net_bridge_etrax_endpoint.vhd b/special/trb_net_bridge_etrax_endpoint.vhd index 3c43d39..556122f 100644 --- a/special/trb_net_bridge_etrax_endpoint.vhd +++ b/special/trb_net_bridge_etrax_endpoint.vhd @@ -631,22 +631,28 @@ begin INT_MASTER_DATA_OUT => apl_to_buf_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), INT_MASTER_PACKET_NUM_OUT=> apl_to_buf_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), INT_MASTER_READ_IN => apl_to_buf_INIT_READ(i), - INT_MASTER_DATAREADY_IN => apl_to_buf_REPLY_DATAREADY(i), - INT_MASTER_DATA_IN => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_MASTER_PACKET_NUM_IN => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_MASTER_READ_OUT => apl_to_buf_REPLY_READ(i), - INT_SLAVE_DATAREADY_OUT => buf_to_apl_INIT_DATAREADY(i), - INT_SLAVE_DATA_OUT => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_OUT => buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_IN => buf_to_apl_INIT_READ(i), - INT_SLAVE_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), - INT_SLAVE_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), - INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), - INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_MASTER_DATAREADY_IN => buf_to_apl_REPLY_DATAREADY(i), + INT_MASTER_DATA_IN => buf_to_apl_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_MASTER_PACKET_NUM_IN => buf_to_apl_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_MASTER_READ_OUT => buf_to_apl_REPLY_READ(i), + INT_SLAVE_DATAREADY_OUT => apl_to_buf_REPLY_DATAREADY(i), + INT_SLAVE_DATA_OUT => apl_to_buf_REPLY_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_OUT => apl_to_buf_REPLY_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_IN => apl_to_buf_REPLY_READ(i), + INT_SLAVE_DATAREADY_IN => buf_to_apl_INIT_DATAREADY(i), + INT_SLAVE_DATA_IN => buf_to_apl_INIT_DATA((i+1)*c_DATA_WIDTH-1 downto i*c_DATA_WIDTH), + INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM((i+1)*c_NUM_WIDTH-1 downto i*c_NUM_WIDTH), + INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ(i), -- Status and control port STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int((2*i+2)*32-1 downto (2*i+1)*32), STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl((2*i+2)*32-1 downto (2*i+1)*32) ); + + + + + + end generate; end generate; gen_no_api : if USE_CHANNELS(i) = c_NO generate diff --git a/trb_net16_endpoint_0_trg_1_api.vhd b/trb_net16_endpoint_0_trg_1_api.vhd index 563b090..cbe02f8 100644 --- a/trb_net16_endpoint_0_trg_1_api.vhd +++ b/trb_net16_endpoint_0_trg_1_api.vhd @@ -80,6 +80,7 @@ entity trb_net16_endpoint_0_trg_1_api is STAT_api_control_signals: out std_logic_vector(31 downto 0); STAT_MPLEX: out std_logic_vector(31 downto 0); CTRL_GEN: in std_logic_vector (31 downto 0); + CTRL_SEQNR_RESET: in std_logic; MPLEX_CTRL: in std_logic_vector (31 downto 0); API_STAT_FIFO_TO_INT: out std_logic_vector(31 downto 0); API_STAT_FIFO_TO_APL: out std_logic_vector(31 downto 0); @@ -225,6 +226,7 @@ architecture trb_net16_endpoint_0_trg_1_api_arch of trb_net16_endpoint_0_trg_1_a INT_SLAVE_READ_OUT : out std_logic; -- Status and control port + CTRL_SEQNR_RESET : in std_logic; STAT_FIFO_TO_INT : out std_logic_vector(31 downto 0); STAT_FIFO_TO_APL : out std_logic_vector(31 downto 0) ); @@ -444,6 +446,7 @@ begin INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_REPLY_PACKET_NUM, INT_SLAVE_READ_OUT => buf_to_apl_REPLY_READ, -- Status and control port + CTRL_SEQNR_RESET => CTRL_SEQNR_RESET, STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl ); @@ -502,6 +505,7 @@ begin INT_SLAVE_PACKET_NUM_IN=> buf_to_apl_INIT_PACKET_NUM, INT_SLAVE_READ_OUT => buf_to_apl_INIT_READ, -- Status and control port + CTRL_SEQNR_RESET => CTRL_SEQNR_RESET, STAT_FIFO_TO_INT => buf_api_stat_fifo_to_int, STAT_FIFO_TO_APL => buf_api_stat_fifo_to_apl ); diff --git a/trb_net16_endpoint_hades_cts.vhd b/trb_net16_endpoint_hades_cts.vhd index 95e6268..ea4d424 100644 --- a/trb_net16_endpoint_hades_cts.vhd +++ b/trb_net16_endpoint_hades_cts.vhd @@ -531,10 +531,10 @@ begin if buf_APL_PACKET_NUM_OUT(2 downto 0) = c_F1 and buf_APL_TYP_OUT(2 downto 0) = TYPE_TRM then buf_TRG_STATUS_BITS_OUT(31 downto 16) <= buf_APL_DATA_OUT(15 downto 0); end if; - if buf_APL_PACKET_NUM_OUT(2 downto 0) = c_F2 and buf_APL_TYP_OUT(2 downto 0) = TYPE_TRM then - buf_TRG_STATUS_BITS_OUT(15 downto 0) <= buf_APL_DATA_OUT(15 downto 0); - end if; - end if; + if buf_APL_PACKET_NUM_OUT(2 downto 0) = c_F2 and buf_APL_TYP_OUT(2 downto 0) = TYPE_TRM then + buf_TRG_STATUS_BITS_OUT(15 downto 0) <= buf_APL_DATA_OUT(15 downto 0); + end if; + end if; end process; diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 556ebff..2c28a86 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -210,7 +210,7 @@ begin end process; - gen_resync : for i in 0 to MII_NUMBER-1 generate + gen_internal_reset : for i in 0 to MII_NUMBER-1 generate SYNC_RESET_MUX_IO : process(CLK) begin if rising_edge(CLK) then diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 6ac0e65..84f1ba9 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -138,7 +138,6 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal reply_arbiter_enable : std_logic; signal reply_arbiter_CLK_EN : std_logic; signal reply_arbiter_reset : std_logic; - signal saved_reply_arbiter_CLK_EN : std_logic; signal INIT_muxed_DATAREADY : std_logic; signal INIT_muxed_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); @@ -673,7 +672,7 @@ begin if rising_edge(CLK) then if RESET = '1' or reply_data_counter_reset = '1' then reply_data_counter <= (others => '1'); - elsif last_comb_REPLY_POOL_DATAREADY = '1' and packet_counter(0) = '0' then + elsif last_comb_REPLY_POOL_DATAREADY = '1' and (packet_counter = c_F1 or packet_counter = c_F3) then reply_data_counter <= reply_data_counter + 1; end if; end if; @@ -761,7 +760,7 @@ reply_compare_finished <= reply_compare_start; reply_adder_overflow, current_reply_reading_DHDR, reply_adder_final_result, evt_seqnr, evt_dtype, evt_random_code, evt_number, number_of_replies, current_muxed_reading_DAT,reply_data_counter, current_point_length, - reply_arbiter_result, REPLY_DATAREADY_IN, saved_reply_arbiter_CLK_EN) + reply_arbiter_result, REPLY_DATAREADY_IN) begin release_locked <= '0'; next_state <= current_state; @@ -884,6 +883,7 @@ reply_compare_finished <= reply_compare_start; when SENDING_DATA => reply_arbiter_enable <= '1'; last_dhdr_addr <= "110"; --length + if packet_counter = c_H0 then -- and not (comb_REPLY_muxed_PACKET_NUM = c_H0 and comb_REPLY_muxed_DATA(2 downto 0) = TYPE_TRM) -- and current_muxed_reading_DAT = '1' then @@ -898,17 +898,15 @@ reply_compare_finished <= reply_compare_start; comb_REPLY_POOL_PACKET_NUM <= packet_counter; end if; - if reply_data_counter = current_point_length then - if packet_counter(0) = '0' then --'0' - reply_arbiter_CLK_EN <= '1'; - reply_data_counter_reset <= '1'; - else - start_read_padding <= reply_arbiter_result; - end if; - elsif or_all(reply_arbiter_result and REPLY_DATAREADY_IN)='1' then - reply_arbiter_CLK_EN <= '0'; - else - reply_arbiter_CLK_EN <= saved_reply_arbiter_CLK_EN; + --if number of announced words is reached and F1 or F3 is written, then care about padding + if reply_data_counter = current_point_length and packet_counter(0) = '1' and comb_REPLY_muxed_DATAREADY = '1' then + reply_arbiter_CLK_EN <= '1'; + reply_data_counter_reset <= '1'; + --either padding or trm follows. So: start reading in any case. + start_read_padding <= reply_arbiter_result; + elsif or_all(current_reply_reading_TRM and reply_arbiter_result) = '1' then +-- elsif or_all(reply_arbiter_result and REPLY_DATAREADY_IN)='1' then + reply_arbiter_CLK_EN <= '1'; end if; if send_reply_trm = '1' then @@ -983,7 +981,6 @@ reply_compare_finished <= reply_compare_start; REPLY_POOL_next_read <= comb_REPLY_POOL_next_read; waiting_for_DHDR_word <= next_waiting_for_DHDR_word; current_waiting_for_reply <= next_current_waiting_for_reply; - saved_reply_arbiter_CLK_EN <= reply_arbiter_CLK_EN; got_all_reply_starts <= not or_all(current_waiting_for_reply); not_reading_HDR <= not or_all(current_reply_reading_HDR); number_of_replies <= to_unsigned(count_ones(expected_replies),5); diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index b63cec2..a98d58b 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -5,6 +5,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_hub_logic is @@ -50,62 +51,6 @@ architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is attribute HGROUP of trb_net16_hub_logic_arch : architecture is "HUBLOGIC_group"; - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN : in STD_LOGIC; --comb logic provides data word - COMB_next_READ_OUT: out STD_LOGIC; --sbuf can read in NEXT cycle - COMB_READ_IN : in STD_LOGIC; --comb logic IS reading - COMB_DATA_IN : in STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT : out STD_LOGIC; - SYN_DATA_OUT : out STD_LOGIC_VECTOR (c_DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out STD_LOGIC_VECTOR (c_NUM_WIDTH-1 downto 0); - SYN_READ_IN : in STD_LOGIC; - -- Status and control port - STAT_BUFFER : out STD_LOGIC - ); - end component; - component trb_net_priority_arbiter is - generic ( - WIDTH : integer := POINT_NUMBER - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); - RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL: in STD_LOGIC_VECTOR (9 downto 0) - ); - end component; - - component ram_dp - generic( - depth : integer := 3; - width : integer := 16 - ); - port( - CLK : in std_logic; - wr1 : in std_logic; - a1 : in std_logic_vector(depth-1 downto 0); - dout1 : out std_logic_vector(width-1 downto 0); - din1 : in std_logic_vector(width-1 downto 0); - a2 : in std_logic_vector(depth-1 downto 0); - dout2 : out std_logic_vector(width-1 downto 0) - ); - end component; - --signals init_pool signal INIT_POOL_DATAREADY : std_logic; signal INIT_POOL_READ : std_logic; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index d3d457d..59b40ea 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -8,6 +8,7 @@ USE IEEE.std_logic_UNSIGNED.ALL; library work; use work.trb_net_std.all; +use work.trb_net_components.all; entity trb_net16_ibuf is generic ( @@ -16,7 +17,6 @@ entity trb_net16_ibuf is USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; USE_CHECKSUM : integer range 0 to 1 := c_YES; SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE : integer range 0 to 1 := c_NO; INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES ); @@ -53,63 +53,6 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is -- -- for whole architecture -- attribute HGROUP of trb_net16_ibuf_arch : architecture is "IBUF_group"; - component trb_net_CRC is - port( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - CRC_OUT : out std_logic_vector(15 downto 0); - CRC_match : out std_logic - ); - end component; - - component trb_net16_fifo is - generic ( - USE_VENDOR_CORES : integer range 0 to 1 := c_NO; - DEPTH : integer := 6 -- Depth of the FIFO - ); - port ( - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_IN : in std_logic_vector(1 downto 0); - WRITE_ENABLE_IN : in std_logic; - DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); - PACKET_NUM_OUT : out std_logic_vector(1 downto 0); - READ_ENABLE_IN : in std_logic; - FULL_OUT : out std_logic; -- Full Flag - EMPTY_OUT : out std_logic - ); - end component; - - component trb_net16_sbuf is - generic ( - VERSION : integer := 0 - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- port to combinatorial logic - COMB_DATAREADY_IN: in std_logic; --comb logic provides data word - COMB_next_READ_OUT: out std_logic; --sbuf can read in NEXT cycle - COMB_READ_IN: in std_logic; --comb logic IS reading - COMB_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - COMB_PACKET_NUM_IN: in std_logic_vector(c_NUM_WIDTH-1 downto 0); - -- Port to synchronous output. - SYN_DATAREADY_OUT: out std_logic; - SYN_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); -- Data word - SYN_PACKET_NUM_OUT: out std_logic_vector (c_NUM_WIDTH-1 downto 0); - SYN_READ_IN: in std_logic; - -- Status and control port - STAT_BUFFER: out std_logic - ); - end component; - - signal fifo_data_in : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_data_out : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal fifo_packet_num_in : std_logic_vector(1 downto 0); @@ -121,10 +64,9 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal saved_packet_type : std_logic_vector(3 downto 0); signal current_fifo_packet_type : std_logic_vector(3 downto 0); signal saved_fifo_packet_type : std_logic_vector(3 downto 0); - signal next_fifo_data_out : std_logic_vector(15 downto 0); - signal next_fifo_packet_num_out : std_logic_vector(1 downto 0); - signal next_last_fifo_read : std_logic; - signal next_fifo_empty : std_logic; + signal comb_fifo_data_out : std_logic_vector(15 downto 0); + signal comb_fifo_packet_num_out : std_logic_vector(1 downto 0); + signal next_fifo_data_valid : std_logic; signal next_read_out, reg_read_out : std_logic; signal got_ack_init_internal, reg_ack_init_internal : std_logic; @@ -148,20 +90,24 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is signal crc_out : std_logic_vector(15 downto 0); signal crc_active: std_logic; --crc active in this transfer, i.e. no short transfer - signal last_fifo_read : std_logic; - signal throw_away : std_logic; + signal fifo_data_valid : std_logic; signal fifo_read_before : std_logic; signal stat_sbufs : std_logic_vector(1 downto 0); signal counter_match : std_logic; signal init_buffer_number : std_logic_vector(15 downto 0); signal reply_buffer_number : std_logic_vector(15 downto 0); - signal next_fifo_full : std_logic; signal fifo_value_waiting : std_logic; signal reg_med_data_in : std_logic_vector(15 downto 0); signal reg_med_dataready_in : std_logic; signal reg_med_packet_num_in : std_logic_vector(2 downto 0); + signal last_fifo_read : std_logic; + signal last_fifo_empty : std_logic; + signal fifo_valid_read : std_logic; + signal reply_word_waiting : std_logic; + signal init_word_waiting : std_logic; + attribute syn_preserve : boolean; attribute syn_keep : boolean; attribute syn_preserve of fifo_data_in : signal is true; @@ -174,88 +120,79 @@ begin counter_match <= '1'; + ------------------------ ---the input fifo +--check incoming data for ACK & fifo status check ------------------------ - FIFO: trb_net16_fifo - generic map ( - DEPTH => DEPTH - ) - port map ( - CLK => CLK, - RESET => RESET, - CLK_EN => CLK_EN, - DATA_IN => fifo_data_in, - PACKET_NUM_IN => fifo_packet_num_in, - WRITE_ENABLE_IN => fifo_write, - DATA_OUT => next_fifo_data_out, - PACKET_NUM_OUT => next_fifo_packet_num_out, - READ_ENABLE_IN => fifo_read, - FULL_OUT => next_fifo_full, - EMPTY_OUT => next_fifo_empty - ); - PROC_NEXT_LAST_FIFO_READ : process(CLK) + proc_store_input_packet_type : process(CLK) begin if rising_edge(CLK) then - if (fifo_read = '1' and next_fifo_empty = '0') or fifo_value_waiting = '1' then - if (comb_next_init_read = '1' and comb_next_reply_read = '1') then - next_last_fifo_read <= '1'; - fifo_value_waiting <= '0'; - else - fifo_value_waiting <= '1'; - next_last_fifo_read <= '0'; - end if; - else - fifo_value_waiting <= '0'; - next_last_fifo_read <= '0'; + if RESET = '1' then + saved_packet_type <= '1' & TYPE_ILLEGAL; + elsif MED_PACKET_NUM_IN = c_H0 then + saved_packet_type <= MED_DATA_IN(3 downto 0); end if; end if; end process; - PROC_SYNC_FIFO_OUTPUTS : process(CLK) - begin - if rising_edge(CLK) then - if next_last_fifo_read = '1' and (sbuf_init_free = '1' and sbuf_reply_free = '1') then - fifo_data_out <= next_fifo_data_out; - fifo_packet_num_out <= next_fifo_packet_num_out; + proc_filter_input_data : process(reg_MED_DATA_IN, reg_MED_DATAREADY_IN, reg_MED_PACKET_NUM_IN, + fifo_full, current_rec_buffer_size_out, + current_error_state, reg_read_out, saved_packet_type) + begin -- process + got_ack_init_internal <= '0'; + got_ack_reply_internal <= '0'; + next_read_out <= not fifo_full; + fifo_write <= '0'; + next_rec_buffer_size_out <= current_rec_buffer_size_out; + next_error_state <= current_error_state; + if reg_MED_DATAREADY_IN = '1' and reg_read_out= '1' then + if saved_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then + if reg_MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then + got_ack_init_internal <= not saved_packet_type(3); + got_ack_reply_internal <= saved_packet_type(3); + end if; + if reg_MED_PACKET_NUM_IN = c_F1 then + next_rec_buffer_size_out <= reg_MED_DATA_IN(3 downto 0); + end if; + elsif not (saved_packet_type(2 downto 0) = TYPE_ILLEGAL) then + fifo_write <= '1'; + if fifo_full = '1' then + next_error_state <= GOT_OVERFLOW_ERROR; + end if; end if; end if; end process; - PROC_LAST_FIFO_READ : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - last_fifo_read <= '0'; - fifo_empty <= '1'; - fifo_full <= '0'; - else - last_fifo_read <= next_last_fifo_read; - fifo_empty <= next_fifo_empty; - fifo_full <= next_fifo_full; --if full it's already too late - end if; - end if; - end process; + MED_READ_OUT <= reg_read_out; - PROC_FIFO_READ_BEFORE : process(CLK) + reg_buffer: process(CLK) begin - if rising_edge(CLK) then - if RESET = '1' then - fifo_read_before <= '0'; - else - if next_last_fifo_read = '1' then - fifo_read_before <= '1'; - elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3)) - or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then - fifo_read_before <= '0'; - end if; - end if; + if rising_edge(CLK) then + if RESET = '1' then + current_rec_buffer_size_out <= (others => '0'); + reg_ack_init_internal <= '0'; + reg_ack_reply_internal <= '0'; + reg_read_out <= '0'; + current_error_state <= IDLE; + else + current_rec_buffer_size_out <= next_rec_buffer_size_out; + reg_ack_init_internal <= got_ack_init_internal; + reg_ack_reply_internal <= got_ack_reply_internal; + reg_read_out <= next_read_out; + current_error_state <= next_error_state; end if; - end process; + end if; + end process; + + + +------------------------ +--FIFO Input +------------------------ - PROC_LED : process(CLK) + PROC_REG_INPUT : process(CLK) begin if rising_edge(CLK) then reg_med_data_in <= MED_DATA_IN; @@ -267,15 +204,54 @@ counter_match <= '1'; fifo_data_in <= reg_med_data_in; fifo_packet_num_in <= reg_med_packet_num_in(2) & reg_med_packet_num_in(0); ---regenerate long packet numbers - process(CLK) + + +------------------------ +--the input fifo +------------------------ + FIFO: trb_net16_fifo + generic map ( + DEPTH => DEPTH + ) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_data_in, + PACKET_NUM_IN => fifo_packet_num_in, + WRITE_ENABLE_IN => fifo_write, + DATA_OUT => comb_fifo_data_out, + PACKET_NUM_OUT => comb_fifo_packet_num_out, + READ_ENABLE_IN => fifo_read, + FULL_OUT => fifo_full, + EMPTY_OUT => fifo_empty + ); + + +------------------------ +--Register FIFO Output +------------------------ + + PROC_SYNC_FIFO_OUTPUTS : process(CLK) --register fifo output + begin + if rising_edge(CLK) then + fifo_valid_read <= fifo_read and not fifo_empty; + fifo_data_valid <= fifo_valid_read; + if fifo_valid_read = '1' then + fifo_data_out <= comb_fifo_data_out; + end if; + end if; + end process; + + + proc_make_full_packet_number : process(CLK) --generate packet number begin if rising_edge(CLK) then if RESET = '1' then fifo_long_packet_num_out <= (others => '0'); - elsif next_last_fifo_read = '1' then - fifo_long_packet_num_out(2) <= next_fifo_packet_num_out(1); - fifo_long_packet_num_out(0) <= next_fifo_packet_num_out(0); + elsif fifo_valid_read = '1' then + fifo_long_packet_num_out(2) <= comb_fifo_packet_num_out(1); + fifo_long_packet_num_out(0) <= comb_fifo_packet_num_out(0); if fifo_long_packet_num_out(2) = '0' and fifo_long_packet_num_out(0) = '1' then fifo_long_packet_num_out(1) <= not fifo_long_packet_num_out(1); else @@ -285,37 +261,33 @@ counter_match <= '1'; end if; end process; + + ------------------------ ---save the current packet type (including init/reply channel) +--save the current packet type from fifo output (including init/reply channel) ------------------------ - process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - saved_packet_type <= '1' & TYPE_ILLEGAL; - elsif MED_PACKET_NUM_IN = c_H0 then - saved_packet_type <= MED_DATA_IN(3 downto 0); - end if; - end if; - end process; process(CLK) begin if rising_edge(CLK) then if RESET = '1' then saved_fifo_packet_type <= '1' & TYPE_ILLEGAL; - elsif fifo_long_packet_num_out = c_H0 then + elsif fifo_long_packet_num_out = c_H0 and fifo_data_valid = '1' then saved_fifo_packet_type <= fifo_data_out(3 downto 0); end if; end if; end process; - --create comb. real packet type --- current_packet_type <= MED_DATA_IN(3 downto 0) when (MED_PACKET_NUM_IN = c_H0) --- else saved_packet_type; - current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_packet_num_out(1)='1')--fifo_long_packet_num_out = c_H0 + + current_fifo_packet_type <= fifo_data_out(3 downto 0) when (fifo_long_packet_num_out = c_H0 and fifo_data_valid = '1') else saved_fifo_packet_type; - gen_crc : if USE_CHECKSUM = 1 generate + + +------------------------ +--CRC check +------------------------ + + gen_crc : if USE_CHECKSUM = c_YES generate THE_CRC : trb_net_CRC port map( CLK => CLK, @@ -326,97 +298,153 @@ counter_match <= '1'; CRC_match => CRC_match ); - process(last_fifo_read, fifo_long_packet_num_out, current_fifo_packet_type, fifo_packet_num_out) + process(fifo_data_valid, fifo_long_packet_num_out, current_fifo_packet_type) begin - CRC_enable <= last_fifo_read and not fifo_packet_num_out(1); --not fifo_long_packet_num_out(2); - if current_fifo_packet_type(2 downto 0) = TYPE_TRM or (current_fifo_packet_type(2 downto 0) = TYPE_EOB) then + CRC_enable <= fifo_data_valid and not fifo_long_packet_num_out(2); + if (current_fifo_packet_type(2 downto 0) = TYPE_TRM or current_fifo_packet_type(2 downto 0) = TYPE_EOB) and fifo_long_packet_num_out /= c_F0 then CRC_enable <= '0'; end if; - if (current_fifo_packet_type(2 downto 0) = TYPE_EOB or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F0 then - CRC_enable <= last_fifo_read; - end if; end process; - end generate; PROC_SAVE_CRC_USED : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if RESET = '1' or (current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3) then CRC_active <= '0'; - else - if (last_fifo_read='1' and fifo_long_packet_num_out(2) = '0' and current_fifo_packet_type(2 downto 0) /= TYPE_TRM) or CRC_active = '1' then - CRC_active <= '1'; - else - CRC_active <= '0'; - end if; - if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3 then - CRC_active <= '0'; - end if; + elsif (CRC_enable = '1' and current_fifo_packet_type(2 downto 0) /= TYPE_TRM) then + CRC_active <= '1'; end if; end if; end process; - gen_no_crc : if USE_CHECKSUM = 0 generate + end generate; + + gen_no_crc : if USE_CHECKSUM = c_NO generate CRC_match <= '1'; + CRC_active <= '0'; end generate; + + ------------------------ ---control incoming data +--Handle FiFo output ------------------------ - FILTER_DATA_IN : process(reg_MED_DATA_IN, reg_MED_DATAREADY_IN, reg_MED_PACKET_NUM_IN, - fifo_full, current_rec_buffer_size_out, - current_error_state, reg_read_out, saved_packet_type) - begin -- process - got_ack_init_internal <= '0'; - got_ack_reply_internal <= '0'; - next_read_out <= not fifo_full; - fifo_write <= '0'; - next_rec_buffer_size_out <= current_rec_buffer_size_out; - next_error_state <= current_error_state; - if reg_MED_DATAREADY_IN = '1' and reg_read_out= '1' then - if saved_packet_type(2 downto 0) = TYPE_ACK and USE_ACKNOWLEDGE = 1 then - if reg_MED_PACKET_NUM_IN = c_H0 and current_error_state /= GOT_OVERFLOW_ERROR then - got_ack_init_internal <= not saved_packet_type(3); - got_ack_reply_internal <= saved_packet_type(3); - end if; - if reg_MED_PACKET_NUM_IN = c_F1 then - next_rec_buffer_size_out <= reg_MED_DATA_IN(3 downto 0); - end if; - elsif not (saved_packet_type(2 downto 0) = TYPE_ILLEGAL) then - fifo_write <= '1'; - if fifo_full = '1' then - next_error_state <= GOT_OVERFLOW_ERROR; + + process(fifo_data_out, fifo_long_packet_num_out, RESET, crc_active, + fifo_data_valid, current_fifo_packet_type, counter_match, + CRC_match, comb_next_init_read, comb_next_reply_read, + init_word_waiting, reply_word_waiting) + begin + + tmp_INT_DATA_OUT <= fifo_data_out; + tmp_INT_PACKET_NUM_OUT <= fifo_long_packet_num_out; + tmp_INT_INIT_DATAREADY_OUT <= '0'; + tmp_INT_REPLY_DATAREADY_OUT <= '0'; + got_eob_init_out <= '0'; + got_eob_reply_out <= '0'; + CRC_RESET <= RESET; + + --write error pattern + if USE_CHECKSUM = 1 then + if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F2 and CRC_active = '1' then + tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; + tmp_INT_DATA_OUT(4) <= fifo_data_out(4) or not counter_match; + end if; + end if; + + + fifo_read <= comb_next_init_read and comb_next_reply_read; + + + --write data to right sbuf + if (fifo_data_valid = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then + tmp_INT_INIT_DATAREADY_OUT <= not current_fifo_packet_type(3); + tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3); + else + tmp_INT_INIT_DATAREADY_OUT <= init_word_waiting; + tmp_INT_REPLY_DATAREADY_OUT <= reply_word_waiting; + end if; + + --trigger sending ACK + if fifo_data_valid = '1' then + if USE_ACKNOWLEDGE = 1 then + if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB + or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F3 then + got_eob_init_out <= not current_fifo_packet_type(3); + got_eob_reply_out <= current_fifo_packet_type(3); end if; end if; end if; + + if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F3 then + CRC_RESET <= '1'; + end if; end process; - MED_READ_OUT <= reg_read_out; - reg_buffer: process(CLK) + + + PROC_word_waiting : process(CLK) begin - if rising_edge(CLK) then - if RESET = '1' then - current_rec_buffer_size_out <= (others => '0'); - reg_ack_init_internal <= '0'; - reg_ack_reply_internal <= '0'; - reg_read_out <= '0'; - current_error_state <= IDLE; - elsif CLK_EN = '1' then - current_rec_buffer_size_out <= next_rec_buffer_size_out; - reg_ack_init_internal <= got_ack_init_internal; - reg_ack_reply_internal <= got_ack_reply_internal; - reg_read_out <= next_read_out; - current_error_state <= next_error_state; + if rising_edge(CLK) then + if RESET = '1' then + init_word_waiting <= '0'; + reply_word_waiting <= '0'; + else + if tmp_INT_INIT_DATAREADY_OUT = '1' and sbuf_init_free = '0' then + init_word_waiting <= '1'; + else + init_word_waiting <= '0'; + end if; + if tmp_INT_REPLY_DATAREADY_OUT = '1' and sbuf_reply_free = '0' then + reply_word_waiting <= '1'; + else + reply_word_waiting <= '0'; + end if; + end if; end if; - end if; - end process; + end process; + + gen_ack1 : if USE_ACKNOWLEDGE = 1 generate + proc_reg_eob_out: process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reg_eob_init_out <= '0'; + reg_eob_reply_out <= '0'; + elsif CLK_EN = '1' then + reg_eob_init_out <= got_eob_init_out; + reg_eob_reply_out <= got_eob_reply_out; + end if; + end if; + end process; + + proc_count_buffers : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + init_buffer_number <= (others => '1'); + reply_buffer_number <= (others => '1'); + elsif CLK_EN = '1' then + if reg_eob_init_out = '1' then + init_buffer_number <= init_buffer_number + 1; + end if; + if reg_eob_reply_out = '1' then + reply_buffer_number <= reply_buffer_number + 1; + end if; + end if; + end if; + end process; + end generate; + + + + ------------------------ ---generate output logic +--Output logic ------------------------ --- gensecure : if SECURE_MODE = 1 generate gen_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_YES generate SBUF_INIT: trb_net16_sbuf generic map ( @@ -428,7 +456,7 @@ counter_match <= '1'; CLK_EN => CLK_EN, COMB_DATAREADY_IN => tmp_INT_INIT_DATAREADY_OUT, COMB_next_READ_OUT => comb_next_init_read, - COMB_READ_IN => '1', + COMB_READ_IN => sbuf_init_free, COMB_DATA_IN => tmp_INT_DATA_OUT, COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT, SYN_DATAREADY_OUT => INT_INIT_DATAREADY_OUT, @@ -444,6 +472,7 @@ counter_match <= '1'; end if; end process; end generate; + gen_no_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_NO generate sbuf_init_free <= '1'; INT_INIT_DATA_OUT <= (others => '0'); @@ -464,7 +493,7 @@ counter_match <= '1'; CLK_EN => CLK_EN, COMB_DATAREADY_IN => tmp_INT_REPLY_DATAREADY_OUT, COMB_next_READ_OUT => comb_next_reply_read, - COMB_READ_IN => '1', + COMB_READ_IN => sbuf_reply_free, COMB_DATA_IN => tmp_INT_DATA_OUT, COMB_PACKET_NUM_IN => tmp_INT_PACKET_NUM_OUT, SYN_DATAREADY_OUT => INT_REPLY_DATAREADY_OUT, @@ -480,6 +509,7 @@ counter_match <= '1'; end if; end process; end generate; + gen_no_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_NO generate sbuf_reply_free <= '1'; INT_REPLY_DATA_OUT <= (others => '0'); @@ -488,141 +518,11 @@ counter_match <= '1'; stat_sbufs(1) <= '0'; comb_next_reply_read <= '1'; end generate; --- end generate; --- gen_notsecure : if SECURE_MODE = 0 generate --- INT_INIT_DATA_OUT <= tmp_INT_DATA_OUT; --- INT_INIT_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT; --- INT_INIT_DATAREADY_OUT <= tmp_INT_INIT_DATAREADY_OUT; --- sbuf_INIT_free <= INT_INIT_READ_IN; --- INT_REPLY_DATA_OUT <= tmp_INT_DATA_OUT; --- INT_REPLY_PACKET_NUM_OUT <= tmp_INT_PACKET_NUM_OUT; --- INT_REPLY_DATAREADY_OUT <= tmp_INT_REPLY_DATAREADY_OUT; --- sbuf_REPLY_free <= INT_REPLY_READ_IN; --- comb_next_init_read <= '1'; --- comb_next_reply_read <= '1'; --- stat_sbufs <= (others => '0'); --- end generate; - - - process(fifo_data_out, fifo_long_packet_num_out, sbuf_init_free, RESET, - fifo_empty, sbuf_reply_free, last_fifo_read, current_fifo_packet_type, - fifo_read_before, CRC_match, throw_away, comb_next_init_read, comb_next_reply_read, - next_last_fifo_read, fifo_value_waiting) - begin - - tmp_INT_DATA_OUT <= fifo_data_out; - tmp_INT_PACKET_NUM_OUT <= fifo_long_packet_num_out; - tmp_INT_INIT_DATAREADY_OUT <= '0'; - tmp_INT_REPLY_DATAREADY_OUT <= '0'; - got_eob_init_out <= '0'; - got_eob_reply_out <= '0'; - throw_away <= '0'; - CRC_RESET <= RESET; - - if USE_CHECKSUM = 1 then - if current_fifo_packet_type(2 downto 0) = TYPE_TRM and fifo_long_packet_num_out = c_F2 and CRC_active = '1' then - tmp_INT_DATA_OUT(3) <= fifo_data_out(3) or not CRC_match; - tmp_INT_DATA_OUT(4) <= fifo_data_out(4) or not counter_match; - CRC_RESET <= '1'; - end if; - end if; --- fifo_read <= not fifo_empty and not (fifo_read_before and not --- ((sbuf_init_free and not current_fifo_packet_type(3)) --- or (sbuf_reply_free and current_fifo_packet_type(3)) --- )); - fifo_read <= ((not fifo_read_before and not next_last_fifo_read) or (sbuf_init_free and sbuf_reply_free)) and not fifo_value_waiting; - - - if (fifo_read_before = '1' and (current_fifo_packet_type(2 downto 0) /= TYPE_EOB)) then --- if SECURE_MODE = 1 then - if INIT_CAN_RECEIVE_DATA = c_YES then - tmp_INT_INIT_DATAREADY_OUT <= (sbuf_init_free and sbuf_reply_free) and not current_fifo_packet_type(3); - end if; - if REPLY_CAN_RECEIVE_DATA = c_YES then - tmp_INT_REPLY_DATAREADY_OUT <= (sbuf_reply_free and sbuf_init_free) and current_fifo_packet_type(3); - end if; --- else --- tmp_INT_INIT_DATAREADY_OUT <= not current_fifo_packet_type(3); --- if REPLY_CAN_RECEIVE_DATA = c_YES then --- tmp_INT_REPLY_DATAREADY_OUT <= current_fifo_packet_type(3); --- end if; --- end if; - end if; - - if last_fifo_read = '1' then - if current_fifo_packet_type(2 downto 0) = TYPE_EOB then - throw_away <= '1'; - end if; - if USE_ACKNOWLEDGE = 1 then - if ( current_fifo_packet_type(2 downto 0) = TYPE_EOB - or current_fifo_packet_type(2 downto 0) = TYPE_TRM) and fifo_long_packet_num_out = c_F3 then - got_eob_init_out <= not current_fifo_packet_type(3); - got_eob_reply_out <= current_fifo_packet_type(3); - end if; - end if; - end if; - end process; - --- process(CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' then --- last_fifo_read <= '0'; --- else --- last_fifo_read <= fifo_read; --- end if; --- end if; --- end process; --- --- process(CLK) --- begin --- if rising_edge(CLK) then --- if RESET = '1' then --- fifo_read_before <= '0'; --- else --- if fifo_read = '1' then --- fifo_read_before <= '1'; --- elsif ( (sbuf_INIT_free and not current_fifo_packet_type(3)) --- or (sbuf_REPLY_free and current_fifo_packet_type(3)) or throw_away) = '1' then --- fifo_read_before <= '0'; --- end if; --- end if; --- end if; --- end process; - - gen_ack1 : if USE_ACKNOWLEDGE = 1 generate - proc_reg_eob_out: process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - reg_eob_init_out <= '0'; - reg_eob_reply_out <= '0'; - elsif CLK_EN = '1' then - reg_eob_init_out <= got_eob_init_out; - reg_eob_reply_out <= got_eob_reply_out; - end if; - end if; - end process; - - proc_count_buffers : process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - init_buffer_number <= (others => '1'); - reply_buffer_number <= (others => '1'); - elsif CLK_EN = '1' then - if reg_eob_init_out = '1' then - init_buffer_number <= init_buffer_number + 1; - end if; - if reg_eob_reply_out = '1' then - reply_buffer_number <= reply_buffer_number + 1; - end if; - end if; - end if; - end process; - end generate; +------------------------ +--Debugging Signals +------------------------ STAT_BUFFER_COUNTER <= reply_buffer_number & init_buffer_number; diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 23fe23e..e947d00 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -105,7 +105,6 @@ begin USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, USE_CHECKSUM => USE_CHECKSUM, SBUF_VERSION => SBUF_VERSION, - SECURE_MODE => IBUF_SECURE_MODE, INIT_CAN_RECEIVE_DATA => INIT_CAN_RECEIVE_DATA, REPLY_CAN_RECEIVE_DATA => REPLY_CAN_RECEIVE_DATA ) diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 2108f10..1704e99 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -126,6 +126,21 @@ package trb_net_components is + component trb_net_CRC is + port( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(15 downto 0); + CRC_OUT : out std_logic_vector(15 downto 0); + CRC_match : out std_logic + ); + end component; + + + + + component trb_net16_dummy_fifo is port ( CLK : in std_logic; @@ -276,47 +291,6 @@ package trb_net_components is - component trb_net16_ibuf is - generic ( - DEPTH : integer range 0 to 7 := c_FIFO_BRAM; - USE_VENDOR_CORES : integer range 0 to 1 := c_YES; - USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; - USE_CHECKSUM : integer range 0 to 1 := c_YES; - SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; - SECURE_MODE : integer range 0 to 1 := c_YES; - INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; - REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES - ); - port( - -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; - -- Media direction port - MED_DATAREADY_IN : in std_logic; - MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); - MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); - MED_READ_OUT : out std_logic; - MED_ERROR_IN : in std_logic_vector (2 downto 0); - -- Internal direction port - INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_INIT_DATAREADY_OUT : out std_logic; - INT_INIT_READ_IN : in std_logic; - INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); - INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); - INT_REPLY_DATAREADY_OUT : out std_logic; - INT_REPLY_READ_IN : in std_logic; - INT_ERROR_OUT : out std_logic_vector (2 downto 0); - -- Status and control port - STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); - STAT_BUFFER : out std_logic_vector (31 downto 0) - ); - end component; - - - - @@ -351,6 +325,10 @@ package trb_net_components is + + + + component trb_net16_fifo is generic ( USE_VENDOR_CORES : integer range 0 to 1 := c_NO; @@ -380,6 +358,55 @@ package trb_net_components is + + component trb_net16_ibuf is + generic ( + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_READ_IN : in std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_READ_IN : in std_logic; + INT_ERROR_OUT : out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0) + ); + end component; + + + + + + + + + + + + component trb_net16_iobuf is generic ( IBUF_DEPTH : integer range 0 to 6 := c_FIFO_BRAM;--std_FIFO_DEPTH; @@ -442,6 +469,8 @@ package trb_net_components is + + component trb_net16_io_multiplexer is port( -- Misc @@ -525,6 +554,9 @@ package trb_net_components is + + + component trb_net16_med_8_SDR_OS is generic( TRANSMISSION_CLOCK_DIV: integer range 1 to 10 := 1 @@ -603,6 +635,10 @@ package trb_net_components is + + + + component trb_net16_med_ecp_fot_4 is port( CLK : in std_logic; @@ -782,6 +818,8 @@ package trb_net_components is + + component trb_net_onewire_listener is port( CLK : in std_logic; @@ -890,37 +928,20 @@ package trb_net_components is - component signal_sync is - generic( - WIDTH : integer := 1; -- - DEPTH : integer := 3 - ); - port( - RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register - CLK0 : in std_logic; --clock for first FF - CLK1 : in std_logic; --Clock for other FF - D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input - D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output - ); - end component; - - - - component trb_net_priority_arbiter is generic ( - WIDTH : integer := 1 + WIDTH : integer := 2 ); port( -- Misc - CLK : in std_logic; - RESET : in std_logic; - CLK_EN : in std_logic; + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; INPUT_IN : in STD_LOGIC_VECTOR (WIDTH-1 downto 0); RESULT_OUT: out STD_LOGIC_VECTOR (WIDTH-1 downto 0); - ENABLE : in std_logic; - CTRL : in STD_LOGIC_VECTOR (9 downto 0) + ENABLE : in std_logic; + CTRL: in STD_LOGIC_VECTOR (9 downto 0) ); end component; @@ -928,6 +949,8 @@ package trb_net_components is + + component ram_dp is generic( depth : integer := 3; @@ -1105,6 +1128,34 @@ package trb_net_components is + + + + + + + + + component signal_sync is + generic( + WIDTH : integer := 1; -- + DEPTH : integer := 3 + ); + port( + RESET : in std_logic; --Reset is neceessary to avoid optimization to shift register + CLK0 : in std_logic; --clock for first FF + CLK1 : in std_logic; --Clock for other FF + D_IN : in std_logic_vector(WIDTH-1 downto 0); --Data input + D_OUT : out std_logic_vector(WIDTH-1 downto 0) --Data output + ); + end component; + + + + + + + component trb_net16_term is generic ( USE_APL_PORT : integer range 0 to 1 := c_YES; -- 2.43.0