From 1dc6fa979e62ec5bede250ccf4706a78218acc8d Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 6 Aug 2010 13:03:12 +0000 Subject: [PATCH] *** empty log message *** --- gbe.tex | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/gbe.tex b/gbe.tex index b9819a9..08e015a 100644 --- a/gbe.tex +++ b/gbe.tex @@ -1,4 +1,4 @@ -Gigabit Ethernet is a verified and a weel known standard for data transmission over Ethernet networks at speed of 1Gbps using both optic fibers and standard UTP cables. It's implementation on TRB Addon boards is a gateway for collected data into event builders via Ethernet network. Entity trb_net16_gbe_buf is the interface between TRBNet streaming API and the UDP packet construction logic. +Gigabit Ethernet is a verified and a weel known standard for data transmission over Ethernet networks at speed of 1Gbps using both optic fibers and standard UTP cables. It's implementation on TRB Addon boards is a gateway for collected data into event builders via Ethernet network. Entity \filename{trb\_net16\_gbe\_buf} is the interface between TRBNet streaming API and the UDP packet construction logic. Current design allows to send data with maximum speed of 400Mbps. Each subevent is sent in one UDP packet. The maximum size of a packet is 65535B. In order to control the size of incoming subevents, two registers can be set which describe the minimum and the maximum size of an accepted subevent. Te ones that will not fit between those two values, will be marked as incorrect and sent to the network. GbE logic performes the check of incoming subevent headers consistency. When the structure or the values are incorrect, the subevent is also marked and sent to event builders. The bit nr. 26 in error vector at the end of subevent signalizes incorrect subevent. @@ -93,7 +93,7 @@ The GbE interface itself has two registers to control the link status, available \subsection{Debugging} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -For debug purpose a set of registers has been prepared, started from address 0x83E0 to 0x83F2 with meaning described in table \ref{GbEDebugRegisters}. While those registers can be read by hand using trbcmd command, a tool gbe_debug_parser.pl is provided to parse the output and display status in clear text. The parser reads out the registers of all GbE enabled and actually connected hubs. +For debug purpose a set of registers has been prepared, started from address 0x83E0 to 0x83F2 with meaning described in table \ref{GbEDebugRegisters}. While those registers can be read by hand using trbcmd command, a tool \filename{gbe\_debug\_parser.pl} is provided to parse the output and display status in clear text. The parser reads out the registers of all GbE enabled and actually connected hubs. \begin{table}[hbtp] \begin{center} @@ -101,7 +101,7 @@ For debug purpose a set of registers has been prepared, started from address 0x8 \hline \textbf{Address} & \textbf{Name} & \textbf{Description} \\ \hline\hline -0x83E0 & ipu2gbe1 & Bit 0: sf_full, Bit 1: sf_empty, Bit 2: sf_afull, Bit 3: sf_aempty, Bit 7..4: load machine state, Bit 11..8: save machine state, Bit 15..12: bank selected, Bit 16: conf_done, Bit 17: remove done, Bit 18: read_done, Bit 19: padding needed, Bit 20: load sub done \\ +0x83E0 & ipu2gbe1 & Bit 0: sf full, Bit 1: sf empty, Bit 2: sf afull, Bit 3: sf aempty, Bit 7..4: load machine state, Bit 11..8: save machine state, Bit 15..12: bank selected, Bit 16: conf done, Bit 17: remove done, Bit 18: read done, Bit 19: padding needed, Bit 20: load sub done \\ 0x83E1 & ipu2gbe2 & Bit 7..0: cts information, Bit 31..16: actual message size \\ 0x83E2 & packetConstr1 & Bit 3..0: construction state, Bit 7..4: save headers state, Bit 11..8: load state, Bit 27..12: queue size, Bit 28: df full, Bit 29: df empty, Bit 30: shf full, Bit 31: shf empty \\ 0x83E3 & packetContsr2 & Bit 15..0: size left, Bit 24..16:all ctr, Bit 25: pc ready \\ @@ -126,16 +126,16 @@ For debug purpose a set of registers has been prepared, started from address 0x8 \end{center} \end{table} -Gbe_monitor.pl is another tool to monitor the status of GbE hubs in the system. It provides information about transmission rates, link status and constructed events counters. Transmission rate is measured as the number of bytes sent from board into the network, it can vary from the one measured at the receiving point due to network issues. +\filename{Gbe\_monitor.pl} is another tool to monitor the status of GbE hubs in the system. It provides information about transmission rates, link status and constructed events counters. Transmission rate is measured as the number of bytes sent from board into the network, it can vary from the one measured at the receiving point due to network issues. %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{Implementation notes} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -Construction and transmission logic runs on 125MHz clock which has to be provided into gbe_buf entity in one of two provided ways: -- 125MHz oscillator is directly connected to SERDES unit: USE_125MHZ_EXTCLK generic value has to be set to 1, then the input port CLK_125_IN is not used, and signal is received from reference clock output of SERDES inside gbe_buf logic (the case of HUB2 addon). -- 125MHz clock signal is connected to FPGA pins: USE_125MHZ_EXTCLK generic value has to be set to 0 and the port CLK_125_IN has to be connected to signal provided by FPGA logic (the case of Shower, MDC and CTS addons). +Construction and transmission logic runs on 125MHz clock which has to be provided into \filename{gbe\_buf} entity in one of two provided ways: +- 125MHz oscillator is directly connected to Serdes unit: \genericname{Use\_125Mhz\_Extclk} generic value has to be set to 1, then the input port \portname{Clk\_125\_In} is not used, and signal is received from reference clock output of Serdes inside \filename{gbe\_buf} logic (the case of HUB2 addon). +- 125MHz clock signal is connected to FPGA pins: \genericname{Use\_125Mhz\_Extclk} generic value has to be set to 0 and the port \portname{Clk\_125\_In} has to be connected to signal provided by FPGA logic (the case of Shower, MDC and CTS addons). While generating a new PCS unit in IPExpress there are two things to care about: - Gigabit Ethernet has to be chosen as the quad protocol mode -- CTC_BYP entry in generated .txt file has to be changed by hand from NORMAL to BYPASS in order to allow the proper operation of SGMII/GBE PCS IPCore. +- CTC\_BYP entry in generated .txt file has to be changed by hand from NORMAL to BYPASS in order to allow the proper operation of SGMII/GBE PCS IPCore. -- 2.43.0