From 1e8ba23fdd6fe95cd139ddcfc9e5bce05666148b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 29 Jan 2013 14:52:48 +0000 Subject: [PATCH] added new 18x16_dualport_oreg, JM --- .../lattice_ecp3_fifo_18x16_dualport_oreg.ipx | 9 + .../lattice_ecp3_fifo_18x16_dualport_oreg.lpc | 47 + .../lattice_ecp3_fifo_18x16_dualport_oreg.vhd | 1040 +++++++++++++++++ 3 files changed, 1096 insertions(+) create mode 100644 lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.ipx create mode 100644 lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.lpc create mode 100644 lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd diff --git a/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.ipx b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.ipx new file mode 100644 index 0000000..ab4de65 --- /dev/null +++ b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.lpc b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.lpc new file mode 100644 index 0000000..64bb69e --- /dev/null +++ b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-6FN1156C +SpeedGrade=6 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.4 +ModuleName=lattice_ecp3_fifo_18x16_dualport_oreg +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=01/29/2013 +Time=15:48:26 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=LUT Based +Depth=16 +Width=18 +RDepth=16 +RWidth=18 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=1 +PfMode=Static - Single Threshold +PfAssert=7 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd new file mode 100644 index 0000000..4799cbf --- /dev/null +++ b/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd @@ -0,0 +1,1040 @@ +-- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- Module Version: 5.4 +--/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -pfu_fifo -depth 16 -width 18 -depth 16 -rdata_width 18 -regout -no_enable -pe -1 -pf 7 -e + +-- Tue Jan 29 15:48:26 2013 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity lattice_ecp3_fifo_18x16_dualport_oreg is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostFull: out std_logic); +end lattice_ecp3_fifo_18x16_dualport_oreg; + +architecture Structure of lattice_ecp3_fifo_18x16_dualport_oreg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal wptr_4: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal rptr_4: std_logic; + signal edataout0: std_logic; + signal edataout1: std_logic; + signal edataout2: std_logic; + signal edataout3: std_logic; + signal edataout4: std_logic; + signal edataout5: std_logic; + signal edataout6: std_logic; + signal edataout7: std_logic; + signal edataout8: std_logic; + signal edataout9: std_logic; + signal edataout10: std_logic; + signal edataout11: std_logic; + signal edataout12: std_logic; + signal edataout13: std_logic; + signal edataout14: std_logic; + signal edataout15: std_logic; + signal edataout16: std_logic; + signal edataout17: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal co2: std_logic; + signal wcount_4: std_logic; + signal co1: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal co2_1: std_logic; + signal rcount_4: std_logic; + signal co1_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal wcount_r3: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal cmp_ci_1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vhi: std_logic; + signal iaf_setcount_0: std_logic; + signal iaf_setcount_1: std_logic; + signal af_set_ctr_ci: std_logic; + signal iaf_setcount_2: std_logic; + signal iaf_setcount_3: std_logic; + signal co0_4: std_logic; + signal iaf_setcount_4: std_logic; + signal co2_2: std_logic; + signal af_setcount_4: std_logic; + signal co1_4: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal rcount_w0: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal af_setcount_0: std_logic; + signal af_setcount_1: std_logic; + signal co0_5: std_logic; + signal rcount_w2: std_logic; + signal rcount_w3: std_logic; + signal af_setcount_2: std_logic; + signal af_setcount_3: std_logic; + signal co1_5: std_logic; + signal af_set_cmp_clr: std_logic; + signal af_set_cmp_set: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; + signal rdataout17: std_logic; + signal rdataout16: std_logic; + signal scuba_vlo: std_logic; + signal rdataout15: std_logic; + signal rdataout14: std_logic; + signal rdataout13: std_logic; + signal rdataout12: std_logic; + signal rdataout11: std_logic; + signal rdataout10: std_logic; + signal rdataout9: std_logic; + signal rdataout8: std_logic; + signal rdataout7: std_logic; + signal rdataout6: std_logic; + signal rdataout5: std_logic; + signal rdataout4: std_logic; + signal rdataout3: std_logic; + signal rdataout2: std_logic; + signal rdataout1: std_logic; + signal rdataout0: std_logic; + signal rptr_3: std_logic; + signal rptr_2: std_logic; + signal rptr_1: std_logic; + signal rptr_0: std_logic; + signal dec0_wre3: std_logic; + signal wptr_3: std_logic; + signal wptr_2: std_logic; + signal wptr_1: std_logic; + signal wptr_0: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1A + generic (INITVAL : in std_logic_vector(15 downto 0)); + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component DPR16X4C + generic (INITVAL : in String); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; WCK: in std_logic; WRE: in std_logic; + RAD0: in std_logic; RAD1: in std_logic; + RAD2: in std_logic; RAD3: in std_logic; + WAD0: in std_logic; WAD1: in std_logic; + WAD2: in std_logic; WAD3: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + attribute GSR : string; + attribute MEM_INIT_FILE : string; + attribute MEM_LPC_FILE : string; + attribute COMP : string; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute MEM_INIT_FILE of fifo_pfu_0_0 : label is "(0-15)(0-3)"; + attribute MEM_LPC_FILE of fifo_pfu_0_0 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; + attribute COMP of fifo_pfu_0_0 : label is "fifo_pfu_0_0"; + attribute MEM_INIT_FILE of fifo_pfu_0_1 : label is "(0-15)(4-7)"; + attribute MEM_LPC_FILE of fifo_pfu_0_1 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; + attribute COMP of fifo_pfu_0_1 : label is "fifo_pfu_0_1"; + attribute MEM_INIT_FILE of fifo_pfu_0_2 : label is "(0-15)(8-11)"; + attribute MEM_LPC_FILE of fifo_pfu_0_2 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; + attribute COMP of fifo_pfu_0_2 : label is "fifo_pfu_0_2"; + attribute MEM_INIT_FILE of fifo_pfu_0_3 : label is "(0-15)(12-15)"; + attribute MEM_LPC_FILE of fifo_pfu_0_3 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; + attribute COMP of fifo_pfu_0_3 : label is "fifo_pfu_0_3"; + attribute MEM_INIT_FILE of fifo_pfu_0_4 : label is "(0-15)(16-17)"; + attribute MEM_LPC_FILE of fifo_pfu_0_4 : label is "lattice_ecp3_fifo_18x16_dualport_oreg.lpc"; + attribute COMP of fifo_pfu_0_4 : label is "fifo_pfu_0_4"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t10: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t9: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t8: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t7: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t6: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t5: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t4: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t3: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t2: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t1: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t0: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + LUT4_14: ROM16X1A + generic map (initval=> X"8000") + port map (AD3=>scuba_vhi, AD2=>wren_i, AD1=>scuba_vhi, + AD0=>scuba_vhi, DO0=>dec0_wre3); + + LUT4_13: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>w_gcount_r24, + DO0=>w_g2b_xor_cluster_0); + + LUT4_12: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r3); + + LUT4_11: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>scuba_vlo, DO0=>wcount_r2); + + LUT4_10: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>wcount_r3, DO0=>wcount_r0); + + LUT4_9: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>r_gcount_w24, + DO0=>r_g2b_xor_cluster_0); + + LUT4_8: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w3); + + LUT4_7: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>scuba_vlo, DO0=>rcount_w2); + + LUT4_6: ROM16X1A + generic map (initval=> X"6996") + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>rcount_w3, DO0=>rcount_w0); + + LUT4_5: ROM16X1A + generic map (initval=> X"0410") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_4: ROM16X1A + generic map (initval=> X"1004") + port map (AD3=>rptr_4, AD2=>rcount_4, AD1=>w_gcount_r24, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_3: ROM16X1A + generic map (initval=> X"0140") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_2: ROM16X1A + generic map (initval=> X"4001") + port map (AD3=>wptr_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + LUT4_1: ROM16X1A + generic map (initval=> X"4c32") + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_set); + + LUT4_0: ROM16X1A + generic map (initval=> X"8001") + port map (AD3=>af_setcount_4, AD2=>wcount_4, AD1=>r_gcount_w24, + AD0=>wptr_4, DO0=>af_set_cmp_clr); + + FF_93: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_92: FD1P3DX + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_91: FD1P3DX + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_90: FD1P3DX + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_89: FD1P3DX + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_88: FD1P3DX + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_87: FD1P3DX + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_86: FD1P3DX + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_85: FD1P3DX + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_84: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_83: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_82: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_81: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_80: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_79: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_78: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_77: FD1P3DX + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_76: FD1P3DX + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_75: FD1P3DX + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_74: FD1P3DX + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_73: FD1P3DX + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_72: FD1P3DX + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_71: FD1P3DX + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_70: FD1P3DX + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_69: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_68: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_67: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_66: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_65: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_64: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_63: FD1P3DX + port map (D=>edataout0, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_62: FD1P3DX + port map (D=>rdataout0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout0); + + FF_61: FD1P3DX + port map (D=>edataout1, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_60: FD1P3DX + port map (D=>rdataout1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout1); + + FF_59: FD1P3DX + port map (D=>edataout2, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_58: FD1P3DX + port map (D=>rdataout2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout2); + + FF_57: FD1P3DX + port map (D=>edataout3, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_56: FD1P3DX + port map (D=>rdataout3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout3); + + FF_55: FD1P3DX + port map (D=>edataout4, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_54: FD1P3DX + port map (D=>rdataout4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout4); + + FF_53: FD1P3DX + port map (D=>edataout5, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_52: FD1P3DX + port map (D=>rdataout5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout5); + + FF_51: FD1P3DX + port map (D=>edataout6, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_50: FD1P3DX + port map (D=>rdataout6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout6); + + FF_49: FD1P3DX + port map (D=>edataout7, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_48: FD1P3DX + port map (D=>rdataout7, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout7); + + FF_47: FD1P3DX + port map (D=>edataout8, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_46: FD1P3DX + port map (D=>rdataout8, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout8); + + FF_45: FD1P3DX + port map (D=>edataout9, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_44: FD1P3DX + port map (D=>rdataout9, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout9); + + FF_43: FD1P3DX + port map (D=>edataout10, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_42: FD1P3DX + port map (D=>rdataout10, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout10); + + FF_41: FD1P3DX + port map (D=>edataout11, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_40: FD1P3DX + port map (D=>rdataout11, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout11); + + FF_39: FD1P3DX + port map (D=>edataout12, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_38: FD1P3DX + port map (D=>rdataout12, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout12); + + FF_37: FD1P3DX + port map (D=>edataout13, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_36: FD1P3DX + port map (D=>rdataout13, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout13); + + FF_35: FD1P3DX + port map (D=>edataout14, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_34: FD1P3DX + port map (D=>rdataout14, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout14); + + FF_33: FD1P3DX + port map (D=>edataout15, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_32: FD1P3DX + port map (D=>rdataout15, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout15); + + FF_31: FD1P3DX + port map (D=>edataout16, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(16)); + + FF_30: FD1P3DX + port map (D=>rdataout16, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout16); + + FF_29: FD1P3DX + port map (D=>edataout17, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(17)); + + FF_28: FD1P3DX + port map (D=>rdataout17, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>edataout17); + + FF_27: FD1S3DX + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_26: FD1S3DX + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_25: FD1S3DX + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_24: FD1S3DX + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_23: FD1S3DX + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_22: FD1S3DX + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_21: FD1S3DX + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_20: FD1S3DX + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_19: FD1S3DX + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_18: FD1S3DX + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_17: FD1S3DX + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_16: FD1S3DX + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_15: FD1S3DX + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_14: FD1S3DX + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_13: FD1S3DX + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_12: FD1S3DX + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_11: FD1S3DX + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_10: FD1S3DX + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_9: FD1S3DX + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_8: FD1S3DX + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_7: FD1S3BX + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_6: FD1S3DX + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + FF_5: FD1P3DX + port map (D=>iaf_setcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_0); + + FF_4: FD1P3BX + port map (D=>iaf_setcount_1, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_1); + + FF_3: FD1P3DX + port map (D=>iaf_setcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_2); + + FF_2: FD1P3BX + port map (D=>iaf_setcount_3, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>af_setcount_3); + + FF_1: FD1P3DX + port map (D=>iaf_setcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>af_setcount_4); + + FF_0: FD1S3DX + port map (D=>af_set, CK=>WrClock, CD=>Reset, Q=>AlmostFull); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>scuba_vlo, CO=>co2, + NC0=>iwcount_4, NC1=>open); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>scuba_vlo, CO=>co2_1, + NC0=>ircount_4, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>w_g2b_xor_cluster_0, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>wcount_r3, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co1_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co1_3, GE=>full_d_c); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + af_set_ctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>af_set_ctr_ci, S0=>open, + S1=>open); + + af_set_ctr_0: CU2 + port map (CI=>af_set_ctr_ci, PC0=>af_setcount_0, + PC1=>af_setcount_1, CO=>co0_4, NC0=>iaf_setcount_0, + NC1=>iaf_setcount_1); + + af_set_ctr_1: CU2 + port map (CI=>co0_4, PC0=>af_setcount_2, PC1=>af_setcount_3, + CO=>co1_4, NC0=>iaf_setcount_2, NC1=>iaf_setcount_3); + + af_set_ctr_2: CU2 + port map (CI=>co1_4, PC0=>af_setcount_4, PC1=>scuba_vlo, + CO=>co2_2, NC0=>iaf_setcount_4, NC1=>open); + + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); + + af_set_cmp_0: AGEB2 + port map (A0=>af_setcount_0, A1=>af_setcount_1, B0=>rcount_w0, + B1=>r_g2b_xor_cluster_0, CI=>cmp_ci_2, GE=>co0_5); + + af_set_cmp_1: AGEB2 + port map (A0=>af_setcount_2, A1=>af_setcount_3, B0=>rcount_w2, + B1=>rcount_w3, CI=>co0_5, GE=>co1_5); + + af_set_cmp_2: AGEB2 + port map (A0=>af_set_cmp_set, A1=>scuba_vlo, B0=>af_set_cmp_clr, + B1=>scuba_vlo, CI=>co1_5, GE=>af_set_c); + + a2: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + fifo_pfu_0_0: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(16), DI1=>Data(17), DI2=>scuba_vlo, + DI3=>scuba_vlo, WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout16, + DO1=>rdataout17, DO2=>open, DO3=>open); + + fifo_pfu_0_1: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(12), DI1=>Data(13), DI2=>Data(14), + DI3=>Data(15), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout12, + DO1=>rdataout13, DO2=>rdataout14, DO3=>rdataout15); + + fifo_pfu_0_2: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(8), DI1=>Data(9), DI2=>Data(10), + DI3=>Data(11), WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, + RAD1=>rptr_1, RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, + WAD1=>wptr_1, WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout8, + DO1=>rdataout9, DO2=>rdataout10, DO3=>rdataout11); + + fifo_pfu_0_3: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(4), DI1=>Data(5), DI2=>Data(6), DI3=>Data(7), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout4, DO1=>rdataout5, + DO2=>rdataout6, DO3=>rdataout7); + + fifo_pfu_0_4: DPR16X4C + generic map (initval=> "0x0000000000000000") + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + WCK=>WrClock, WRE=>dec0_wre3, RAD0=>rptr_0, RAD1=>rptr_1, + RAD2=>rptr_2, RAD3=>rptr_3, WAD0=>wptr_0, WAD1=>wptr_1, + WAD2=>wptr_2, WAD3=>wptr_3, DO0=>rdataout0, DO1=>rdataout1, + DO2=>rdataout2, DO3=>rdataout3); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of lattice_ecp3_fifo_18x16_dualport_oreg is + for Structure + for all:AGEB2 use entity ecp3.AGEB2(V); end for; + for all:AND2 use entity ecp3.AND2(V); end for; + for all:CU2 use entity ecp3.CU2(V); end for; + for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; + for all:INV use entity ecp3.INV(V); end for; + for all:OR2 use entity ecp3.OR2(V); end for; + for all:ROM16X1A use entity ecp3.ROM16X1A(V); end for; + for all:DPR16X4C use entity ecp3.DPR16X4C(V); end for; + for all:VHI use entity ecp3.VHI(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + for all:XOR2 use entity ecp3.XOR2(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on -- 2.43.0