From 1f8beba9290ce159ae77ffe1ac7683cb8eda8f4f Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 26 Jul 2017 18:25:01 +0200 Subject: [PATCH] Add option to not use external clock - needed for ADC AddOn --- code/clock_reset_handler.vhd | 86 +++++++++++++++++++++--------------- 1 file changed, 50 insertions(+), 36 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index fe4a104..798ab76 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -50,6 +50,8 @@ signal clock_select : std_logic := '0'; signal timer : unsigned(27 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i : std_logic; +signal debug_reset_handler : std_logic_vector(15 downto 0); + attribute syn_keep of clear_n_i : signal is true; attribute syn_preserve of clear_n_i : signal is true; @@ -115,15 +117,17 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate LOCK => pll_int_lock ); - THE_EXT_PLL : entity work.pll_in200_out100 - port map( - CLK => EXT_CLK_IN, - RESET => '0', - CLKOP => open, --100 - CLKOS => clk_ext_half, --same as OP, but for DCS - CLKOK => clk_ext_full, --200, bypassed - LOCK => pll_ext_lock - ); + gen_ext_pll : if USE_EXTERNAL_CLOCK = c_YES generate + THE_EXT_PLL : entity work.pll_in200_out100 + port map( + CLK => EXT_CLK_IN, + RESET => '0', + CLKOP => open, --100 + CLKOS => clk_ext_half, --same as OP, but for DCS + CLKOK => clk_ext_full, --200, bypassed + LOCK => pll_ext_lock + ); + end generate; end generate; gen_240 : if USE_120_MHZ = c_YES generate @@ -135,33 +139,42 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate LOCK => pll_int_lock ); - THE_EXT_PLL : entity work.pll_in240_out240 - port map( - CLK => EXT_CLK_IN, - CLKOP => clk_ext_half, - CLKOK => clk_ext_full, - LOCK => pll_ext_lock - ); + gen_ext_pll : if USE_EXTERNAL_CLOCK = c_YES generate + THE_EXT_PLL : entity work.pll_in240_out240 + port map( + CLK => EXT_CLK_IN, + CLKOP => clk_ext_half, + CLKOK => clk_ext_full, + LOCK => pll_ext_lock + ); + end generate; end generate; --------------------------------------------------------------------------- -- Select clocks --------------------------------------------------------------------------- - THE_CLOCK_SWITCH_FULL: DCS - port map( - SEL => clock_select, - CLK0 => clk_int_full, - CLK1 => clk_ext_full, - DCSOUT => clk_selected_full - ); - THE_CLOCK_SWITCH_HALF: DCS - port map( - SEL => clock_select, - CLK0 => clk_int_half, - CLK1 => clk_ext_half, - DCSOUT => clk_selected_half - ); + gen_switch_clock : if USE_EXTERNAL_CLOCK = c_YES generate + THE_CLOCK_SWITCH_FULL: DCS + port map( + SEL => clock_select, + CLK0 => clk_int_full, + CLK1 => clk_ext_full, + DCSOUT => clk_selected_full + ); + THE_CLOCK_SWITCH_HALF: DCS + port map( + SEL => clock_select, + CLK0 => clk_int_half, + CLK1 => clk_ext_half, + DCSOUT => clk_selected_half + ); + end generate; + gen_direct_clock : if USE_EXTERNAL_CLOCK = c_NO generate + clk_selected_half <= clk_int_half; + clk_selected_full <= clk_int_full; + end generate; + --------------------------------------------------------------------------- -- Clock switch logic @@ -205,7 +218,7 @@ THE_RESET_HANDLER : trb_net_reset_handler TRB_RESET_IN => RESET_FROM_NET, -- TRBnet reset signal (SYSCLK) CLEAR_OUT => CLEAR_OUT, -- async reset out, USE WITH CARE! RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) - DEBUG_OUT => open + DEBUG_OUT => debug_reset_handler ); RESET_OUT <= reset_i; @@ -224,10 +237,11 @@ RESET_OUT <= reset_i; DEBUG_OUT(0) <= pll_int_lock; -DEBUG_OUT(1) <= pll_ext_lock; -DEBUG_OUT(2) <= clock_select; -DEBUG_OUT(3) <= clear_n_i; -DEBUG_OUT(31 downto 4) <= (others => '0'); +DEBUG_OUT(1) <= clear_n_i; +DEBUG_OUT(13 downto 2) <= debug_reset_handler(13 downto 2); +DEBUG_OUT(14) <= pll_ext_lock; +DEBUG_OUT(15) <= clock_select; +DEBUG_OUT(31 downto 16) <= (others => '0'); BUS_TX.data <= (others => '0'); BUS_TX.unknown <= '1'; @@ -236,4 +250,4 @@ BUS_TX.nack <= '0'; -end architecture; \ No newline at end of file +end architecture; -- 2.43.0