From 1fbca34cdd12cd70d545dfd1905c8d3391f4f8d3 Mon Sep 17 00:00:00 2001 From: palka Date: Wed, 16 Jan 2008 14:10:37 +0000 Subject: [PATCH] changing names of entity port --- optical_link/flexi_PCS_synch.vhd | 46 +++++++++++++++++++------------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd index c4f94e3..b938db4 100644 --- a/optical_link/flexi_PCS_synch.vhd +++ b/optical_link/flexi_PCS_synch.vhd @@ -10,22 +10,27 @@ use work.all; entity flexi_PCS_synch is generic ( - HOW_MANY_CHANNELS : positive); + HOW_MANY_CHANNELS : positive); port ( - CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); - RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - RESET : in std_logic; - RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); - CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - TXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); - TX_FORCE_DISP : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); - DATA_VALID_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - DATA_VALID_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); - FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0) + CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)-1 downto 0); + RX_CLK : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + RESET : in std_logic; + RXD : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + MED_DATA_OUT : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + RX_K : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + RX_RST : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*4-1 downto 0); + CV : in std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + MED_DATA_IN : in std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + TXD_SYNCH : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*64-1 downto 0); + TX_FORCE_DISP : out std_logic_vector(((HOW_MANY_CHANNELS+3)/4)*8-1 downto 0); + MED_DATAREADY_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_DATAREADY_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + FLEXI_PCS_SYNCH_STATUS : out std_logic_vector(HOW_MANY_CHANNELS*16-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0); + MED_PACKET_NUM_OUT : out std_logic_vector(HOW_MANY_CHANNELS*2-1 downto 0); + MED_READ_IN : in std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_READ_OUT : out std_logic_vector(HOW_MANY_CHANNELS-1 downto 0); + MED_ERROR_OUT : out std_logic_vector(HOW_MANY_CHANNELS*3-1 downto 0) ); end flexi_PCS_synch; architecture flexi_PCS_synch of flexi_PCS_synch is @@ -49,22 +54,25 @@ architecture flexi_PCS_synch of flexi_PCS_synch is begin CHANNEL_GENERATE : for bit_index in 0 to HOW_MANY_CHANNELS-1 generate begin + MED_READ_OUT <= (others => '1'); + MED_ERROR_OUT <= (others => '0'); SYNCH :flexi_PCS_channel_synch port map ( CLK => CLK(bit_index/4), --4 different channles clk RX_CLK => RX_CLK(bit_index), RESET => RESET, RXD => RXD((bit_index*16+15) downto bit_index*16), - RXD_SYNCH => RXD_SYNCH((bit_index*16+15) downto bit_index*16), + RXD_SYNCH => MED_DATA_OUT((bit_index*16+15) downto bit_index*16), RX_K => RX_K(bit_index*2+1 downto bit_index*2), RX_RST => RX_RST(bit_index), CV => CV((bit_index*2+1) downto bit_index*2), - TXD => TXD((bit_index*16+15) downto bit_index*16), + TXD => MED_DATA_IN((bit_index*16+15) downto bit_index*16), TXD_SYNCH => TXD_SYNCH((bit_index*16+15) downto bit_index*16), TX_FORCE_DISP => TX_FORCE_DISP(bit_index*2+1 downto bit_index*2), - DATA_VALID_IN => DATA_VALID_IN(bit_index), - DATA_VALID_OUT => DATA_VALID_OUT(bit_index), + DATA_VALID_IN => MED_DATAREADY_IN(bit_index), + DATA_VALID_OUT => MED_DATAREADY_OUT(bit_index), FLEXI_PCS_STATUS => FLEXI_PCS_SYNCH_STATUS((bit_index*16+15) downto bit_index*16) ); end generate CHANNEL_GENERATE; + end flexi_PCS_synch; -- 2.43.0