From 201517eabc30afc7a67331eeecbb023924f291b4 Mon Sep 17 00:00:00 2001 From: Rene Hagdorn Date: Tue, 18 Dec 2018 10:35:48 +0100 Subject: [PATCH] reworked DataDecoder --- mupix/Mupix8/sources/Datapath/DataDecoder.vhd | 178 ++++++++++-------- 1 file changed, 96 insertions(+), 82 deletions(-) diff --git a/mupix/Mupix8/sources/Datapath/DataDecoder.vhd b/mupix/Mupix8/sources/Datapath/DataDecoder.vhd index 9f1415d..15f67c6 100644 --- a/mupix/Mupix8/sources/Datapath/DataDecoder.vhd +++ b/mupix/Mupix8/sources/Datapath/DataDecoder.vhd @@ -11,27 +11,27 @@ use IEEE.NUMERIC_STD.ALL; entity DataDecoder is generic ( - D_W : integer := 32; -- width of full data word - Pix_W : integer := 8; -- col/row address width - ToT_W : integer := 6; -- time over threshold width - TS_W : integer := 10; -- timestamp width - LINKS : integer := 4 -- number of links (data + counters) + DWidth : integer := 32; -- width of full data word + PixWidth : integer := 8; -- col/row address width + ToTWidth : integer := 6; -- time over threshold width + TSWidth : integer := 10; -- timestamp width + LINKS : integer := 4 -- number of links (data + counters) ); port ( clk : in std_logic; reset : in std_logic; bypass : in std_logic; - datain : in std_logic_vector(D_W - 1 downto 0); -- incoming data word - datain_valid : in std_logic; -- valid signal for input data - counterA_in : in std_logic_vector(D_W - 1 downto 0); -- last counter value link A - counterB_in : in std_logic_vector(D_W - 1 downto 0); -- last counter value link B - counterC_in : in std_logic_vector(D_W - 1 downto 0); -- last counter value link B + datain : in std_logic_vector(DWidth - 1 downto 0); -- incoming data word + datain_valid : in std_logic; -- valid signal for input data + counterA_in : in std_logic_vector(DWidth - 1 downto 0); -- last counter value link A + counterB_in : in std_logic_vector(DWidth - 1 downto 0); -- last counter value link B + counterC_in : in std_logic_vector(DWidth - 1 downto 0); -- last counter value link B - dataout : out std_logic_vector(D_W - 1 downto 0); -- decoded data word - dataout_valid : out std_logic; -- valid output data - counterA_out : out std_logic_vector(D_W - 1 downto 0); -- last counter value link A - counterB_out : out std_logic_vector(D_W - 1 downto 0); -- last counter value link B - counterC_out : out std_logic_vector(D_W - 1 downto 0) -- last counter value link B + dataout : out std_logic_vector(DWidth - 1 downto 0); -- decoded data word + dataout_valid : out std_logic; -- valid output data + counterA_out : out std_logic_vector(DWidth - 1 downto 0); -- last counter value link A + counterB_out : out std_logic_vector(DWidth - 1 downto 0); -- last counter value link B + counterC_out : out std_logic_vector(DWidth - 1 downto 0) -- last counter value link B ); end DataDecoder; @@ -39,90 +39,104 @@ architecture RTL of DataDecoder is component PixelAddressDecode is generic ( - column_width : integer := 8; -- column bits - row_width : integer := 8); -- row bits + column_width : integer := 8; -- column bits + row_width : integer := 8); -- row bits port ( - clk : in std_logic; -- clock in - reset : in std_logic; -- reset in - bypass : in std_logic; -- bypass logic - ena : in std_logic; -- enable in + clk : in std_logic; -- clock in + reset : in std_logic; -- reset in + bypass : in std_logic; -- bypass logic + ena : in std_logic; -- enable in col_in : in std_logic_vector(column_width - 1 downto 0); -- mupix col addr. - row_in : in std_logic_vector(row_width - 1 downto 0); -- mupix row addr. - valid_o : out std_logic; -- valid output + row_in : in std_logic_vector(row_width - 1 downto 0); -- mupix row addr. + valid_o : out std_logic; -- valid output col_out : out std_logic_vector(column_width - 1 downto 0); -- phys. col addr. - row_out : out std_logic_vector(row_width - 1 downto 0)); -- phys row addr. + row_out : out std_logic_vector(row_width - 1 downto 0)); -- phys row addr. end component; component gray_to_binary is generic(NBITS : integer := 10); port ( - clk : in std_logic; -- clk input - reset : in std_logic; -- reset input - bypass : in std_logic; -- bypass logic + clk : in std_logic; -- clk input + reset : in std_logic; -- reset input + bypass : in std_logic; -- bypass logic gray_in : in std_logic_vector (NBITS - 1 downto 0); -- gray counter input bin_out : out std_logic_vector (NBITS - 1 downto 0) -- binary counter output ); end component; -signal datain_i : std_logic_vector(LINKS*D_W - 1 downto 0); -- data channel and counters -signal dataout_i : std_logic_vector(LINKS*D_W - 1 downto 0); -- data channel and counters -signal validin_i : std_logic_vector(LINKS - 1 downto 0); -signal validout_i : std_logic_vector(LINKS - 1 downto 0); -- valid signals +-- combine counters (for easier decoder generation) +signal ctrs_in_i : std_logic_vector((LINKS - 1)*DWidth - 1 downto 0) := (others => '0'); +signal ctrs_out_i : std_logic_vector((LINKS - 1)*DWidth - 1 downto 0) := (others => '0'); begin + ctrs_in_i <= counterA_in & counterB_in & counterC_in; + + -- *********************************** + -- * decode data (address & hit info)* + -- *********************************** + address_decoder_data : PixelAddressDecode + generic map ( + column_width => PixWidth, + row_width => PixWidth + ) + port map ( + clk => clk, + reset => reset, + bypass => bypass, + ena => datain_valid, + col_in => datain(DWidth - PixWidth - 1 downto DWidth - 2*PixWidth), + row_in => datain(DWidth - 1 downto DWidth - PixWidth), + valid_o => dataout_valid, + col_out => dataout(DWidth - PixWidth - 1 downto DWidth - 2*PixWidth), + row_out => dataout(DWidth - 1 downto DWidth - PixWidth) + ); - -- combine datain and counters to single stream for easier decoder generation - datain_i <= datain & counterA_in & counterB_in & counterC_in; - validin_i <= datain_valid & b"111"; - - Decode_J : for J in 1 to LINKS generate - address_decoder : PixelAddressDecode - generic map ( - column_width => Pix_W, - row_width => Pix_W - ) - port map ( - clk => clk, - reset => reset, - bypass => bypass, - ena => validin_i(J - 1), - col_in => datain_i(J*D_W - Pix_W - 1 downto J*D_W - 2*Pix_W), - row_in => datain_i(J*D_W - 1 downto J*D_W - Pix_W), - valid_o => validout_i(J - 1), - col_out => dataout_i(J*D_W - Pix_W - 1 downto J*D_W - 2*Pix_W), - row_out => dataout_i(J*D_W - 1 downto J*D_W - Pix_W) - ); - - ToT_decoder : gray_to_binary - generic map ( - NBITS => ToT_W - ) - port map ( - clk => clk, - reset => reset, - bypass => bypass, - gray_in => datain_i(J*D_W - 2*Pix_W - 1 downto (J-1)*D_W + TS_W), - bin_out => dataout_i(J*D_W - 2*Pix_W - 1 downto (J-1)*D_W + TS_W) - ); + ToT_decoder_data : gray_to_binary + generic map ( + NBITS => ToTWidth + ) + port map ( + clk => clk, + reset => reset, + bypass => bypass, + gray_in => datain(DWidth - 2*PixWidth - 1 downto TSWidth), + bin_out => dataout(DWidth - 2*PixWidth - 1 downto TSWidth) + ); - Timestamp_decoder : gray_to_binary - generic map ( - NBITS => TS_W - ) - port map ( - clk => clk, - reset => reset, - bypass => bypass, - gray_in => datain_i((J-1)*D_W + TS_W - 1 downto (J-1)*D_W), - bin_out => dataout_i((J-1)*D_W + TS_W - 1 downto (J-1)*D_W) - ); - end generate Decode_J; + TS_decoder_data : gray_to_binary + generic map ( + NBITS => TSWidth + ) + port map ( + clk => clk, + reset => reset, + bypass => bypass, + gray_in => datain(TSWidth - 1 downto 0), + bin_out => dataout(TSWidth - 1 downto 0) + ); + + + -- *********************************** + -- * decode counters (w/o addrresses)* + -- *********************************** + decode_counters: for J in 1 to (LINKS - 1) generate + gray_decode: gray_to_binary + generic map ( + NBITS => (ToTWidth + TSWidth) + ) + port map ( + clk => clk, + reset => reset, + bypass => bypass, + gray_in => ctrs_in_i(J*DWidth - 2*PixWidth - 1 downto (J-1)*DWidth), + bin_out => ctrs_out_i(J*DWidth - 2*PixWidth - 1 downto (J-1)*DWidth) + ); + end generate; - -- split datastream back up to individual outputs - dataout_valid <= validout_i(LINKS - 1); - dataout <= dataout_i(LINKS*D_W - 1 downto (LINKS - 1)*D_W); - counterA_out <= dataout_i((LINKS - 1)*D_W - 1 downto (LINKS - 2)*D_W); - counterB_out <= dataout_i((LINKS - 2)*D_W - 1 downto (LINKS - 3)*D_W); - counterC_out <= dataout_i((LINKS - 3)*D_W - 1 downto (LINKS - 4)*D_W); + -- split counters back up to individual outputs + counterA_out <= ctrs_out_i((LINKS - 1)*DWidth - 1 downto (LINKS - 2)*DWidth); + counterB_out <= ctrs_out_i((LINKS - 2)*DWidth - 1 downto (LINKS - 3)*DWidth); + counterC_out <= ctrs_out_i((LINKS - 3)*DWidth - 1 downto (LINKS - 4)*DWidth); end RTL; + -- 2.43.0