From 20158840eff90a9ac42b745ed02e5f7e23347de1 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Fri, 4 Feb 2022 11:12:33 +0100 Subject: [PATCH] main RX reset counters changed for better timing, SCI RD polling time extended --- media_interfaces/sync/main_rx_reset_RS.vhd | 44 ++++++++++++---------- media_interfaces/sync/sci_reader_RS.vhd | 12 +----- 2 files changed, 27 insertions(+), 29 deletions(-) diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index 5659379..96bc90b 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -29,11 +29,14 @@ architecture main_rx_reset_RS_arch of main_rx_reset_RS is -- Remark: work of Christian Michel. Just re-edited to reflect necessary changes for ECP3. -- Without this piece of code, many things would have been a real pain. - constant Tshort : unsigned(31 downto 0) := x"0000000a"; --- @200MHz 100ms - constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; - constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; - constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tshort_bit : integer := 4; -- count up to 2^4 = 16 +-- constant Tshort : unsigned(31 downto 0) := x"0000000a"; + constant Tplol_bit : integer := 22; +-- constant Tplol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tcdr_bit : integer := 22; +-- constant Tcdr : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; + constant Tviol_bit : integer := 22; +-- constant Tviol : unsigned(31 downto 0) := x"003fffff"; --x"01312d00"; signal pll_lol_s : std_logic; signal cdr_lol_s : std_logic; @@ -97,7 +100,8 @@ begin if( (pll_lol_s = '1') or (sd_los_s = '1') ) then cnt <= (others => '0'); else - if( cnt = Tplol ) then +-- if( cnt = Tplol ) then + if( cnt(Tplol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; else @@ -110,7 +114,8 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( cnt = Tshort ) then +-- if( cnt = Tshort ) then + if( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= WAIT_CDR_LOCK; else @@ -122,7 +127,8 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( cnt = Tcdr ) then +-- if( cnt = Tcdr ) then + if( cnt(Tcdr_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_CDR; else @@ -138,7 +144,8 @@ begin cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; else - if( cnt = Tcdr ) then +-- if( cnt = Tcdr ) then + if( cnt(Tcdr_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; else @@ -151,7 +158,8 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - if( cnt = Tshort ) then +-- if( cnt = Tshort ) then + if( cnt(Tshort_bit) ) then cnt <= (others => '0'); rx_sm <= WAIT_RXPCS_LOCK; else @@ -163,7 +171,8 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - if( cnt = Tviol ) then +-- if( cnt = Tviol ) then + if( cnt(Tviol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= TEST_RXPCS; else @@ -179,7 +188,8 @@ begin cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; else - if( cnt = Tviol ) then +-- if( cnt = Tviol ) then + if( cnt(Tviol_bit) = '1' ) then cnt <= (others => '0'); rx_sm <= CHECK_WAP; else @@ -193,7 +203,8 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; cnt <= (others => '0'); - if( cnt = Tshort ) then +-- if( cnt = Tshort ) then + if( cnt(Tshort_bit) = '1' ) then cnt <= (others => '0'); if( wap_zero_s = '1' ) then rx_sm <= NORMAL_OP; @@ -204,12 +215,6 @@ begin else cnt <= cnt + 1; end if; --- if( wap_zero_s = '1' ) then --- rx_sm <= NORMAL_OP; --- else ----- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK --- rx_sm <= APPLY_CDR_RST; --- end if; when NORMAL_OP => STATE_OUT <= x"8"; @@ -228,6 +233,7 @@ begin RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; rx_sm <= POWERUP; + cnt <= (others => '0'); end case; diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index 2ea0f3f..3178438 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -39,23 +39,15 @@ architecture sci_reader_arch of sci_reader_RS is type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); signal sci_state : sci_ctrl; -signal sci_timer : unsigned(12 downto 0) := (others => '0'); +signal sci_timer : unsigned(14 downto 0) := (others => '0'); signal sci_reg_i : std_logic; signal wa_position : std_logic_vector(15 downto 0); signal next_sci_wr : std_logic; ---signal wap_req_q : std_logic_vector(2 downto 0); begin --- THE_SYNC_PROC: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- wap_req_q(2 downto 0) <= wap_req_q(1 downto 0) & WA_REQ_IN; --- end if; --- end process THE_SYNC_PROC; - -------------------------------------------------- +------------------------------------------------ -- SCI ------------------------------------------------- --gives access to serdes config port from slow control and reads word alignment every ~ 40 us -- 2.43.0