From 2130cebbddce92b2558f91d6f0fddd00f6bd2aba Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 8 Jul 2013 18:21:02 +0200 Subject: [PATCH] last version of JTAG code --- vhdl/code/jtag_mvd.vhd | 93 +++++++++++++----------- vhdl/trb3_periph_mvdjtag.prj | 52 ++++++------- vhdl/trb3_periph_mvdjtag.vhd | 9 ++- vhdl/trb3_periph_mvdjtag_constraints.lpf | 13 +++- 4 files changed, 92 insertions(+), 75 deletions(-) diff --git a/vhdl/code/jtag_mvd.vhd b/vhdl/code/jtag_mvd.vhd index 899c0b8..3e20a6e 100644 --- a/vhdl/code/jtag_mvd.vhd +++ b/vhdl/code/jtag_mvd.vhd @@ -188,9 +188,9 @@ begin THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 7, - PORT_ADDRESSES => (0 => x"1000", 1 => x"0000", 2 => x"0200", 3 => x"0400", 4 => x"0600", 5 => x"0800", 6 => x"1800", others => x"0000"), - PORT_ADDR_MASK => (0 => 8, 1 => 9, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 6, others => 0) + PORT_NUMBER => num_bus_handler_ports, + PORT_ADDRESSES => (0 => x"1000", 1 => x"1800", 2 => x"0000", 3 => x"0200", 4 => x"0400", 5 => x"0600", 6 => x"0800", others => x"0000"), + PORT_ADDR_MASK => (0 => 8, 1 => 8, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 9, others => 0) ) port map( CLK => clk_sys, @@ -221,30 +221,31 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler BUS_NO_MORE_DATA_IN(0) => com_settings_no_more_data_out, BUS_UNKNOWN_ADDR_IN(0) => com_settings_unknown_addr_out, + --Status Registers + BUS_READ_ENABLE_OUT(1) => statreg_read_en, + BUS_WRITE_ENABLE_OUT(1) => statreg_write_en, + BUS_DATA_OUT(1*32+31 downto 1*32) => open, + BUS_ADDR_OUT(1*16+7 downto 1*16) => statreg_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+8) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(1*32+31 downto 1*32) => statreg_data, + BUS_DATAREADY_IN(1) => statreg_ack, + BUS_WRITE_ACK_IN(1) => '0', + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(1) => statreg_nack, + --JTAG chains - BUS_READ_ENABLE_OUT(NUM_CHAINS downto 1) => jtag_cmd_m26c_read_enable_in, - BUS_WRITE_ENABLE_OUT(NUM_CHAINS downto 1) => jtag_cmd_m26c_write_enable_in, - BUS_DATA_OUT(NUM_CHAINS*32+31 downto 1*32) => jtag_cmd_m26c_data_in, - BUS_ADDR_OUT(NUM_CHAINS*16+15 downto 1*16) => jtag_cmd_m26c_addr_in, - BUS_TIMEOUT_OUT(NUM_CHAINS downto 1) => open, - BUS_DATA_IN(NUM_CHAINS*32+31 downto 1*32) => jtag_cmd_m26c_data_out, - BUS_DATAREADY_IN(NUM_CHAINS downto 1) => jtag_cmd_m26c_dataready_out, - BUS_WRITE_ACK_IN(NUM_CHAINS downto 1) => jtag_cmd_m26c_write_ack_out, - BUS_NO_MORE_DATA_IN(NUM_CHAINS downto 1) => jtag_cmd_m26c_no_more_data_out, - BUS_UNKNOWN_ADDR_IN(NUM_CHAINS downto 1) => jtag_cmd_m26c_unknown_addr_out, + BUS_READ_ENABLE_OUT((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_read_enable_in, + BUS_WRITE_ENABLE_OUT((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_write_enable_in, + BUS_DATA_OUT((NUM_CHAINS+1)*32+31 downto 2*32) => jtag_cmd_m26c_data_in, + BUS_ADDR_OUT((NUM_CHAINS+1)*16+15 downto 2*16) => jtag_cmd_m26c_addr_in, + BUS_TIMEOUT_OUT((NUM_CHAINS+1) downto 2) => open, + BUS_DATA_IN((NUM_CHAINS+1)*32+31 downto 2*32) => jtag_cmd_m26c_data_out, + BUS_DATAREADY_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_dataready_out, + BUS_WRITE_ACK_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_write_ack_out, + BUS_NO_MORE_DATA_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_no_more_data_out, + BUS_UNKNOWN_ADDR_IN((NUM_CHAINS+1) downto 2) => jtag_cmd_m26c_unknown_addr_out, - --Status Registers - BUS_READ_ENABLE_OUT(6) => statreg_read_en, - BUS_WRITE_ENABLE_OUT(6) => statreg_write_en, - BUS_DATA_OUT(6*32+31 downto 6*32) => open, - BUS_ADDR_OUT(6*16+7 downto 6*16) => statreg_addr, - BUS_ADDR_OUT(6*16+15 downto 6*16+8) => open, - BUS_TIMEOUT_OUT(6) => open, - BUS_DATA_IN(6*32+31 downto 6*32) => statreg_data, - BUS_DATAREADY_IN(6) => statreg_ack, - BUS_WRITE_ACK_IN(6) => statreg_ack, - BUS_NO_MORE_DATA_IN(6) => '0', - BUS_UNKNOWN_ADDR_IN(6) => statreg_nack, STAT_DEBUG => open ); @@ -265,33 +266,41 @@ THE_BUS_HANDLER : trb_net16_regio_bus_handler -- Generic status register --------------------------------------------------------------------------- gen_status_out : for i in 0 to NUM_CHAINS-1 generate - status_regs(i*256+95 downto i*256+64) <= jtagcmd_write_errors_count_out(i) & jtagcmd_read_id_errors_count_out(i); - status_regs(i*256+127 downto i*256+96) <= jtagcmd_sampling_errors_count_out(i) & jtagcmd_data_changed_count_out(i); - status_regs(i*256+159 downto i*256+128) <= jtagcmd_run_counter_out(i); - status_regs(i*256+191 downto i*256+160) <= "000" & '0' & "000" & '0' & + status_regs(i*256+31 downto i*256+0) <= jtagcmd_write_errors_count_out(i) & jtagcmd_read_id_errors_count_out(i); + status_regs(i*256+63 downto i*256+32) <= jtagcmd_sampling_errors_count_out(i) & jtagcmd_data_changed_count_out(i); + status_regs(i*256+95 downto i*256+64) <= jtagcmd_run_counter_out(i); + status_regs(i*256+127 downto i*256+96) <= "000" & '0' & "000" & '0' & "000" & jtagcmd_crc_error_out(i) & "000" & jtagcmd_last_read_errors_out(i) & "000" & jtagcmd_last_write_errors_out(i) & "000" & jtagcmd_last_data_changed_out(i) & "000" & jtagcmd_last_run_successful_out(i) & "000" & jtagcmd_started_out(i); - status_regs(i*256+255 downto i*256+192) <= (others => '0'); + status_regs(i*256+255 downto i*256+128) <= (others => '1'); end generate; STATUS_OUT(NUM_CHAINS*256-1 downto 0) <= status_regs; - THE_STAT_REG_MUX : process begin - wait until rising_edge(clk_sys); - statreg_ack <= '0'; - statreg_nack <= '0'; - - if statreg_read_en = '1' then - if unsigned(statreg_addr) < to_unsigned(NUM_CHAINS*8,8) then - statreg_ack <= '1'; - statreg_data <= status_regs(to_integer(unsigned(statreg_addr))*32+31 downto to_integer(unsigned(statreg_addr))*32); - else + THE_STAT_REG_MUX : process(clk_sys) + begin + if rising_edge(clk_sys) then + statreg_ack <= '0'; + statreg_nack <= '0'; + case(statreg_addr(2 downto 0)) is + when "000" => statreg_data <= status_regs(31 downto 0); + when "001" => statreg_data <= status_regs(63 downto 32); + when "010" => statreg_data <= status_regs(95 downto 64); + when "011" => statreg_data <= status_regs(127 downto 96); + when "100" => statreg_data <= x"12345678"; + when others => statreg_data <= (others => '0'); + end case; + if statreg_read_en = '1' then + if statreg_addr(7 downto 3) = "00000" then + statreg_ack <= '1'; + else + statreg_nack <= '1'; + end if; + elsif statreg_write_en = '1' then statreg_nack <= '1'; end if; - elsif statreg_write_en = '1' then - statreg_nack <= '1'; end if; end process; diff --git a/vhdl/trb3_periph_mvdjtag.prj b/vhdl/trb3_periph_mvdjtag.prj index 03dcefa..2cbbf37 100644 --- a/vhdl/trb3_periph_mvdjtag.prj +++ b/vhdl/trb3_periph_mvdjtag.prj @@ -140,32 +140,32 @@ add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in200_out100.vhd" add_file -vhdl -lib "work" "../../trb3/base/cores/pll_in100_out80.vhd" add_file -vhdl -lib "work" "../../trb3/base/cores/oddr.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_constants.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_misc.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/mathhelpers.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_mvd.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_cmd_m26c.vhd" - -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/blank_ram.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/copy_ram.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/crc_32.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_bypassreg_testchain_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_check_crc_ram1a.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_delay_expected_values.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_init_ram1b.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_pulses.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_read_m26devid_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_tck_out_component.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_tdo_compare_count_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_tdo_compare_counttotal_noram_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_tdo_data_to_ram_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_tdo_sample.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_update_error_counts_ram3a.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/jtag_write_m10.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/ram_mux2to1_readport.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/ram_mux2to1_writeport.vhd" -add_file -vhdl -lib "work" "../../jtag_mvd/vhdl/code/ram_mux4to1_readport.vhd" +add_file -vhdl -lib "work" "code/jtag_constants.vhd" +add_file -vhdl -lib "work" "code/jtag_misc.vhd" +add_file -vhdl -lib "work" "code/mathhelpers.vhd" +add_file -vhdl -lib "work" "code/jtag_mvd.vhd" +add_file -vhdl -lib "work" "code/jtag_cmd_m26c.vhd" + +add_file -vhdl -lib "work" "code/blank_ram.vhd" +add_file -vhdl -lib "work" "code/copy_ram.vhd" +add_file -vhdl -lib "work" "code/crc_32.vhd" +add_file -vhdl -lib "work" "code/jtag_bypassreg_testchain_m10.vhd" +add_file -vhdl -lib "work" "code/jtag_check_crc_ram1a.vhd" +add_file -vhdl -lib "work" "code/jtag_delay_expected_values.vhd" +add_file -vhdl -lib "work" "code/jtag_init_ram1b.vhd" +add_file -vhdl -lib "work" "code/jtag_mux_buffer_tms_tdi_out_and_metainfo.vhd" +add_file -vhdl -lib "work" "code/jtag_pulses.vhd" +add_file -vhdl -lib "work" "code/jtag_read_m26devid_m10.vhd" +add_file -vhdl -lib "work" "code/jtag_tck_out_component.vhd" +add_file -vhdl -lib "work" "code/jtag_tdo_compare_count_m10.vhd" +add_file -vhdl -lib "work" "code/jtag_tdo_compare_counttotal_noram_m10.vhd" +add_file -vhdl -lib "work" "code/jtag_tdo_data_to_ram_m10.vhd" +add_file -vhdl -lib "work" "code/jtag_tdo_sample.vhd" +add_file -vhdl -lib "work" "code/jtag_update_error_counts_ram3a.vhd" +add_file -vhdl -lib "work" "code/jtag_write_m10.vhd" +add_file -vhdl -lib "work" "code/ram_mux2to1_readport.vhd" +add_file -vhdl -lib "work" "code/ram_mux2to1_writeport.vhd" +add_file -vhdl -lib "work" "code/ram_mux4to1_readport.vhd" diff --git a/vhdl/trb3_periph_mvdjtag.vhd b/vhdl/trb3_periph_mvdjtag.vhd index 6c648a3..bd4630c 100644 --- a/vhdl/trb3_periph_mvdjtag.vhd +++ b/vhdl/trb3_periph_mvdjtag.vhd @@ -138,10 +138,10 @@ architecture trb3_periph_mvdjtag_arch of trb3_periph_mvdjtag is signal med_read_in : std_logic; --Slow Control channel - signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0); - signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); - signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0); - signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0); + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0) := (others => '0'); + signal stat_reg : std_logic_vector(32*2**REGIO_NUM_STAT_REGS-1 downto 0) := (others => '0'); + signal ctrl_reg : std_logic_vector(32*2**REGIO_NUM_CTRL_REGS-1 downto 0) := (others => '0'); signal common_stat_reg_strobe : std_logic_vector(std_COMSTATREG-1 downto 0); signal common_ctrl_reg_strobe : std_logic_vector(std_COMCTRLREG-1 downto 0); signal stat_reg_strobe : std_logic_vector(2**REGIO_NUM_STAT_REGS-1 downto 0); @@ -492,6 +492,7 @@ begin BUS_ADDR_OUT(2*16+15 downto 2*16+9) => open, BUS_TIMEOUT_OUT(2) => open, BUS_DATA_IN(2*32+7 downto 2*32) => sci1_data_out, + BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'), BUS_DATAREADY_IN(2) => sci1_ack, BUS_WRITE_ACK_IN(2) => sci1_ack, BUS_NO_MORE_DATA_IN(2) => '0', diff --git a/vhdl/trb3_periph_mvdjtag_constraints.lpf b/vhdl/trb3_periph_mvdjtag_constraints.lpf index 8ac9752..3ee6513 100644 --- a/vhdl/trb3_periph_mvdjtag_constraints.lpf +++ b/vhdl/trb3_periph_mvdjtag_constraints.lpf @@ -2,14 +2,21 @@ BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; + +################################################################# +# Basic Settings +################################################################# + FREQUENCY NET "clk_100_internal_c" 100.0 MHz; + FREQUENCY NET "clk_200_internal_c" 200.0 MHz; + + SYSCONFIG MCCLK_FREQ = 20; + + ################################################################# # Reset Nets ################################################################# GSR_NET NET "reset_i"; -FREQUENCY NET "clk_100_internal_c" 100.0 MHz; -FREQUENCY NET "clk_200_internal_c" 200.0 MHz; - ################################################################# # Locate Serdes and media interfaces ################################################################# -- 2.43.0