From 21c81a4a4893e9295ade16151db74403e294de26 Mon Sep 17 00:00:00 2001 From: HADES DAQ Date: Mon, 13 Jun 2022 15:35:00 +0200 Subject: [PATCH] correction from my last commit: trb5sc_cbmrich.prj back to 240MHz, mt --- cbmrich/trb5sc_cbmrich.prj | 17 +++++------------ 1 file changed, 5 insertions(+), 12 deletions(-) diff --git a/cbmrich/trb5sc_cbmrich.prj b/cbmrich/trb5sc_cbmrich.prj index 61b81c3..11a145b 100644 --- a/cbmrich/trb5sc_cbmrich.prj +++ b/cbmrich/trb5sc_cbmrich.prj @@ -66,11 +66,9 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" #Basic Infrastructure add_file -vhdl -lib work "../../dirich/cores/pll_240_100/pll_240_100.vhd" -add_file -vhdl -lib work "../../dirich/cores/pll_200_100.vhd" add_file -vhdl -lib work "../../dirich/cores/ecp5/pll_200_240.vhd" -#add_file -vhdl -lib work "../../dirich/cores/ecp5/pll_200_240.vhd" -add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" -#add_file -vhdl -lib work "../../dirich/code/clock_reset_handler_240.vhd" +#add_file -vhdl -lib work "../../dirich/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../dirich/code/clock_reset_handler_240.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" add_file -vhdl -lib work "../../vhdlbasics/ecp5/sedcheck.vhd" @@ -179,17 +177,12 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_240.vh #channel 1, SFP add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/chan0_1/serdes_sync_0.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" ########################################## -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs_240.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs2_240.vhd" - -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs_240.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/240MHz/pcs2_240.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/240MHz/serdes_sync_0_softlogic.v" -#add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/240MHz/serdes_sync_0_softlogic.v" -add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" -- 2.43.0