From 22ad49bca19865e9b8899f2deea5050b91341efb Mon Sep 17 00:00:00 2001 From: Ingo Froehlich Date: Fri, 6 Jul 2018 10:35:14 +0200 Subject: [PATCH] still testing, link crashes after resubmit, IF --- media_interfaces/med_ecp3_sfp_sync_4.vhd | 73 +++++++++- .../med_ecp3_sfp_sync_4_slave3.vhd | 74 +++++++++- media_interfaces/sync/med_sync_control.vhd | 128 ++++++++++++++---- media_interfaces/sync/med_sync_define.vhd | 2 + media_interfaces/sync/rx_control.vhd | 54 ++++++-- media_interfaces/sync/tb/med_sync_tb.vhd | 16 ++- media_interfaces/sync/tx_control.vhd | 20 ++- 7 files changed, 308 insertions(+), 59 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_4.vhd b/media_interfaces/med_ecp3_sfp_sync_4.vhd index 17745db..f04179d 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4.vhd @@ -14,7 +14,8 @@ use work.med_sync_define.all; entity med_ecp3_sfp_sync_4 is generic( IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode - IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES) + IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES); + REG_OFFSET : std_logic_vector(7 downto 0) := x"00" ); port( CLK_REF_FULL : in std_logic; -- 200 MHz reference clock @@ -38,10 +39,13 @@ entity med_ecp3_sfp_sync_4 is SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - + MII_RX : in CTRLBUS_RX; + MII_TX : out CTRLBUS_TX; + -- Status and control port STAT_DEBUG : out std_logic_vector (63 downto 0); CTRL_DEBUG : in std_logic_vector (63 downto 0) := (others => '0') @@ -104,6 +108,9 @@ signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0); attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; +signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3); +signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3); + begin -- SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -258,13 +265,60 @@ SD_TXDIS_OUT <= (others => RESET); rst_qd_c => rst_qd(0), serdes_rst_qd_c => '0', tx_sync_qd_c => '0' - ); +BUS_MULTIPLEXER : process + begin + wait until rising_edge(SYSCLK); + mii_rx_i(0).data <= mii_rx.data; + mii_rx_i(1).data <= mii_rx.data; + mii_rx_i(2).data <= mii_rx.data; + mii_rx_i(3).data <= mii_rx.data; + mii_rx_i(0).addr <= mii_rx.addr; + mii_rx_i(1).addr <= mii_rx.addr; + mii_rx_i(2).addr <= mii_rx.addr; + mii_rx_i(3).addr <= mii_rx.addr; + + mii_tx.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; + mii_tx.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; + mii_tx.unknown <= mii_tx_i(0).unknown and mii_tx_i(1).unknown and mii_tx_i(2).unknown and mii_tx_i(3).unknown; + + mii_rx_i(0).read <= '0'; + mii_rx_i(1).read <= '0'; + mii_rx_i(2).read <= '0'; + mii_rx_i(3).read <= '0'; + mii_rx_i(0).write <= '0'; + mii_rx_i(1).write <= '0'; + mii_rx_i(2).write <= '0'; + mii_rx_i(3).write <= '0'; + -- connect debug registers, mii0 should be at 0x00+offset, mii1 at + -- 0x10+offset, etc + if (mii_rx.read = '1') then + if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then + mii_rx_i(0).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then + mii_rx_i(1).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then + mii_rx_i(2).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then + mii_rx_i(3).read <= '1'; + end if; + end if; + + if (mii_rx.write = '1') then + if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then + mii_rx_i(0).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then + mii_rx_i(1).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then + mii_rx_i(2).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then + mii_rx_i(3).write <= '1'; + end if; + end if; +end process; + - - - gen_control : for i in 0 to 3 generate gen_used_control : if IS_USED(i) = c_YES generate THE_MED_CONTROL : entity work.med_sync_control @@ -310,7 +364,10 @@ gen_control : for i in 0 to 3 generate STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), - STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32) + STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32), + + BUS_RX => mii_rx_i(i), + BUS_TX => mii_tx_i(i) ); end generate; @@ -318,6 +375,8 @@ gen_control : for i in 0 to 3 generate MEDIA_MED2INT(i).dataready <= '0'; MEDIA_MED2INT(i).tx_read <= '1'; MEDIA_MED2INT(i).stat_op <= x"0007"; + mii_tx_i(i).data <= x"00000000"; + mii_tx_i(i).ack <= '0'; end generate; end generate; diff --git a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd index ad185b4..15c316f 100644 --- a/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd @@ -14,7 +14,8 @@ use work.med_sync_define.all; entity med_ecp3_sfp_sync_4_slave3 is generic( IS_SYNC_SLAVE : int_array_t(0 to 3) := (c_NO, c_NO, c_NO, c_NO); --select slave mode - IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES) + IS_USED : int_array_t(0 to 3) := (c_YES,c_YES,c_YES,c_YES); + REG_OFFSET : std_logic_vector(7 downto 0) := x"00" ); port( CLK_REF_FULL : in std_logic; -- 200 MHz reference clock @@ -38,9 +39,12 @@ entity med_ecp3_sfp_sync_4_slave3 is SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic_vector(3 downto 0); -- SFP Loss Of Signal ('0' = OK, '1' = no signal) SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- SFP disable + --Control Interface BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; + MII_RX : in CTRLBUS_RX; + MII_TX : out CTRLBUS_TX; -- Status and control port STAT_DEBUG : out std_logic_vector (63 downto 0); @@ -103,6 +107,9 @@ signal hdinp, hdinn, hdoutp, hdoutn : std_logic_vector(3 downto 0); attribute nopad : string; attribute nopad of hdinp, hdinn, hdoutp, hdoutn : signal is "true"; +signal mii_tx_i : CTRLBUS_TX_array_t(0 to 3); +signal mii_rx_i : CTRLBUS_RX_array_t(0 to 3); + begin SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready @@ -256,13 +263,63 @@ SD_TXDIS_OUT <= (others =>'0'); --not (rx_allow_q or not IS_SLAVE); --slave on rst_qd_c => rst_qd(0), serdes_rst_qd_c => '0', tx_sync_qd_c => '0' - ); - -- clk_rxi <= (0 => CLK_REF_FULL,1 => CLK_REF_FULL,2 => CLK_REF_FULL,3 => clk_rx_full(3)); - - + + +BUS_MULTIPLEXER : process + begin + wait until rising_edge(SYSCLK); + + mii_rx_i(0).data <= mii_rx.data; + mii_rx_i(1).data <= mii_rx.data; + mii_rx_i(2).data <= mii_rx.data; + mii_rx_i(3).data <= mii_rx.data; + mii_rx_i(0).addr <= mii_rx.addr; + mii_rx_i(1).addr <= mii_rx.addr; + mii_rx_i(2).addr <= mii_rx.addr; + mii_rx_i(3).addr <= mii_rx.addr; + + mii_tx.data <= mii_tx_i(0).data or mii_tx_i(1).data or mii_tx_i(2).data or mii_tx_i(3).data; + mii_tx.ack <= mii_tx_i(0).ack or mii_tx_i(1).ack or mii_tx_i(2).ack or mii_tx_i(3).ack; + + mii_rx_i(0).read <= '0'; + mii_rx_i(1).read <= '0'; + mii_rx_i(2).read <= '0'; + mii_rx_i(3).read <= '0'; + mii_rx_i(0).write <= '0'; + mii_rx_i(1).write <= '0'; + mii_rx_i(2).write <= '0'; + mii_rx_i(3).write <= '0'; + -- connect debug registers, mii0 should be at 0x00+offset, mii1 at + -- 0x10+offset, etc + if (mii_rx.read = '1') then + if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then + mii_rx_i(0).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then + mii_rx_i(1).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then + mii_rx_i(2).read <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then + mii_rx_i(3).read <= '1'; + end if; + end if; + + if (mii_rx.write = '1') then + if (mii_rx.addr(7 downto 4) = (REG_OFFSET(7 downto 4))) then + mii_rx_i(0).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 1)) then + mii_rx_i(1).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 2)) then + mii_rx_i(2).write <= '1'; + elsif (mii_rx.addr(7 downto 4) = std_logic_vector(unsigned(REG_OFFSET(7 downto 4)) + 3)) then + mii_rx_i(3).write <= '1'; + end if; + end if; +end process; + + gen_control : for i in 0 to 3 generate gen_used_control : if IS_USED(i) = c_YES generate THE_MED_CONTROL : entity work.med_sync_control @@ -307,7 +364,10 @@ gen_control : for i in 0 to 3 generate STAT_RX_CONTROL => stat_rx_control_i(i*32+31 downto i*32), DEBUG_TX_CONTROL => debug_tx_control_i(i*32+31 downto i*32), DEBUG_RX_CONTROL => debug_rx_control_i(i*32+31 downto i*32), - STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32) + STAT_RESET => stat_fsm_reset_i(i*32+31 downto i*32), + + BUS_RX => mii_rx_i(i), + BUS_TX => mii_tx_i(i) ); end generate; @@ -315,6 +375,8 @@ gen_control : for i in 0 to 3 generate MEDIA_MED2INT(i).dataready <= '0'; MEDIA_MED2INT(i).tx_read <= '1'; MEDIA_MED2INT(i).stat_op <= x"0007"; + mii_tx_i(i).data <= x"00000000"; + mii_tx_i(i).ack <= '0'; end generate; end generate; diff --git a/media_interfaces/sync/med_sync_control.vhd b/media_interfaces/sync/med_sync_control.vhd index 6056c01..cf3f4be 100644 --- a/media_interfaces/sync/med_sync_control.vhd +++ b/media_interfaces/sync/med_sync_control.vhd @@ -54,7 +54,10 @@ entity med_sync_control is DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); STAT_RESET : out std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX ); end entity; @@ -64,14 +67,20 @@ architecture med_sync_control_arch of med_sync_control is signal rx_fsm_state : std_logic_vector(3 downto 0); signal tx_fsm_state : std_logic_vector(3 downto 0); signal wa_position_rx : std_logic_vector(3 downto 0); -signal start_timer : unsigned(20 downto 0) := (others => '0'); --REAL ---signal start_timer : unsigned(11 downto 0) := (others => '0'); --SIM +--signal start_timer : unsigned(20 downto 0) := (others => '0'); --REAL +signal start_timer : unsigned(11 downto 0) := (others => '0'); --SIM signal request_retr_i : std_logic; signal start_retr_i : std_logic; signal request_retr_position_i : std_logic_vector(7 downto 0); signal start_retr_position_i : std_logic_vector(7 downto 0); + +signal request_retr_counter : std_logic_vector(15 downto 0) := x"0000"; +signal start_retr_counter : std_logic_vector(15 downto 0) := x"0000"; + +signal force_crc_error : std_logic := '0'; + signal rx_dlm_i : std_logic; signal led_ok : std_logic; @@ -95,13 +104,26 @@ signal media_med2int_i : MED2INT; signal finished_reset_rx, finished_reset_rx_q : std_logic; signal finished_reset_tx, finished_reset_tx_q : std_logic; +signal STAT_TX_CONTROL_i : std_logic_vector(31 downto 0); +signal STAT_RX_CONTROL_i : std_logic_vector(31 downto 0); +signal DEBUG_TX_CONTROL_i : std_logic_vector(31 downto 0); +signal DEBUG_RX_CONTROL_i : std_logic_vector(31 downto 0); +signal STAT_RESET_i : std_logic_vector(31 downto 0); +signal DEBUG_OUT_i : std_logic_vector(31 downto 0); + + begin +STAT_TX_CONTROL <= STAT_TX_CONTROL_i; +STAT_RX_CONTROL <= STAT_RX_CONTROL_i; +DEBUG_TX_CONTROL <= DEBUG_TX_CONTROL_i; +DEBUG_RX_CONTROL <= DEBUG_RX_CONTROL_i; +STAT_RESET <= STAT_RESET_i; +DEBUG_OUT <= DEBUG_OUT_i; + rst_n_tx <= not (CLEAR or sd_los_i or make_link_reset_real_i) when (IS_SYNC_SLAVE = 1 and IS_TX_RESET = 1) else not (CLEAR or make_link_reset_real_i); - - rst_n <= not (CLEAR or sd_los_i or make_link_reset_real_i); reset_i <= (RESET or sd_los_i or make_link_reset_real_i); @@ -188,7 +210,51 @@ PROC_START_TIMER : process begin start_timer <= (others => '0'); end if; end process; - + +PROC_RETRANS_COUNTER : process begin + wait until rising_edge(CLK_SYS); + if request_retr_i = '1' then + request_retr_counter <= std_logic_vector(unsigned(request_retr_counter) + 1); + end if; + if start_retr_i = '1' then + start_retr_counter <= std_logic_vector(unsigned(start_retr_counter) + 1); + end if; +-- if make_link_reset_real_i = '0' then +-- request_retr_counter <= x"0000"; +-- start_retr_counter <= x"0000"; +-- end if; +end process; + +PROC_REG : process begin + wait until rising_edge(CLK_SYS); + BUS_TX.data <= x"00000000"; + BUS_TX.unknown <= '0'; + BUS_TX.ack <= '0'; + if BUS_RX.write = '1' then + BUS_TX.ack <= '1'; + case BUS_RX.addr(3 downto 0) is + when x"0" => force_crc_error <= '1'; + when others => BUS_TX.unknown <= '1'; + end case; + elsif BUS_RX.read = '1' then + BUS_TX.ack <= '1'; + BUS_TX.data <= x"deadface"; + case BUS_RX.addr(3 downto 0) is + when x"0" => BUS_TX.data <= x"000" & "000" & force_crc_error & request_retr_counter; + when x"1" => BUS_TX.data <= x"0000" & start_retr_counter; + when x"2" => BUS_TX.data <= STAT_TX_CONTROL_i; + when x"3" => BUS_TX.data <= DEBUG_TX_CONTROL_i; + when x"4" => BUS_TX.data <= STAT_RX_CONTROL_i; + when x"5" => BUS_TX.data <= DEBUG_RX_CONTROL_i; + when others => BUS_TX.unknown <= '1'; + end case; + end if; + + if request_retr_i = '1' then + force_crc_error <= '0'; + end if; +end process; + ------------------------------------------------- -- TX Data ------------------------------------------------- @@ -207,11 +273,11 @@ THE_TX : tx_control TX_K_OUT => TX_K, TX_CD_OUT => TX_CD, - REQUEST_RETRANSMIT_IN => request_retr_i, --TODO - REQUEST_POSITION_IN => request_retr_position_i, --TODO + REQUEST_RETRANSMIT_IN => request_retr_i, + REQUEST_POSITION_IN => request_retr_position_i, - START_RETRANSMIT_IN => start_retr_i, --TODO - START_POSITION_IN => start_retr_position_i, --TODO + START_RETRANSMIT_IN => start_retr_i, + START_POSITION_IN => start_retr_position_i, SEND_DLM => TX_DLM, SEND_DLM_WORD => TX_DLM_WORD, @@ -220,11 +286,11 @@ THE_TX : tx_control TX_ALLOW_IN => tx_allow, RX_ALLOW_IN => rx_allow, - ENABLE_SEND_CHKSUM => '1', - -- ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8), + --ENABLE_SEND_CHKSUM => '1', --SIM + ENABLE_SEND_CHKSUM => MEDIA_INT2MED.ctrl_op(8), - DEBUG_OUT => DEBUG_TX_CONTROL, - STAT_REG_OUT => STAT_TX_CONTROL + DEBUG_OUT => DEBUG_TX_CONTROL_i, + STAT_REG_OUT => STAT_TX_CONTROL_i ); @@ -251,6 +317,8 @@ THE_RX_CONTROL : rx_control START_RETRANSMIT_OUT => start_retr_i, START_POSITION_OUT => start_retr_position_i, + FORCE_CRC_ERROR => force_crc_error, + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM RX_DLM => rx_dlm_i, RX_DLM_WORD => RX_DLM_WORD, @@ -261,8 +329,8 @@ THE_RX_CONTROL : rx_control RX_RESET_FINISHED => finished_reset_rx, GOT_LINK_READY => got_link_ready_i, - DEBUG_OUT => DEBUG_RX_CONTROL, - STAT_REG_OUT => STAT_RX_CONTROL + DEBUG_OUT => DEBUG_RX_CONTROL_i, + STAT_REG_OUT => STAT_RX_CONTROL_i ); RX_DLM <= rx_dlm_i; @@ -293,16 +361,16 @@ end process; -- Status signals ------------------------------------------------- -STAT_RESET(3 downto 0) <= rx_fsm_state; -STAT_RESET(7 downto 4) <= tx_fsm_state; -STAT_RESET(8) <= tx_allow; -STAT_RESET(9) <= rx_allow; -STAT_RESET(15 downto 10) <= (others => '0'); -STAT_RESET(16) <= RX_CDR_LOL; -STAT_RESET(17) <= RX_LOS; -STAT_RESET(18) <= '0'; --RX_PCS_RST; -STAT_RESET(19) <= '0'; -STAT_RESET(31 downto 20) <= std_logic_vector(start_timer(start_timer'left downto start_timer'left - 11)); +STAT_RESET_i(3 downto 0) <= rx_fsm_state; +STAT_RESET_i(7 downto 4) <= tx_fsm_state; +STAT_RESET_i(8) <= tx_allow; +STAT_RESET_i(9) <= rx_allow; +STAT_RESET_i(15 downto 10) <= (others => '0'); +STAT_RESET_i(16) <= RX_CDR_LOL; +STAT_RESET_i(17) <= RX_LOS; +STAT_RESET_i(18) <= '0'; --RX_PCS_RST; +STAT_RESET_i(19) <= '0'; +STAT_RESET_i(31 downto 20) <= std_logic_vector(start_timer(start_timer'left downto start_timer'left - 11)); gen_link_reset : if IS_SYNC_SLAVE = 1 generate @@ -331,9 +399,9 @@ media_med2int_i.stat_op(8) <= rx_allow; media_med2int_i.stat_op(7 downto 4) <= (others => '0'); media_med2int_i.stat_op(3 downto 0) <= x"0" when rx_allow = '1' and tx_allow = '1' else x"7"; -DEBUG_OUT(0) <= tx_allow; -DEBUG_OUT(1) <= rx_allow; -DEBUG_OUT(2) <= sd_los_i; -DEBUG_OUT(3) <= '0'; --DEBUG_RX_CONTROL(4); +DEBUG_OUT_i(0) <= tx_allow; +DEBUG_OUT_i(1) <= rx_allow; +DEBUG_OUT_i(2) <= sd_los_i; +DEBUG_OUT_i(3) <= '0'; --DEBUG_RX_CONTROL(4); end architecture; diff --git a/media_interfaces/sync/med_sync_define.vhd b/media_interfaces/sync/med_sync_define.vhd index f01e6ac..f823b69 100644 --- a/media_interfaces/sync/med_sync_define.vhd +++ b/media_interfaces/sync/med_sync_define.vhd @@ -36,6 +36,8 @@ component rx_control is START_RETRANSMIT_OUT : out std_logic := '0'; START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); + FORCE_CRC_ERROR : in std_logic := '0'; + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM RX_DLM : out std_logic := '0'; RX_DLM_WORD : out std_logic_vector( 7 downto 0) := (others => '0'); diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index e6e4811..1881bb1 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -28,6 +28,8 @@ entity rx_control is START_RETRANSMIT_OUT : out std_logic := '0'; START_POSITION_OUT : out std_logic_vector( 7 downto 0) := (others => '0'); + FORCE_CRC_ERROR : in std_logic; + --send_dlm: 200 MHz, 1 clock strobe, data valid until next DLM RX_DLM : out std_logic := '0'; RX_DLM_WORD : out std_logic_vector( 7 downto 0) := (others => '0'); @@ -38,7 +40,7 @@ entity rx_control is RX_ALLOW_IN : in std_logic := '0'; --clk_sys RX_RESET_FINISHED : in std_logic := '0'; --clk_rx GOT_LINK_READY : out std_logic := '0'; --clk_rx - + DEBUG_OUT : out std_logic_vector(31 downto 0); STAT_REG_OUT : out std_logic_vector(31 downto 0) ); @@ -68,7 +70,7 @@ signal idle_hist_i : std_logic_vector(3 downto 0) := x"0"; signal got_link_ready_i : std_logic := '0'; signal start_retr_i : std_logic; signal start_retr_pos_i : std_logic_vector(7 downto 0); -signal req_retr_i : std_logic; +signal req_retr_i : std_logic := '0'; signal req_retr_pos_i : std_logic_vector(7 downto 0); signal rx_dlm_i : std_logic; signal rx_dlm_word_i : std_logic_vector(7 downto 0); @@ -97,6 +99,11 @@ signal good_pos_counter : unsigned(7 downto 0) := (others => '0'); signal num_pakets : unsigned(3 downto 0) := (others => '0'); signal use_crc : std_logic := '0'; +signal load_use_crc : std_logic := '0'; + +signal num_crc : unsigned(3 downto 0) := (others => '0'); +signal num_pak : unsigned(3 downto 0) := (others => '0'); + begin @@ -125,6 +132,11 @@ process begin good_pos_counter <= good_pos_counter+5; elsif ct_fifo_empty = '1' then got_pulse_good <= '0'; + if load_use_crc = '1' then + use_crc <= '1'; + else + use_crc <= '0'; + end if; end if; if pulse_bad_100 = '1' then got_pulse_bad <= '1'; @@ -142,6 +154,9 @@ process begin rx_packet_num <= std_logic_vector(unsigned(rx_packet_num)+1); end if; end if; + if send_link_reset_i = '1' then + good_pos_counter <= (others => '0'); + end if; end process; ---------------------------------------------------------------------- @@ -188,7 +203,6 @@ PROC_RX_FSM : process begin wait until rising_edge(CLK_200); ct_fifo_write <= '0'; start_retr_i <= '0'; - req_retr_i <= '0'; rx_dlm_i <= '0'; idle_hist_i(3 downto 1) <= idle_hist_i(2 downto 0); idle_hist_i(0) <= got_link_ready_i; @@ -212,6 +226,7 @@ PROC_RX_FSM : process begin when FIRST => rx_state_bits <= x"2"; + req_retr_i <= '0'; rx_data(7 downto 0) <= reg_rx_data_in; if reg_rx_k_in = '1' then case reg_rx_data_in is @@ -265,14 +280,21 @@ PROC_RX_FSM : process begin when GET_CRC => if (use_crc = '0') then -- first time - use_crc <= '1'; - pulse_good <= '1'; + load_use_crc <= '1'; + pulse_good <= '1'; else - if (crc_q = reg_rx_data_in and waiting_for_retr = '0' and num_pakets = 5) then -- CRC match + if (crc_q = reg_rx_data_in and waiting_for_retr = '0') --- and num_pakets = 5) + and force_crc_error = '0' then -- CRC match pulse_good <= '1'; else + --pulse_good <= '1'; pulse_bad <= '1'; if waiting_for_retr = '0' then + if crc_q /= reg_rx_data_in then + num_crc <= num_crc+1; + else + num_pak <= num_pak+1; + end if; req_retr_i <= '1'; waiting_for_retr <= '1'; end if; @@ -285,6 +307,10 @@ PROC_RX_FSM : process begin when GET_RETR => rx_state <= FIRST; waiting_for_retr <= '0'; + crc_reset <= '1'; + num_pakets <= (others => '0'); + num_crc <= num_crc+1; --BUGBUG + --load_use_crc <= '0'; when GET_DLM => rx_state_bits <= x"5"; @@ -300,6 +326,10 @@ PROC_RX_FSM : process begin when MAKE_RESET => rx_state_bits <= x"F"; + load_use_crc <= '0'; + crc_reset <= '1'; + waiting_for_retr <= '0'; + num_pakets <= (others => '0'); if reg_rx_k_in = '1' and reg_rx_data_in = K_RST then send_link_reset_i <= '1'; make_reset_i <= '0'; @@ -313,7 +343,7 @@ PROC_RX_FSM : process begin send_link_reset_i <= '0'; make_reset_i <= '1'; rx_state <= SLEEP; - else + else reset_cnt <= reset_cnt + 1; send_link_reset_i <= '1'; end if; @@ -409,12 +439,18 @@ DEBUG_OUT(5) <= ct_fifo_afull; DEBUG_OUT(6) <= ct_fifo_empty; DEBUG_OUT(7) <= ct_fifo_write; DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); + DEBUG_OUT(16) <= reg_rx_k_in; DEBUG_OUT(17) <= make_reset_i; DEBUG_OUT(18) <= send_link_reset_i; DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; ---DEBUG_OUT(16) <= rx_data(16); -DEBUG_OUT(31 downto 20) <= (others => '0'); + +DEBUG_OUT(20) <= use_crc; + +DEBUG_OUT(23 downto 21) <= (others => '0'); +DEBUG_OUT(27 downto 24) <= num_crc; +DEBUG_OUT(31 downto 28) <= num_pak; + -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); -- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); diff --git a/media_interfaces/sync/tb/med_sync_tb.vhd b/media_interfaces/sync/tb/med_sync_tb.vhd index f9dfb9f..f0eaf14 100644 --- a/media_interfaces/sync/tb/med_sync_tb.vhd +++ b/media_interfaces/sync/tb/med_sync_tb.vhd @@ -60,7 +60,11 @@ component med_sync_control is DEBUG_TX_CONTROL : out std_logic_vector(31 downto 0); DEBUG_RX_CONTROL : out std_logic_vector(31 downto 0); STAT_RESET : out std_logic_vector(31 downto 0); - DEBUG_OUT : out std_logic_vector(31 downto 0) + DEBUG_OUT : out std_logic_vector(31 downto 0); + + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX + ); end component; @@ -73,6 +77,7 @@ signal clear_m : std_logic := '1'; signal reset_s : std_logic := '1'; signal clear_s : std_logic := '1'; +signal BUS_RX : CTRLBUS_RX; signal med2int_m, med2int_s : MED2INT; signal int2med_m, int2med_s : INT2MED; @@ -276,7 +281,9 @@ THE_MASTER : med_sync_control DEBUG_TX_CONTROL => open, DEBUG_RX_CONTROL => open, STAT_RESET => open, - DEBUG_OUT => open + DEBUG_OUT => open, + + BUS_RX => BUS_RX ); @@ -326,7 +333,10 @@ THE_SLAVE : med_sync_control DEBUG_TX_CONTROL => open, DEBUG_RX_CONTROL => open, STAT_RESET => open, - DEBUG_OUT => open + DEBUG_OUT => open, + + BUS_RX => BUS_RX + ); end architecture; diff --git a/media_interfaces/sync/tx_control.vhd b/media_interfaces/sync/tx_control.vhd index a0f98c0..69ed56c 100644 --- a/media_interfaces/sync/tx_control.vhd +++ b/media_interfaces/sync/tx_control.vhd @@ -67,6 +67,10 @@ architecture arch of tx_control is signal ram_empty : std_logic; signal ram_afull : std_logic; + signal ram_read_addr1 : unsigned(7 downto 0) := (others => '0'); + signal ram_read_addr2 : unsigned(7 downto 0) := (others => '0'); + + signal request_position_q : std_logic_vector( 7 downto 0); signal restart_position_q : std_logic_vector( 7 downto 0); signal request_position_i : std_logic_vector( 7 downto 0); @@ -107,7 +111,8 @@ architecture arch of tx_control is signal first_idle : std_logic; signal toggle_idle : std_logic := '0'; - -- signal ENABLE_SEND_CHKSUM : std_logic := '0'; + signal send_chksum_counter : std_logic_vector(7 downto 0) := x"00"; + begin ---------------------------------------------------------------------- @@ -187,7 +192,10 @@ begin if tx_allow_qtx = '0' then ram_read_addr <= (others => '0'); elsif load_read_pointer_i = '1' then + --BUGBUG + ram_read_addr1 <= ram_read_addr; ram_read_addr <= unsigned(restart_position_i); + ram_read_addr2 <= ram_read_addr; elsif ram_read = '1' then ram_read_addr <= ram_read_addr + to_unsigned(1,1); end if; @@ -279,6 +287,7 @@ begin TX_DATA_OUT <= ram_dout(15 downto 8); when SEND_CHKSUM_L => + send_chksum_counter <= std_logic_vector(unsigned(send_chksum_counter) + 1); TX_DATA_OUT <= K_EOP; TX_K_OUT <= '1'; load_sop <= '0'; @@ -528,9 +537,12 @@ begin DEBUG_OUT(9) <= ram_write; DEBUG_OUT(13 downto 10) <= state_bits; DEBUG_OUT(15 downto 14) <= "00"; - DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0); - DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0); - +-- DEBUG_OUT(23 downto 16) <= tx_data_200(7 downto 0); +-- DEBUG_OUT(31 downto 24) <= ram_dout(7 downto 0); +-- DEBUG_OUT(31 downto 24) <= send_chksum_counter; + DEBUG_OUT(23 downto 16) <= ram_read_addr1; + DEBUG_OUT(31 downto 24) <= ram_read_addr2; + process(CLK_100) begin if rising_edge(CLK_100) then -- 2.43.0