From 232bc7e40d82f806e6cb22369d4aee0341ab43d0 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Sat, 20 Jun 2015 09:53:35 +0200 Subject: [PATCH] Maybe fixing the Baseline follower --- ADC/source/adc_handler.vhd | 12 ++++++------ ADC/source/adc_package.vhd | 6 +++--- ADC/source/adc_processor_cfd_ch.vhd | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/ADC/source/adc_handler.vhd b/ADC/source/adc_handler.vhd index 2de252c..dccabd5 100644 --- a/ADC/source/adc_handler.vhd +++ b/ADC/source/adc_handler.vhd @@ -507,9 +507,9 @@ begin when x"1c" => BUS_TX.data(1 downto 0) <= std_logic_vector(to_unsigned(config_cfd.DebugMode, 2)); when x"1d" => BUS_TX.data(7 downto 0) <= std_logic_vector(config_cfd.IntegrateWindow); - BUS_TX.data(12 downto 8) <= std_logic_vector(config_cfd.CFDDelay); - BUS_TX.data(16 downto 13) <= std_logic_vector(config_cfd.CFDMult); - BUS_TX.data(20 downto 17) <= std_logic_vector(config_cfd.CFDMultDly); + BUS_TX.data(12 downto 8) <= std_logic_vector(resize(config_cfd.CFDDelay,5)); + BUS_TX.data(16 downto 13) <= std_logic_vector(resize(config_cfd.CFDMult,4)); + BUS_TX.data(20 downto 17) <= std_logic_vector(resize(config_cfd.CFDMultDly,4)); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; @@ -555,9 +555,9 @@ begin when x"1c" => config_cfd.DebugMode <= to_integer(unsigned(BUS_RX.data(1 downto 0))); when x"1d" => config_cfd.IntegrateWindow <= unsigned(BUS_RX.data(7 downto 0)); - config_cfd.CFDDelay <= unsigned(BUS_RX.data(12 downto 8)); - config_cfd.CFDMult <= unsigned(BUS_RX.data(16 downto 13)); - config_cfd.CFDMultDly <= unsigned(BUS_RX.data(20 downto 17)); + config_cfd.CFDDelay <= resize(unsigned(BUS_RX.data(12 downto 8)), config_cfd.CFDDelay'length); + config_cfd.CFDMult <= resize(unsigned(BUS_RX.data(16 downto 13)), config_cfd.CFDMult'length); + config_cfd.CFDMultDly <= resize(unsigned(BUS_RX.data(20 downto 17)), config.CFDMult'length); when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd index cfd39ca..f832152 100644 --- a/ADC/source/adc_package.vhd +++ b/ADC/source/adc_package.vhd @@ -50,9 +50,9 @@ package adc_package is PolarityInvert : std_logic; BaselineAverage : unsigned(4 downto 0); BaselineAlwaysOn : std_logic; - CFDDelay : unsigned(4 downto 0); - CFDMult : unsigned(3 downto 0); - CFDMultDly : unsigned(3 downto 0); + CFDDelay : unsigned(2 downto 0); + CFDMult : unsigned(2 downto 0); + CFDMultDly : unsigned(2 downto 0); IntegrateWindow : unsigned(7 downto 0); TriggerDelay : unsigned(11 downto 0); CheckWord1 : std_logic_vector(RESOLUTION - 1 downto 0); diff --git a/ADC/source/adc_processor_cfd_ch.vhd b/ADC/source/adc_processor_cfd_ch.vhd index aee508c..c7878a1 100644 --- a/ADC/source/adc_processor_cfd_ch.vhd +++ b/ADC/source/adc_processor_cfd_ch.vhd @@ -35,7 +35,7 @@ architecture arch of adc_processor_cfd_ch is constant RESOLUTION_CFD : integer := RESOLUTION_PROD + 1; -- this should be 16 to fit into the readout ram constant RESOLUTION_BASEAVG : integer := RESOLUTION + 2 ** CONF.BaselineAverage'length - 1; - constant LENGTH_BASEDLY : integer := 32; -- longer than typical pulses? + constant LENGTH_BASEDLY : integer := 128; -- longer than typical pulses? constant LENGTH_CFDDLY : integer := 2 ** CONF.CFDDelay'length; constant LENGTH_INTDLY : integer := 3; -- must match CFD/zeroX calculation chain -- 2.43.0