From 2354457e8e9d5c7b6dc110f4e0cc822346c1fce6 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 7 Dec 2015 13:26:19 +0100 Subject: [PATCH] changing clock manager timing again --- code/clock_reset_handler.vhd | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/code/clock_reset_handler.vhd b/code/clock_reset_handler.vhd index 77ba5d9..fe4a104 100644 --- a/code/clock_reset_handler.vhd +++ b/code/clock_reset_handler.vhd @@ -47,7 +47,7 @@ signal pll_int_lock, pll_ext_lock : std_logic; signal wait_for_lock : std_logic := '1'; signal clock_select : std_logic := '0'; -signal timer : unsigned(26 downto 0) := (others => '0'); +signal timer : unsigned(27 downto 0) := (others => '0'); signal clear_n_i : std_logic := '0'; signal reset_i : std_logic; @@ -169,21 +169,24 @@ gen_norecov_clock : if USE_RXCLOCK = c_NO generate process begin wait until rising_edge(INT_CLK_IN); - if timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '0' then --after 135us or 8.8ms - timer <= timer + 1; + if timer(26-CLOCK_FAST_SELECT*11) = '0' and timer(27-CLOCK_FAST_SELECT*11) = '0' then + clock_select <= '0'; + end if; + if timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(25-CLOCK_FAST_SELECT*11 downto 0) = 0 then --after 135us or 8.8ms clock_select <= pll_ext_lock; - elsif timer(26-CLOCK_FAST_SELECT*11) = '1' and timer(0) = '1' then --after 135us or 8.8ms plus 1 + end if; + + if timer(27-CLOCK_FAST_SELECT*11) = '1' then --after 135us or 8.8ms plus 1 timer <= timer; else timer <= timer + 1; - clock_select <= '0'; end if; end process; end generate; -clear_n_i <= timer(26-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN); +clear_n_i <= timer(27-CLOCK_FAST_SELECT*11) when rising_edge(INT_CLK_IN); --------------------------------------------------------------------------- -- Reset generation -- 2.43.0