From 24473373a0c3f8170dd8318d4892b45ac5835913 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 31 Jul 2022 09:40:47 +0200 Subject: [PATCH] recompilation with new RX_RB --- gbe/tomcat_gbe.vhd | 70 ++++++++++++++++++++++++++++++---------------- 1 file changed, 46 insertions(+), 24 deletions(-) diff --git a/gbe/tomcat_gbe.vhd b/gbe/tomcat_gbe.vhd index 0537adf..258b503 100644 --- a/gbe/tomcat_gbe.vhd +++ b/gbe/tomcat_gbe.vhd @@ -132,7 +132,8 @@ architecture arch of tomcat_gbe is -- 8 : fifo_eof -- 7..0: fifo_data type dl_rx_data_t is array(0 to 1) of std_logic_vector(10 downto 0); - signal dl_rx_data : dl_rx_data_t; + signal dl_rx_data : dl_rx_data_t; + signal dl_rx_data_q : dl_rx_data_t; signal dl_rx_frame_req : std_logic_vector(1 downto 0); signal dl_rx_frame_ack : std_logic_vector(1 downto 0); signal dl_rx_frame_avail : std_logic_vector(1 downto 0); @@ -155,7 +156,6 @@ architecture arch of tomcat_gbe is signal switch_rx_data : std_logic_vector(10 downto 0); -- 1:n MUX to 1:2 MUXes - signal dl_rx_port_sel : std_logic_vector(1 downto 0); signal dl_rx_port_mux : std_logic_vector(3 downto 0); signal ul_tx_port_sel : std_logic; signal dl_tx_port_sel : std_logic; @@ -227,7 +227,7 @@ begin --------------------------------------------------------------------------- GBE_SFP_INTERFACE: entity gbe_med_fifo generic map( - SERDES_NUM => 3 + SERDES_NUM => 0 ) port map( RESET => reset_i, @@ -263,17 +263,17 @@ begin TICK_MS_IN => tick_ms_int, -- Debug STATUS_OUT => status(7 downto 0), --- DEBUG_OUT => open - DEBUG_OUT(9 downto 0) => debug(9 downto 0), - DEBUG_OUT(13 downto 10) => debug(23 downto 20) + DEBUG_OUT => open ); + debug(127 downto 34) <= (others => '0'); + --------------------------------------------------------------------------- -- GbE interface (copper) --------------------------------------------------------------------------- GBE_COPPER_INTERFACE: entity gbe_med_fifo generic map( - SERDES_NUM => 0 + SERDES_NUM => 3 ) port map( RESET => reset_i, @@ -305,17 +305,9 @@ begin TICK_MS_IN => tick_ms_int, -- Debug STATUS_OUT => open, --- DEBUG_OUT => open - DEBUG_OUT(9 downto 0) => debug(19 downto 10), - DEBUG_OUT(13 downto 10) => debug(27 downto 24) + DEBUG_OUT => open ); --- debug(19 downto 10) <= (others => '0'); - - debug(32 downto 28) <= (others => '0'); - - debug(33) <= clk_sys; - --------------------------------------------------------------------------- --------------------------------------------------------------------------- THE_SGL_CTRL: entity sgl_ctrl @@ -334,7 +326,7 @@ begin DL_FRAME_ACK_IN(1 downto 0) => dl_rx_frame_ack, -- DL RXn sent acknowledge -- CPU port -- not needed -- MUX control - DL_RX_PORT_SEL_OUT(1 downto 0) => dl_rx_port_sel, + DL_RX_PORT_SEL_OUT(1 downto 0) => open, DL_RX_PORT_MUX_OUT => dl_rx_port_mux, DL_TX_PORT_SEL_OUT => dl_tx_port_sel, LOCAL_TX_PORT_SEL_OUT => local_tx_port_sel, @@ -343,13 +335,43 @@ begin DEBUG => sgl_debug --open ); +-- debug(19..0) are on INTCOM +-- debug(33..20) are on GPIO +-- 33 = CLK2 (white/green) +-- 32 = CLK1 (white/blue) + + debug(7 downto 0) <= ul_rx_data(7 downto 0); + debug(15 downto 8) <= ul_tx_data(7 downto 0); + debug(16) <= ul_rx_data(9); + debug(17) <= ul_tx_data(9); + debug(18) <= ul_rx_data(10); + debug(19) <= ul_tx_data(10); + debug(20) <= ul_rx_data(8); + debug(21) <= ul_tx_data(8); + debug(22) <= ul_rx_frame_req; + debug(23) <= ul_rx_frame_ack; + debug(24) <= ul_rx_frame_avail; + debug(25) <= dl_rx_frame_req(0); + debug(26) <= dl_rx_frame_ack(0); + debug(27) <= dl_rx_frame_avail(0); + debug(31 downto 28) <= sgl_debug(3 downto 0); + debug(32) <= dl_rx_port_mux(1); + debug(33) <= clk_sys; + +--------------------------------------------------------------------------- +-- Multiplexers for data streams +--------------------------------------------------------------------------- + THE_PIPELINING: for I in 0 to 1 generate + dl_rx_data_q(I) <= dl_rx_data(I) when rising_edge(clk_sys); + end generate THE_PIPELINING; + local_rx_data <= (others => '0'); -- no local CPU port - THE_DL_RX_MUX: process( dl_rx_port_sel, dl_rx_data ) + THE_DL_RX_MUX: process( dl_rx_port_mux, dl_rx_data_q ) begin - case dl_rx_port_sel is - when b"01" => switch_rx_data <= dl_rx_data(0); - when b"10" => switch_rx_data <= dl_rx_data(1); + case dl_rx_port_mux is + when x"0" => switch_rx_data <= dl_rx_data_q(0); + when x"1" => switch_rx_data <= dl_rx_data_q(1); when others => switch_rx_data <= (others => '0'); end case; end process THE_DL_RX_MUX; @@ -594,10 +616,10 @@ begin LED_SFP_GREEN <= not (status(0) and status(1) and status(2)); --'0'; LED_SFP_YELLOW <= not status(5); --'0'; LED_SFP_RED <= not status(6); --'0'; - LED(3) <= not additional_reg(7); --'0'; - LED(2) <= not additional_reg(6); --'0'; + LED(3) <= not '1'; --additional_reg(7); --'0'; + LED(2) <= not '1'; --additional_reg(6); --'0'; LED(1) <= not '1'; --additional_reg(5); --'0'; - LED(0) <= not '1'; --additional_reg(4); --'0'; + LED(0) <= not additional_reg(4); --'0'; -- 0 red -- 1 orange -- 2.43.0