From 245a028fcc9a063ea8fc009fcb41c73661369a14 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 4 Oct 2007 12:32:11 +0000 Subject: [PATCH] small changes to 16bit files, Jan --- testbench/trb_net16_dummy_apl.vhd | 41 +++++++++++--------- testbench/trb_net16_dummy_passive_apl.vhd | 41 ++++++++++++++++---- testbench/trb_net_dummy_apl.vhd | 46 ++++++++++++++++------- trb_net16_base_api.vhd | 14 +++++-- trb_net16_passive_apimbuf.vhd | 2 +- 5 files changed, 102 insertions(+), 42 deletions(-) diff --git a/testbench/trb_net16_dummy_apl.vhd b/testbench/trb_net16_dummy_apl.vhd index 4b729d4..66221f3 100644 --- a/testbench/trb_net16_dummy_apl.vhd +++ b/testbench/trb_net16_dummy_apl.vhd @@ -1,5 +1,7 @@ -- this is a dummy apl, just sending data into an active api +--THIS IS NOT WORKING !!!! + LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; @@ -12,8 +14,8 @@ use work.trb_net_std.all; entity trb_net16_dummy_apl is generic ( TARGET_ADDRESS : std_logic_vector (15 downto 0) := x"ffff"; - PREFILL_LENGTH : integer := 0; - TRANSFER_LENGTH : integer := 0 -- length of dummy data + PREFILL_LENGTH : integer := 3; + TRANSFER_LENGTH : integer := 3 -- length of dummy data -- might not work with transfer_length > api_fifo -- because of incorrect handling of fifo_full_in! -- shorttransfer is not working too @@ -73,22 +75,31 @@ begin end generate; - SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET) + SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT) begin -- process - next_APL_SEND_OUT <= '0'; + next_APL_SEND_OUT <= buf_APL_SEND_OUT; next_state <= MY_ERROR; next_counter <= reg_counter; next_APL_PACKET_NUM_OUT <= packet_counter; next_APL_WRITE_OUT <= '0'; + next_APL_DATA_OUT <= (others => '0'); + next_packet_counter <= packet_counter; ------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------- if current_state = IDLE then if APL_FIFO_FULL_IN = '1' or reg_counter = PREFILL_LENGTH then next_state <= RUNNING; + next_APL_SEND_OUT <= '0'; else + if buf_APL_SEND_OUT = '1' or APL_RUN_IN = '0' then + next_APL_SEND_OUT <= '1'; + end if; next_state <= WRITING; - end if; + next_APL_DATA_OUT <= (1 => '1', others => '0'); + next_APL_WRITE_OUT <= '1'; + next_packet_counter <= "01"; + end if; ------------------------------------------------------------------------- -- WRITING ------------------------------------------------------------------------- @@ -96,18 +107,13 @@ begin next_state <= WRITING; if packet_counter = "01" then next_APL_WRITE_OUT <= '1'; - next_APL_SEND_OUT <= '1'; - next_APL_DATA_OUT <= (1 => '1', others => '0'); + next_APL_DATA_OUT <= (0 => '1', others => '0'); next_packet_counter <= "10"; elsif packet_counter = "10" then next_APL_WRITE_OUT <= '1'; - next_APL_SEND_OUT <= '1'; - next_APL_DATA_OUT <= (0 => '1', others => '0'); - next_packet_counter <= "11"; - else - next_APL_WRITE_OUT <= '1'; - next_APL_SEND_OUT <= '1'; next_APL_DATA_OUT <= reg_counter; + next_packet_counter <= "11"; + elsif packet_counter <= "11" then next_state <= IDLE; next_packet_counter <= "01"; next_counter <= reg_counter +1; @@ -116,14 +122,13 @@ begin -- RUNNING ----------------------------------------------------------------------- elsif current_state = RUNNING then - next_APL_SEND_OUT <= '1'; + next_APL_SEND_OUT <= '0'; if reg_counter = TRANSFER_LENGTH then next_state <= WAITING; else next_state <= RUNNING; if APL_FIFO_FULL_IN = '0' then next_counter <= reg_counter +1; - next_APL_WRITE_OUT <= '1'; end if; end if; ----------------------------------------------------------------------- @@ -143,7 +148,7 @@ begin end process; APL_DATA_OUT(15 downto 0) <= buf_APL_DATA_OUT; -APL_PACKET_NUM_OUT <= buf_APL_PACKET_NUM_OUT; +APL_PACKET_NUM_OUT <= packet_counter; APL_WRITE_OUT <= buf_APL_WRITE_OUT; APL_SEND_OUT <= buf_APL_SEND_OUT; @@ -153,6 +158,7 @@ APL_SEND_OUT <= buf_APL_SEND_OUT; if RESET = '1' then current_state <= IDLE; reg_counter <= (others => '0'); + packet_counter <= "01"; buf_APL_DATA_OUT <= (others => '0'); buf_APL_PACKET_NUM_OUT <= "00"; buf_APL_WRITE_OUT <= '0'; @@ -160,6 +166,7 @@ APL_SEND_OUT <= buf_APL_SEND_OUT; elsif CLK_EN = '1' then reg_counter <= next_counter; current_state <= next_state; + packet_counter <= next_packet_counter; buf_APL_DATA_OUT <= next_APL_DATA_OUT; buf_APL_PACKET_NUM_OUT <= next_APL_PACKET_NUM_OUT; buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; @@ -168,4 +175,4 @@ APL_SEND_OUT <= buf_APL_SEND_OUT; end if; end process; -end entity; +end architecture; diff --git a/testbench/trb_net16_dummy_passive_apl.vhd b/testbench/trb_net16_dummy_passive_apl.vhd index bd01bdf..19fa02b 100644 --- a/testbench/trb_net16_dummy_passive_apl.vhd +++ b/testbench/trb_net16_dummy_passive_apl.vhd @@ -59,6 +59,8 @@ architecture trb_net16_dummy_passive_apl_arch of trb_net16_dummy_passive_apl is signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; signal next_packet_counter, packet_counter : std_logic_vector(1 downto 0); + signal state_bits : std_logic_vector(2 downto 0); + signal current_TYPE_IN, saved_PACKET_TYPE_IN : std_logic_vector(2 downto 0); begin APL_READ_OUT <= '1'; --just read, do not check @@ -73,9 +75,36 @@ begin CHECK_2:if TRANSFER_LENGTH =0 generate APL_SHORT_TRANSFER_OUT <= '1'; end generate; + + process(current_state) + begin + case current_state is + when IDLE => state_bits <= "000"; + when WRITING => state_bits <= "001"; + when RUNNING => state_bits <= "010"; + when WAITING => state_bits <= "011"; + when MY_ERROR => state_bits <= "100"; + when others => state_bits <= "111"; + end case; + end process; + --this holds the current packet type from fifo_to_apl + process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + saved_PACKET_TYPE_IN <= TYPE_ILLEGAL; + elsif APL_PACKET_NUM_IN = "00" then + saved_PACKET_TYPE_IN <= APL_TYP_IN; + end if; + end if; + end process; + --create comb. real packet type + current_TYPE_IN <= APL_TYP_IN when (APL_PACKET_NUM_IN = "00" and RESET = '0') + else saved_PACKET_TYPE_IN; - SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, packet_counter, buf_APL_SEND_OUT) + SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET, + packet_counter, buf_APL_SEND_OUT, current_TYPE_IN, APL_DATAREADY_IN, APL_PACKET_NUM_IN) begin -- process next_APL_SEND_OUT <= buf_APL_SEND_OUT; next_state <= MY_ERROR; @@ -92,9 +121,7 @@ begin next_state <= RUNNING; next_APL_SEND_OUT <= '0'; else - if buf_APL_SEND_OUT = '1' or APL_RUN_IN = '0' then - next_APL_SEND_OUT <= '1'; - end if; + next_APL_SEND_OUT <= '1'; next_state <= WRITING; next_APL_DATA_OUT <= (1 => '1', others => '0'); next_APL_WRITE_OUT <= '1'; @@ -135,11 +162,11 @@ begin -- WAITING ----------------------------------------------------------------------- elsif current_state = WAITING then - if not (APL_TYP_IN = TYPE_TRM and APL_DATAREADY_IN = '1') then - next_state <= WAITING; - else + if (current_TYPE_IN = TYPE_TRM and APL_PACKET_NUM_IN = "11" and APL_DATAREADY_IN = '1') then next_state <= IDLE; next_counter <= (others => '0'); + else + next_state <= WAITING; end if; end if; -- end state switch if RESET = '1' then diff --git a/testbench/trb_net_dummy_apl.vhd b/testbench/trb_net_dummy_apl.vhd index bd8981f..a35774e 100644 --- a/testbench/trb_net_dummy_apl.vhd +++ b/testbench/trb_net_dummy_apl.vhd @@ -11,8 +11,11 @@ use work.trb_net_std.all; entity trb_net_dummy_apl is generic (TARGET_ADDRESS : STD_LOGIC_VECTOR (15 downto 0) := x"ffff"; - PREFILL_LENGTH : integer := 3; - TRANSFER_LENGTH : integer := 6); -- length of dummy data + PREFILL_LENGTH : integer := 0; + TRANSFER_LENGTH : integer := 0); -- length of dummy data + -- might not work with transfer_length > api_fifo + -- because of incorrect handling of fifo_full_in! + -- shorttransfer is not working too port( -- Misc @@ -49,15 +52,18 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is type SENDER_STATE is (IDLE, RUNNING, WAITING, MY_ERROR); signal current_state, next_state : SENDER_STATE; - signal next_counter, reg_counter : std_logic_vector(47 downto 0); - + signal next_counter, reg_counter : std_logic_vector(23 downto 0); + signal buf_APL_DATA_OUT, next_APL_DATA_OUT : std_logic_vector(23 downto 0); + signal buf_APL_WRITE_OUT, next_APL_WRITE_OUT : std_logic; + signal buf_APL_SEND_OUT, next_APL_SEND_OUT : std_logic; + begin APL_READ_OUT <= '1'; --just read, do not check APL_DTYPE_OUT <= x"1"; APL_ERROR_PATTERN_OUT <= x"12345678"; APL_TARGET_ADDRESS_OUT <= TARGET_ADDRESS; - APL_DATA_OUT <= reg_counter; + --APL_DATA_OUT <= reg_counter; CHECK_1:if TRANSFER_LENGTH >0 generate APL_SHORT_TRANSFER_OUT <= '0'; @@ -69,10 +75,10 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is SENDER_CTRL: process (current_state, APL_FIFO_FULL_IN, reg_counter, APL_RUN_IN, RESET) begin -- process - APL_SEND_OUT <= '0'; + next_APL_SEND_OUT <= '0'; next_state <= MY_ERROR; next_counter <= reg_counter; - APL_WRITE_OUT <= '0'; + next_APL_WRITE_OUT <= '0'; ------------------------------------------------------------------------- -- IDLE ------------------------------------------------------------------------- @@ -82,27 +88,27 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is else next_state <= IDLE; next_counter <= reg_counter +1; - APL_WRITE_OUT <= '1'; + next_APL_WRITE_OUT <= '1'; end if; ----------------------------------------------------------------------- -- RUNNING ----------------------------------------------------------------------- elsif current_state = RUNNING then - APL_SEND_OUT <= '1'; + next_APL_SEND_OUT <= '1'; if reg_counter = TRANSFER_LENGTH then next_state <= WAITING; else next_state <= RUNNING; if APL_FIFO_FULL_IN = '0' then next_counter <= reg_counter +1; - APL_WRITE_OUT <= '1'; + next_APL_WRITE_OUT <= '1'; end if; end if; ----------------------------------------------------------------------- -- WAITING ----------------------------------------------------------------------- elsif current_state = WAITING then - if APL_RUN_IN = '1' then + if APL_RUN_IN = '1' or buf_APL_SEND_OUT = '1' then next_state <= WAITING; else next_state <= IDLE; @@ -110,10 +116,14 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is end if; end if; -- end state switch if RESET = '1' then - APL_WRITE_OUT <= '0'; + next_APL_WRITE_OUT <= '0'; end if; end process; +APL_DATA_OUT(47 downto 24) <= (others => '0'); +APL_DATA_OUT(23 downto 0) <= buf_APL_DATA_OUT; +APL_WRITE_OUT <= buf_APL_WRITE_OUT; +APL_SEND_OUT <= buf_APL_SEND_OUT; CLK_REG: process(CLK) begin @@ -121,14 +131,22 @@ architecture trb_net_dummy_apl_arch of trb_net_dummy_apl is if RESET = '1' then current_state <= IDLE; reg_counter <= (others => '0'); + buf_APL_DATA_OUT <= (others => '0'); + buf_APL_WRITE_OUT <= '0'; + buf_APL_SEND_OUT <= '0'; + elsif CLK_EN = '1' then reg_counter <= next_counter; current_state <= next_state; - + buf_APL_DATA_OUT <= reg_counter; + buf_APL_WRITE_OUT <= next_APL_WRITE_OUT; + buf_APL_SEND_OUT <= next_APL_SEND_OUT; else reg_counter <= reg_counter; current_state <= current_state; - + buf_APL_DATA_OUT <= buf_APL_DATA_OUT; + buf_APL_WRITE_OUT <= buf_APL_WRITE_OUT; + buf_APL_SEND_OUT <= buf_APL_SEND_OUT; end if; end if; end process; diff --git a/trb_net16_base_api.vhd b/trb_net16_base_api.vhd index 5bbc61a..1d6c0a5 100644 --- a/trb_net16_base_api.vhd +++ b/trb_net16_base_api.vhd @@ -627,6 +627,10 @@ begin end if; if master_counter = "00" then next_state <= WAITING; + next_INT_MASTER_DATAREADY_OUT <= '0'; + if API_TYPE = 0 then --here is the end of the passive transfer + next_sequence_counter <= sequence_counter +1; + end if; else next_state <= SEND_TRAILER; end if; @@ -646,21 +650,25 @@ begin -- part 2: connection to apl -- if fifo_to_apl_empty = '0' then - if fifo_to_apl_empty = '0' and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') + if fifo_to_apl_empty = '0' --and not (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') and fifo_to_apl_packet_num_out /= "00" then --is this really correct???? next_APL_DATAREADY_OUT <= '1'; end if; -- read/no read if (reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1') or fifo_to_apl_packet_num_out = "00" then -- valid read - fifo_to_apl_read <= '1'; + if fifo_to_apl_empty = '0' then + fifo_to_apl_read <= '1'; + end if; if (reg_APL_TYP_OUT = TYPE_TRM or reg_APL_TYP_OUT = TYPE_HDR) then next_slave_running <= '1'; end if; if reg_APL_TYP_OUT = TYPE_TRM and reg_APL_PACKET_NUM_OUT= "11" and (APL_READ_IN = '1' and reg_APL_DATAREADY_OUT = '1') then --fifo_to_apl_read = '1' next_state <= IDLE; - next_sequence_counter <= sequence_counter +1; + if API_TYPE = 1 then + next_sequence_counter <= sequence_counter +1; + end if; end if; end if; -- MISSING: SEQNR check diff --git a/trb_net16_passive_apimbuf.vhd b/trb_net16_passive_apimbuf.vhd index 37f74d4..d6e4cf2 100644 --- a/trb_net16_passive_apimbuf.vhd +++ b/trb_net16_passive_apimbuf.vhd @@ -345,7 +345,7 @@ begin m_READ_OUT(1) <= MED_REPLY_READ_OUT; - ACTIVE_API: trb_net16_passive_api + PASSIVE_API: trb_net16_passive_api generic map (FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, FIFO_TO_APL_DEPTH => FIFO_TO_APL_DEPTH, -- 2.43.0