From 24706bfbecd0f87b46ae2c6d3d0eab5feb233701 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Thu, 11 Jul 2013 18:23:12 +0200
Subject: [PATCH] changed most ui commands to trbnet-Perl-Lib
---
soft/toolbox/jtag_atomic/ui.pl | 4 +
soft/toolbox/jtag_atomic/ui_generators.pl | 185 ++++++++--------------
2 files changed, 69 insertions(+), 120 deletions(-)
diff --git a/soft/toolbox/jtag_atomic/ui.pl b/soft/toolbox/jtag_atomic/ui.pl
index d7c91b1..e0ca209 100755
--- a/soft/toolbox/jtag_atomic/ui.pl
+++ b/soft/toolbox/jtag_atomic/ui.pl
@@ -1,12 +1,14 @@
#!/usr/bin/perl
use strict;
use warnings;
+use HADES::TrbNet;
use lib "./libs/";
use Config::Abstract::Ini;
use POSIX qw(strftime);
use FileHandle;
use Getopt::Long;
use Sys::Syslog;
+
require "./ui_generators.pl";
@@ -35,6 +37,8 @@ if($opt_help or not defined $opt_board) {
exit(0);
}
+die "DAQOPSERVER not set in environment" unless (defined $ENV{'DAQOPSERVER'});
+die "can not connect to trbnet-daemon on $ENV{'DAQOPSERVER'}: ".trb_strerror() unless (defined &trb_init_ports());
sub help(){
diff --git a/soft/toolbox/jtag_atomic/ui_generators.pl b/soft/toolbox/jtag_atomic/ui_generators.pl
index 4605fe1..0e29d69 100644
--- a/soft/toolbox/jtag_atomic/ui_generators.pl
+++ b/soft/toolbox/jtag_atomic/ui_generators.pl
@@ -1,3 +1,11 @@
+#Send a command that writes data
+sub send_write_command {
+ my ($fpga, $dreg, $creg, $val, $cmd) = @_;
+ trb_register_write($fpga, $dreg, $val);
+ trb_register_write($fpga, $creg, $cmd);
+ }
+
+
sub generate_h_read_ram1b_word {
my ($chain, $fpga_addr, $debug_ram1baddr, $debug_ram1bdata, $addr) = @_;
@@ -42,8 +50,11 @@ sub generate_h_man_maps_reset {
reportd "regval: ". substr($regval, 8, 10). "\n";
my $resetnormal = substr($regval, 8, 10);
# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
- my $resetinv = int_to_32bit_hex((~(1<< 10)) & hex($resetnormal));
+ my $resetinv = (~(1<< 10)) & hex($resetnormal);
execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$resetinv 2>&1 && sleep 1 && trbcmd w $fpga_addr $conf_signals_addr $resetnormal 2>&1", "");
+ trb_register_write($fpga_addr, $conf_signals_addr,$resetinv);
+ sleep 1;
+ trb_register_write($fpga_addr, $conf_signals_addr,hex($resetnormal));
}
}
@@ -51,64 +62,38 @@ sub generate_h_maps_start_signal {
my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
return sub {
init_msg( "generate MAPS start $onoroff " . $chain);
- # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
- my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
- reportd "regval: ". substr($regval, 8, 10). "\n";
- my $before = substr($regval, 8, 10);
-# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
- my $newval;
if($onoroff == 0) {
- #off
- $newval = int_to_32bit_hex((~(1<< 9)) & hex($before));
- }
+ trb_register_clearbit($fpga_addr,$conf_signals_addr,(1 << 9));
+ }
else {
- #on
- $newval = int_to_32bit_hex(((1<< 9)) | hex($before));
- }
- execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ trb_register_setbit($fpga_addr,$conf_signals_addr,(1 << 9));
+ }
}
}
sub generate_h_maps_reset_signal {
my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
return sub {
init_msg("MAPS reset signal $onoroff " . $chain);
- # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
- my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
- reportd "regval: ". substr($regval, 8, 10). "\n";
- my $before = substr($regval, 8, 10);
-# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
- my $newval;
if($onoroff == 0) {
- #off
- $newval = int_to_32bit_hex((~(1<< 11)) & hex($before));
- }
+ trb_register_clearbit($fpga_addr,$conf_signals_addr,(1 << 11));
+ }
else {
- #on
- $newval = int_to_32bit_hex(((1<< 11)) | hex($before));
- }
- execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval", "");
+ trb_register_setbit($fpga_addr,$conf_signals_addr,(1 << 11));
+ }
}
}
+
sub generate_h_maps_clk_signal {
my ($onoroff, $chain, $fpga_addr, $conf_signals_addr) = @_;
return sub {
init_msg("generate MAPS clk $onoroff " . $chain);
- # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
- my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_signals_addr");
- reportd "regval: ". substr($regval, 8, 10). "\n";
- my $before = substr($regval, 8, 10);
-# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
- my $newval;
if($onoroff == 0) {
- #off
- $newval = int_to_32bit_hex((~(1<< 13)) & hex($before));
- }
+ trb_register_clearbit($fpga_addr,$conf_signals_addr,(1 << 13));
+ }
else {
- #on
- $newval = int_to_32bit_hex(((1<< 13)) | hex($before));
- }
- execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x$newval\n", "");
+ trb_register_setbit($fpga_addr,$conf_signals_addr,(1 << 13));
+ }
}
}
@@ -124,25 +109,15 @@ sub generate_h_set_timing_10mhz {
my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
return sub {
init_msg("timing 10 MHz $chain.");
- my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
-trbcmd w $fpga_addr $data_reg_addr 0x0000000A 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
-trbcmd w $fpga_addr $data_reg_addr 0x00000003 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x00000008 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x00000004 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
-trbcmd w $fpga_addr $data_reg_addr 0x00000009 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
- #reportd $cmdline;
- #system($cmdline);
- execute_shell_command($cmdline, "");
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x0000000A); #M26C_CMD_STOP
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x0000000A,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000003,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000008,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000004,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000004,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000004,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000009,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x00000009); #M26C_CMD_START
}
}
@@ -150,59 +125,40 @@ sub generate_h_set_timing_1mhz {
my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
return sub {
init_msg("timing 1 MHz $chain.");
- my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
-trbcmd w $fpga_addr $data_reg_addr 0x00000064 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
-trbcmd w $fpga_addr $data_reg_addr 0x00000031 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x00000062 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x00000030 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
-trbcmd w $fpga_addr $data_reg_addr 0x00000063 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
- execute_shell_command($cmdline, "");
- }
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x0000000A); #M26C_CMD_STOP
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000064,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000031,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000062,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000030,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000030,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000030,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x00000063,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x00000009); #M26C_CMD_START
+ }
}
sub generate_h_set_timing_100khz {
my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr) = @_;
return sub {
init_msg("timing 100 kHz $chain.");
- my $cmdline = "trbcmd w $fpga_addr $cmd_reg_addr 0x0000000A 2>&1 # COMMAND: M26C_CMD_STOP
-trbcmd w $fpga_addr $data_reg_addr 0x000003E8 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000040 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
-trbcmd w $fpga_addr $data_reg_addr 0x000001CC 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000042 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x000003C0 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000044 2>&1 # COMMAND: M26C_CMD_SET_JTAG_CLOCK_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000046 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME1
-trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000048 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME2
-trbcmd w $fpga_addr $data_reg_addr 0x000001F0 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004a 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SAMPLE_TIME3
-trbcmd w $fpga_addr $data_reg_addr 0x000003E7 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x0000004c 2>&1 # COMMAND: M26C_CMD_SET_JTAG_SET_DATA_TIME
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000009 2>&1 # COMMAND: M26C_CMD_START";
- execute_shell_command($cmdline, "");
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x0000000A); #M26C_CMD_STOP
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000003E8,0x00000040);#M26C_CMD_SET_JTAG_CLOCK_CYCLE_LENGTH
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000001CC,0x00000042);#M26C_CMD_SET_JTAG_CLOCK_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000003C0,0x00000044);#M26C_CMD_SET_JTAG_CLOCK_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000001F0,0x00000046);#M26C_CMD_SET_JTAG_SAMPLE_TIME1
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000001F0,0x00000048);#M26C_CMD_SET_JTAG_SAMPLE_TIME2
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000001F0,0x0000004a);#M26C_CMD_SET_JTAG_SAMPLE_TIME3
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0x000003E7,0x0000004c);#M26C_CMD_SET_JTAG_SET_DATA_TIME
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,0,0x00000009); #M26C_CMD_START
}
}
-
sub generate_h_delay {
my($chain, $fpga_addr, $cmd_reg_addr, $data_reg_addr, $delay) = @_;
return sub {
init_msg("Delay $delay $chain.");
- my $cmdline = "trbcmd w $fpga_addr $data_reg_addr 0x".int_to_32bit_hex($delay)." 2>&1 # ADDR_CONTROL_DATA_REGISTER
-trbcmd w $fpga_addr $cmd_reg_addr 0x00000067 2>&1 # COMMAND: M26C_CMD_SET_DELAY_EXPECTED_VALUES";
- execute_shell_command($cmdline, "");
+ send_write_command($fpga_addr,$data_reg_addr,$cmd_reg_addr,$delay,0x00000067);
}
}
@@ -216,8 +172,7 @@ sub generate_h_waitbeforestart_6us {
return;
}
# Set time to wait after finished programming before sending MAPS_start
- execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00000200", ""); # wait before start (counted with 80 MHz)
-
+ trb_register_write($fpga_addr, $conf_waitstart_addr, 0x00000200);# wait before start (counted with 80 MHz)
}
}
@@ -231,7 +186,7 @@ sub generate_h_waitbeforestart_1ms {
return;
}
# Set time to wait after finished programming before sending MAPS_start
- execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x00013880", ""); # wait before start (counted with 80 MHz)
+ trb_register_write($fpga_addr, $conf_waitstart_addr, 0x00013880);# wait before start (counted with 80 MHz)
}
}
@@ -246,7 +201,7 @@ sub generate_h_waitbeforestart_1s {
return;
}
# Set time to wait after finished programming before sending MAPS_start
- execute_shell_command("trbcmd w $fpga_addr $conf_waitstart_addr 0x04C4B400", ""); # wait before start (counted with 80 MHz)
+ trb_register_write($fpga_addr, $conf_waitstart_addr, 0x04C4B400);# wait before start (counted with 80 MHz)
}
}
@@ -255,21 +210,12 @@ sub generate_h_maps_reset {
my ($onoroff, $chain, $chainnr, $fpga_addr, $conf_resets_addr) = @_;
return sub {
init_msg("initseq setting: MAPS reset addr $conf_resets_addr $onoroff " . $chain);
- # set signals_invert bit 10 (reset inverted) temporarily to generate a manual reset
- my $regval = execute_shell_command_return("trbcmd r $fpga_addr $conf_resets_addr");
- reportd "regval: ". substr($regval, 8, 10). "\n";
- my $before = substr($regval, 8, 10);
-# my $resetinv = int_to_32bit_hex((~(0b10000000000)) & hex_to_32bit_int($resetnormal));
- my $newval;
if($onoroff == 0) {
- #off
- $newval = int_to_32bit_hex((~(1<<$chainnr)) & hex($before));
- }
+ trb_register_clearbit($fpga_addr,$conf_signals_addr,(1 << $chainnr));
+ }
else {
- #on
- $newval = int_to_32bit_hex(((1<<$chainnr)) | hex($before));
- }
- execute_shell_command("trbcmd w $fpga_addr $conf_resets_addr 0x$newval", "");
+ trb_register_setbit($fpga_addr,$conf_signals_addr,(1 << $chainnr));
+ }
}
}
@@ -279,17 +225,16 @@ sub generate_h_trig {
return sub {
init_msg("generate trigger addr $conf_trigger_addr " . $board);
# hack: for runjtag trigger single trigger address is used, otherwise setting LSB would be sufficient
- execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0xFFFFFFFF", "");
+ trb_register_write($fpga_addr, $conf_trigger_addr, 0xFFFFFFFF);
}
}
+
sub generate_h_chain_trig {
my ($chain, $chainnr, $fpga_addr, $conf_trigger_addr) = @_;
return sub {
init_msg("generate trigger addr $conf_trigger_addr chainnr:$chainnr " . $chain);
# set bit in trigger register correspondig to chain-# $chainnr
- my $newval;
- $newval = int_to_32bit_hex(((1<<$chainnr)));
- execute_shell_command("trbcmd w $fpga_addr $conf_trigger_addr 0x$newval", "");
+ trb_register_write($fpga_addr, $conf_trigger_addr, 1<<$chainnr);
}
}
@@ -304,7 +249,7 @@ sub generate_h_set_inout {
report('report_general', "TrbNet address missing. Doing nothing.\n");
return;
}
- execute_shell_command("trbcmd w $fpga_addr $conf_signals_addr 0x000002EAA", "");# outputs/inputs not inverted, but activated, RESET activated and inverted (high)
+ trb_register_write($fpga_addr, $conf_signals_addr, 0x000002EAA);
}
}
--
2.43.0