From 24807c6a451195558a677c15c7eeae6d6e9ead1b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 20 Feb 2008 14:17:26 +0000 Subject: [PATCH] new fifo versions, Jan --- .../simulation/xilinx_fifo_dualport_18x1k.vhd | 139 ++++++++++++++++ .../xilinx_fifo_dualport_18x1k_4.vhd | 151 ++++++++++++++++++ xilinx/virtex4/trb_net16_fifo_arch.vhd | 40 ++--- .../virtex4/xilinx_fifo_dualport_18x1k_4.xco | 64 ++++++++ 4 files changed, 374 insertions(+), 20 deletions(-) create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd create mode 100644 xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k_4.vhd create mode 100644 xilinx/virtex4/xilinx_fifo_dualport_18x1k_4.xco diff --git a/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd b/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd new file mode 100644 index 0000000..8ab3e25 --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k.vhd @@ -0,0 +1,139 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_virtex4_fifo_dualport_18x1k.vhd when simulating +-- the core, xilinx_virtex4_fifo_dualport_18x1k. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_dualport_18x1k IS + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +END xilinx_fifo_dualport_18x1k; + +ARCHITECTURE xilinx_fifo_dualport_18x1k_a OF xilinx_fifo_dualport_18x1k IS +-- synopsys translate_off +component wrapped_xilinx_fifo_dualport_18x1k + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_dualport_18x1k use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 3, + c_family => "virtex4", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 0, + c_has_rd_rst => 0, + c_has_almost_full => 0, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 10, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 0, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 768, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 256, + c_prog_empty_thresh_assert_val => 256, + c_has_valid => 0, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 768, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 1024, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 4); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_dualport_18x1k + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + dout => dout, + empty => empty, + full => full); +-- synopsys translate_on + +END xilinx_fifo_dualport_18x1k_a; + diff --git a/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k_4.vhd b/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k_4.vhd new file mode 100644 index 0000000..2dd65be --- /dev/null +++ b/xilinx/virtex4/simulation/xilinx_fifo_dualport_18x1k_4.vhd @@ -0,0 +1,151 @@ +-------------------------------------------------------------------------------- +-- This file is owned and controlled by Xilinx and must be used -- +-- solely for design, simulation, implementation and creation of -- +-- design files limited to Xilinx devices or technologies. Use -- +-- with non-Xilinx devices or technologies is expressly prohibited -- +-- and immediately terminates your license. -- +-- -- +-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- +-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR -- +-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION -- +-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION -- +-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS -- +-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- +-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- +-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- +-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- +-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- +-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- +-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- +-- FOR A PARTICULAR PURPOSE. -- +-- -- +-- Xilinx products are not intended for use in life support -- +-- appliances, devices, or systems. Use in such applications are -- +-- expressly prohibited. -- +-- -- +-- (c) Copyright 1995-2005 Xilinx, Inc. -- +-- All rights reserved. -- +-------------------------------------------------------------------------------- +-- You must compile the wrapper file xilinx_fifo_dualport_18x1k_4.vhd when simulating +-- the core, xilinx_fifo_dualport_18x1k_4. When compiling the wrapper file, be sure to +-- reference the XilinxCoreLib VHDL simulation library. For detailed +-- instructions, please refer to the "CORE Generator Help". + +-- The synopsys directives "translate_off/translate_on" specified +-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity +-- synthesis tools. Ensure they are correct for your synthesis tool(s). + +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; +-- synopsys translate_off +Library XilinxCoreLib; +-- synopsys translate_on +ENTITY xilinx_fifo_dualport_18x1k_4 IS + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + almost_full: OUT std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_empty: OUT std_logic; + valid: OUT std_logic; + underflow: OUT std_logic); +END xilinx_fifo_dualport_18x1k_4; + +ARCHITECTURE xilinx_fifo_dualport_18x1k_4_a OF xilinx_fifo_dualport_18x1k_4 IS +-- synopsys translate_off +component wrapped_xilinx_fifo_dualport_18x1k_4 + port ( + din: IN std_logic_VECTOR(17 downto 0); + rd_clk: IN std_logic; + rd_en: IN std_logic; + rst: IN std_logic; + wr_clk: IN std_logic; + wr_en: IN std_logic; + almost_full: OUT std_logic; + dout: OUT std_logic_VECTOR(17 downto 0); + empty: OUT std_logic; + full: OUT std_logic; + prog_empty: OUT std_logic; + valid: OUT std_logic; + underflow: OUT std_logic); +end component; + +-- Configuration specification + for all : wrapped_xilinx_fifo_dualport_18x1k_4 use entity XilinxCoreLib.fifo_generator_v2_1(behavioral) + generic map( + c_wr_response_latency => 1, + c_has_rd_data_count => 0, + c_din_width => 18, + c_has_wr_data_count => 0, + c_implementation_type => 2, + c_family => "virtex4", + c_has_wr_rst => 0, + c_underflow_low => 0, + c_has_meminit_file => 0, + c_has_overflow => 0, + c_preload_latency => 1, + c_dout_width => 18, + c_rd_depth => 1024, + c_default_value => "BlankString", + c_mif_file_name => "BlankString", + c_has_underflow => 1, + c_has_rd_rst => 0, + c_has_almost_full => 1, + c_has_rst => 1, + c_data_count_width => 2, + c_has_wr_ack => 0, + c_wr_ack_low => 0, + c_common_clock => 0, + c_rd_pntr_width => 10, + c_has_almost_empty => 0, + c_rd_data_count_width => 2, + c_enable_rlocs => 0, + c_wr_pntr_width => 10, + c_overflow_low => 0, + c_prog_empty_type => 1, + c_optimization_mode => 0, + c_wr_data_count_width => 2, + c_preload_regs => 0, + c_dout_rst_val => "0", + c_has_data_count => 0, + c_prog_full_thresh_negate_val => 768, + c_wr_depth => 1024, + c_prog_empty_thresh_negate_val => 256, + c_prog_empty_thresh_assert_val => 3, + c_has_valid => 1, + c_init_wr_pntr_val => 0, + c_prog_full_thresh_assert_val => 768, + c_has_backup => 0, + c_valid_low => 0, + c_prim_fifo_type => 1024, + c_count_type => 0, + c_prog_full_type => 0, + c_memory_type => 1); +-- synopsys translate_on +BEGIN +-- synopsys translate_off +U0 : wrapped_xilinx_fifo_dualport_18x1k_4 + port map ( + din => din, + rd_clk => rd_clk, + rd_en => rd_en, + rst => rst, + wr_clk => wr_clk, + wr_en => wr_en, + almost_full => almost_full, + dout => dout, + empty => empty, + full => full, + prog_empty => prog_empty, + valid => valid, + underflow => underflow); +-- synopsys translate_on + +END xilinx_fifo_dualport_18x1k_4_a; + diff --git a/xilinx/virtex4/trb_net16_fifo_arch.vhd b/xilinx/virtex4/trb_net16_fifo_arch.vhd index c5a3ff0..2099685 100644 --- a/xilinx/virtex4/trb_net16_fifo_arch.vhd +++ b/xilinx/virtex4/trb_net16_fifo_arch.vhd @@ -5,26 +5,26 @@ USE ieee.std_logic_signed.ALL; USE IEEE.numeric_std.ALL; use work.trb_net_std.all; --- entity trb_net16_fifo is --- generic ( --- USE_VENDOR_CORES : integer range 0 to 1 := c_NO; --- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets --- ); --- port ( --- CLK : in std_logic; --- RESET : in std_logic; --- CLK_EN : in std_logic; --- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data --- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- WRITE_ENABLE_IN : in std_logic; --- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data --- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- READ_ENABLE_IN : in std_logic; --- FULL_OUT : out std_logic; -- Full Flag --- EMPTY_OUT : out std_logic; --- DEPTH_OUT : out std_logic_vector(7 downto 0) --- ); --- end entity; +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); +end entity; architecture arch_trb_net16_fifo of trb_net16_fifo is component xilinx_fifo_18x1k diff --git a/xilinx/virtex4/xilinx_fifo_dualport_18x1k_4.xco b/xilinx/virtex4/xilinx_fifo_dualport_18x1k_4.xco new file mode 100644 index 0000000..00cfc29 --- /dev/null +++ b/xilinx/virtex4/xilinx_fifo_dualport_18x1k_4.xco @@ -0,0 +1,64 @@ +# BEGIN Project Options +SET flowvendor = Foundation_iSE +SET vhdlsim = True +SET verilogsim = True +SET workingdirectory = . +SET speedgrade = -10 +SET simulationfiles = Behavioral +SET asysymbol = True +SET addpads = False +SET device = xc4vlx40 +SET implementationfiletype = Edif +SET busformat = BusFormatAngleBracketNotRipped +SET foundationsym = False +SET package = ff1148 +SET createndf = False +SET designentry = VHDL +SET devicefamily = virtex4 +SET formalverification = False +SET removerpms = False +# END Project Options +# BEGIN Select +SELECT Fifo_Generator family Xilinx,_Inc. 2.1 +# END Select +# BEGIN Parameters +CSET almost_empty_flag=false +CSET write_data_count=false +CSET full_threshold_negate_value=768 +CSET empty_threshold_negate_value=256 +CSET output_data_width=18 +CSET input_depth=1024 +CSET valid_flag=true +CSET empty_threshold_negate_presets=3/4_Empty +CSET write_acknowledge_flag=false +CSET programmable_empty_type=Single_Programmable_Empty_Threshold_Constant +CSET full_threshold_negate_presets=3/4_Full +CSET fifo_implementation=Independent_Clocks_Block_RAM +CSET underflow_flag=true +CSET use_extra_logic=false +CSET register_outputs=false +CSET valid_sense=Active_High +CSET write_data_count_width=2 +CSET data_count_width=2 +CSET output_depth=1024 +CSET dout_reset_value=0 +CSET underflow_sense=Active_High +CSET component_name=xilinx_fifo_dualport_18x1k_4 +CSET overflow_sense=Active_High +CSET overflow_flag=false +CSET read_data_count=false +CSET data_count=false +CSET primitive_depth=1024 +CSET programmable_full_type=No_Programmable_Full_Threshold +CSET read_data_count_width=2 +CSET read_latency=1 +CSET empty_threshold_assert_presets=3/4_Empty +CSET full_threshold_assert_value=768 +CSET almost_full_flag=true +CSET full_threshold_assert_presets=3/4_Full +CSET write_acknowledge_sense=Active_High +CSET empty_threshold_assert_value=3 +CSET input_data_width=18 +# END Parameters +GENERATE + -- 2.43.0