From 24d890b882d13808eee9be0bfc6c5de251489071 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 10 Jan 2008 09:44:39 +0000 Subject: [PATCH] updated tlk_med, Jan --- trb_net16_med_tlk.vhd | 142 ++++++++++++++++++++++++++++++++++-------- 1 file changed, 117 insertions(+), 25 deletions(-) diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index 5454459..c23d176 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -57,32 +57,44 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is end component trb_net_fifo_16bit_bram_dualport; - signal fifo_din_a : std_logic_vector(17 downto 0); - signal fifo_dout_a : std_logic_vector(17 downto 0); + signal fifo_din_a : std_logic_vector(17 downto 0); + signal fifo_dout_a : std_logic_vector(17 downto 0); signal fifo_wr_en_a : std_logic; signal fifo_rd_en_a : std_logic; signal fifo_empty_a : std_logic; - signal fifo_full_a : std_logic; - signal fifo_din_m : std_logic_vector(17 downto 0); - signal fifo_dout_m : std_logic_vector(17 downto 0); + signal fifo_full_a : std_logic; + signal fifo_din_m : std_logic_vector(17 downto 0); + signal fifo_dout_m : std_logic_vector(17 downto 0); signal fifo_rd_en_m : std_logic; + signal fifo_wr_en_m : std_logic; signal fifo_empty_m : std_logic; - signal fifo_full_m : std_logic; + signal fifo_full_m : std_logic; - signal fifo_reset : std_logic; + signal fifo_reset : std_logic; signal fifo_status_a : std_logic_vector(3 downto 0); signal fifo_status_m : std_logic_vector(3 downto 0); signal last_fifo_rd_en_a, last_fifo_rd_en_m : std_logic; signal buf_MED_PACKET_NUM_OUT : std_logic_vector(1 downto 0); + signal buf_MED_READ_OUT : std_logic; + signal rx_locked : std_logic; + signal tx_allow : std_logic; + signal rx_lock_counter : std_logic_vector(20 downto 0); + signal internal_reset : std_logic; + signal reset_counter : std_logic_vector(16 downto 0); + + signal reg_RXD : std_logic_vector(15 downto 0); + signal reg_RX_DV : std_logic; + signal reg_RX_ER : std_logic; + begin - STAT(3 downto 0) <= fifo_status_a; - STAT(5 downto 4) <= fifo_empty_a & fifo_full_a; - STAT(7 downto 6) <= (others => '0'); - STAT(11 downto 8) <= fifo_status_m; - STAT(13 downto 12) <= fifo_empty_m & fifo_full_m; - STAT(31 downto 14) <= (others => '0'); +-- STAT(3 downto 0) <= fifo_status_a; +-- STAT(5 downto 4) <= fifo_empty_a & fifo_full_a; +-- STAT(7 downto 6) <= (others => '0'); +-- STAT(11 downto 8) <= fifo_status_m; +-- STAT(13 downto 12) <= fifo_empty_m & fifo_full_m; +-- STAT(31 downto 14) <= (others => '0'); TLK_TX_ER <= '0'; TLK_ENABLE <= not RESET; @@ -90,8 +102,9 @@ begin TLK_PRBSEN <= '0'; TLK_LOOPEN <= '0'; SFP_TX_DIS <= RESET; - - MED_READ_OUT <= not RESET; + + buf_MED_READ_OUT <= tx_allow; + MED_READ_OUT <= buf_MED_READ_OUT; ------------- --Receiver @@ -111,19 +124,44 @@ begin fifostatus_out => fifo_status_a ); - fifo_wr_en_a <= TLK_RX_DV and not TLK_RX_ER; - fifo_din_a <= '0' & TLK_RX_ER & TLK_RXD; + fifo_wr_en_a <= reg_RX_DV and not reg_RX_ER and rx_locked; + fifo_din_a <= rx_locked & reg_RX_ER & reg_RXD; fifo_rd_en_a <= not fifo_empty_a; - fifo_reset <= RESET; + fifo_reset <= internal_reset; MED_DATA_OUT <= fifo_dout_a(15 downto 0); - MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16); - MED_ERROR_OUT <= ERROR_OK when TLK_RX_ER = '0' else ERROR_NC; + MED_DATAREADY_OUT <= last_fifo_rd_en_a and not fifo_dout_a(16) and fifo_dout_a(17); + MED_ERROR_OUT <= ERROR_OK when rx_locked = '1' else ERROR_NC; MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; + + STAT(0) <= internal_reset; + STAT(1) <= rx_locked; + STAT(2) <= tx_allow; + STAT(3) <= fifo_wr_en_a; + STAT(4) <= fifo_rd_en_a; + STAT(5) <= fifo_empty_a; + STAT(6) <= fifo_rd_en_m; + STAT(7) <= fifo_empty_m; + process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if internal_reset = '1' then + reg_RXD <= (others => '0'); + reg_RX_DV <= '0'; + reg_RX_ER <= '0'; + else + reg_RXD <= TLK_RXD; + reg_RX_DV <= TLK_RX_DV; + reg_RX_ER <= TLK_RX_ER; + end if; + end if; + end process; + + process(CLK) + begin + if rising_edge(CLK) then + if internal_reset = '1' then buf_MED_PACKET_NUM_OUT <= "11"; elsif fifo_rd_en_a = '1' then buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; @@ -134,7 +172,7 @@ begin process(CLK) begin if rising_edge(CLK) then - if RESET = '1' then + if internal_reset = '1' then last_fifo_rd_en_a <= '0'; else last_fifo_rd_en_a <= fifo_rd_en_a; @@ -152,7 +190,7 @@ begin read_clock_in => TLK_CLK, write_clock_in => CLK, read_enable_in => fifo_rd_en_m, - write_enable_in => MED_DATAREADY_IN, + write_enable_in => fifo_wr_en_m, fifo_gsr_in => fifo_reset, write_data_in => fifo_din_m, read_data_out => fifo_dout_m, @@ -161,7 +199,8 @@ begin fifostatus_out => fifo_status_m ); - fifo_rd_en_m <= not TLK_RX_ER and not fifo_empty_m; + fifo_rd_en_m <= tx_allow and not fifo_empty_m; + fifo_wr_en_m <= MED_DATAREADY_IN and buf_MED_READ_OUT; fifo_din_m <= "00" & MED_DATA_IN; TLK_TXD <= fifo_dout_m(15 downto 0); TLK_TX_EN <= last_fifo_rd_en_m; @@ -169,7 +208,7 @@ begin process(TLK_CLK) begin if rising_edge(TLK_CLK) then - if RESET = '1' then + if internal_reset = '1' then last_fifo_rd_en_m <= '0'; else last_fifo_rd_en_m <= fifo_rd_en_m; @@ -177,4 +216,57 @@ begin end if; end process; + +--count time the receiver is locked + RESET_FIFO_COUNTER_PROC: process (TLK_RX_CLK) + begin + if rising_edge(TLK_RX_CLK) then + if internal_reset = '1' or TLK_RX_ER = '1' then + rx_lock_counter <= (others => '0'); + elsif rx_lock_counter(20) = '0' then + rx_lock_counter <= rx_lock_counter + 1; + end if; + end if; + end process RESET_FIFO_COUNTER_PROC; + + +--wait 2.5us to see if receiver is really locked + process (TLK_RX_CLK) + begin + if rising_edge(TLK_RX_CLK) then + if internal_reset = '1' or TLK_RX_ER = '1' then + rx_locked <= '0'; + elsif rx_lock_counter(8) = '1' then + rx_locked <= '1'; + end if; + end if; + end process; + +--wait 2800us to enable transmitter after receiver is locked + process (TLK_RX_CLK) + begin + if rising_edge(TLK_RX_CLK) then + if internal_reset = '1' or TLK_RX_ER = '1' then + tx_allow <= '0'; + elsif rx_lock_counter(10) = '1' then + tx_allow <= '1'; + end if; + end if; + end process; + + +--internal reset is hold for approx. 650 us + internal_reset_counter: process (CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + reset_counter <= (others => '0'); + elsif reset_counter(16) = '0' then + reset_counter <= reset_counter + 1; + end if; + end if; + end process internal_reset_counter; + +internal_reset <= not reset_counter(16); + end architecture; -- 2.43.0