From 24da33cdff9d312381c8e5b24259c3e850609b10 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Sat, 13 Jun 2015 18:11:46 +0200 Subject: [PATCH] CTS: Make Mainz A2 receiver module work again (hopefully) --- cts/source/mainz_a2_recv.vhd | 3 ++- cts/trb3_central.vhd | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/cts/source/mainz_a2_recv.vhd b/cts/source/mainz_a2_recv.vhd index c6a923a..22ff00a 100644 --- a/cts/source/mainz_a2_recv.vhd +++ b/cts/source/mainz_a2_recv.vhd @@ -19,6 +19,7 @@ entity mainz_a2_recv is -- the external trigger id is sent on SERIAL_IN TRG_SYNC_OUT : out std_logic; -- sync. to CLK + TRG_ASYNC_OUT : out std_logic; -- Asynchronous for TDC --data output for read-out TRIGGER_IN : in std_logic; @@ -73,7 +74,6 @@ architecture arch1 of mainz_a2_recv is signal timeout_seen : std_logic := '0'; - signal trg_async : std_logic; signal trg_sync : std_logic; signal trg_sync_old : std_logic; @@ -93,6 +93,7 @@ begin timer_tick_1us <= TIMER_TICK_1US_IN; TRG_SYNC_OUT <= trg_sync; + TRG_ASYNC_OUT <= EXT_TRG_IN; trg_sync <= EXT_TRG_IN when rising_edge(CLK); trg_sync_old <= trg_sync when rising_edge(CLK); reg_SERIAL_IN <= SERIAL_IN when rising_edge(CLK); diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index a6bfcd2..dad6427 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -617,6 +617,7 @@ begin TIMER_TICK_1US_IN => timer_ticks(0), SERIAL_IN => CLK_EXT(3), EXT_TRG_IN => CLK_EXT(4), + TRG_ASYNC_OUT => tdc_inputs(1), TRG_SYNC_OUT => cts_ext_trigger, TRIGGER_IN => cts_rdo_trg_data_valid, -- 2.43.0