From 2560535bb3f80d31f8a4586de924ca85f16d52c9 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 23 Nov 2018 16:57:13 +0100 Subject: [PATCH] remove unnecessary logic from trigger handler --- releases/tdc_v2.3/TriggerHandler.vhd | 51 +++++----------------------- 1 file changed, 8 insertions(+), 43 deletions(-) diff --git a/releases/tdc_v2.3/TriggerHandler.vhd b/releases/tdc_v2.3/TriggerHandler.vhd index 0eaf56d..06ff076 100644 --- a/releases/tdc_v2.3/TriggerHandler.vhd +++ b/releases/tdc_v2.3/TriggerHandler.vhd @@ -94,31 +94,8 @@ begin -- architecture behavioral trg_in_2r <= trg_in_r when rising_edge(CLK_TDC); trg_in_3r <= trg_in_2r when rising_edge(CLK_TDC); --- GEN_TRIGGER : for i in 0 to TRIGGER_NUM-1 generate --- Validation : process (CLK_TDC) --- begin --- if rising_edge(CLK_TDC) then --- --- -- calculate trigger length --- if trg_in_3r(i) = '0' then --- trg_length(i) <= (others => '0'); --- else --- trg_length(i) <= trg_length(i) + to_unsigned(1, 5); --- end if; --- --- -- accept trigger if it is longer than 100 ns --- if RESET_TDC = '1' then --- trg_pulse_tdc(i) <= '0'; --- elsif trg_length(i) = to_unsigned(15, 5) then --- trg_pulse_tdc(i) <= '1'; --- else --- trg_pulse_tdc(i) <= '0'; --- end if; --- --- end if; --- end process Validation; --- end generate GEN_TRIGGER; -trg_pulse_tdc(0) <= valid_timing_200; + + trg_pulse_tdc(0) <= valid_timing_200; -- sync the strobes to the readout clock domain @@ -136,19 +113,6 @@ trg_pulse_tdc(0) <= valid_timing_200; TRG_RDO_OUT <= trg_pulse_rdo when rising_edge(CLK_RDO); TRG_TDC_OUT <= trg_pulse_tdc when rising_edge(CLK_TDC); --- ValidateTrigger : process (CLK_TDC) is --- begin --- if rising_edge(CLK_TDC) then -- rising clock edge --- if RESET_TDC = '1' then --- valid_trigger_flag <= '0'; --- elsif valid_timing_200 = '1' then --- valid_trigger_flag <= '1'; --- elsif trg_release_200 = '1' then --- valid_trigger_flag <= '0'; --- end if; --- end if; --- end process ValidateTrigger; - TriggerReleaseSync : entity work.pulse_sync port map ( CLK_A_IN => CLK_RDO, @@ -195,14 +159,15 @@ trg_pulse_tdc(0) <= valid_timing_200; begin -- Outputs to be registered if rising_edge(CLK_TDC) then -- rising clock edge + STATE_TW_CURRENT <= STATE_TW_NEXT; + trg_win_cnt <= trg_win_cnt_f; + trg_win_end_tdc <= trg_win_end_f; + missing_ref_time_tdc <= missing_ref_time_f; + if RESET_TDC = '1' then STATE_TW_CURRENT <= IDLE; - else - STATE_TW_CURRENT <= STATE_TW_NEXT; - trg_win_cnt <= trg_win_cnt_f; - trg_win_end_tdc <= trg_win_end_f; - missing_ref_time_tdc <= missing_ref_time_f; end if; + end if; -- Outputs not to be registered end process FSM_TRIGGER_WINDOW_SEQUENTIAL; -- 2.43.0