From 257a747310cf9b7ec6deb5196450d1c507b88533 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 11 Oct 2021 20:03:23 +0200 Subject: [PATCH] update 32 pin addon --- 32PinAddOn/config.vhd | 4 +-- 32PinAddOn/config_compile_frankfurt.pl | 4 +-- 32PinAddOn/trb3_periph_32PinAddOn.prj | 49 +++++++++++--------------- 3 files changed, 25 insertions(+), 32 deletions(-) diff --git a/32PinAddOn/config.vhd b/32PinAddOn/config.vhd index 40e50bc..93012f8 100644 --- a/32PinAddOn/config.vhd +++ b/32PinAddOn/config.vhd @@ -12,7 +12,7 @@ package config is --TDC settings constant FPGA_TYPE : integer := 3; --3: ECP3, 5: ECP5 constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, @@ -29,7 +29,7 @@ package config is -- 14: Debug - single fine time and the ROM addresses for the two transitions -- 15: Debug - complete carry chain dump - constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 11; -- size of the event buffer, 2**N + constant EVENT_BUFFER_SIZE : integer range 9 to 13 := 13; -- size of the event buffer, 2**N constant EVENT_MAX_SIZE : integer := 1024; --maximum event size. Should not exceed EVENT_BUFFER_SIZE/2 constant INCLUDE_UART : integer := c_NO; diff --git a/32PinAddOn/config_compile_frankfurt.pl b/32PinAddOn/config_compile_frankfurt.pl index d4460fe..5306aff 100644 --- a/32PinAddOn/config_compile_frankfurt.pl +++ b/32PinAddOn/config_compile_frankfurt.pl @@ -2,8 +2,8 @@ TOPNAME => "trb3_periph_32PinAddOn", project_path => "32PinAddOn", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@hadeb05", -lattice_path => '/d/jspc29/lattice/diamond/3.7_x64', -synplify_path => '/d/jspc29/lattice/synplify/K-2015.09/', +lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1/', # synplify_command => "/d/jspc29/lattice/diamond/3.6_x64/bin/lin64/synpwrap -fg -options", # synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", diff --git a/32PinAddOn/trb3_periph_32PinAddOn.prj b/32PinAddOn/trb3_periph_32PinAddOn.prj index 79cb1db..0136814 100644 --- a/32PinAddOn/trb3_periph_32PinAddOn.prj +++ b/32PinAddOn/trb3_periph_32PinAddOn.prj @@ -52,8 +52,7 @@ impl -active "workdir" -#add_file options - +#project files add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" @@ -82,23 +81,22 @@ add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" -add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_gbe.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" -add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" @@ -109,22 +107,22 @@ add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" -#add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload.vhd" add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" - +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" @@ -137,30 +135,27 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" -add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_200_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" -add_file -vhdl -lib work "../../trb3/base/code/trb3_tools.vhd" -add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" -add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" -add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" -add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" -add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" -add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" -add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" -add_file -vhdl -lib work "../base/code/input_to_trigger_logic.vhd" add_file -vhdl -lib work "../base/code/input_to_trigger_logic_record.vhd" add_file -vhdl -lib work "../base/code/input_statistics.vhd" add_file -vhdl -lib work "../base/code/sedcheck.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../base/code/trb3_tools.vhd" add_file -vhdl -lib work "tdc_release/tdc_components.vhd" @@ -169,12 +164,10 @@ add_file -vhdl -lib work "tdc_release/BusHandler_record.vhd" add_file -vhdl -lib work "tdc_release/Channel.vhd" add_file -vhdl -lib work "tdc_release/Channel_200.vhd" add_file -vhdl -lib work "tdc_release/Encoder_288_Bit.vhd" -add_file -vhdl -lib work "tdc_release/Encoder_304_Bit.vhd" add_file -vhdl -lib work "tdc_release/fallingEdgeDetect.vhd" add_file -vhdl -lib work "tdc_release/hit_mux.vhd" add_file -vhdl -lib work "tdc_release/LogicAnalyser.vhd" add_file -vhdl -lib work "tdc_release/risingEdgeDetect.vhd" -#add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp5.vhd" add_file -vhdl -lib work "tdc_release/ROM_encoder_ecp3.vhd" add_file -vhdl -lib work "tdc_release/ShiftRegisterSISO.vhd" add_file -vhdl -lib work "tdc_release/Stretcher_A.vhd" -- 2.43.0