From 25968c24a0b5a6bfec12cd5ecacb69fc9a43d5ee Mon Sep 17 00:00:00 2001
From: hadeshyp <hadeshyp>
Date: Mon, 24 Aug 2009 14:42:22 +0000
Subject: [PATCH] added reset via media interface

---
 mdc_oepb.vhd | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/mdc_oepb.vhd b/mdc_oepb.vhd
index b6c5bc6..3cd5187 100644
--- a/mdc_oepb.vhd
+++ b/mdc_oepb.vhd
@@ -180,7 +180,7 @@ architecture mdc_oepb_arch of mdc_oepb is
   signal write_ctrl_register : std_logic;
 
   signal reset_mdc_addon_daq_bus_0, pulse_reset_internal_logic : std_logic;
-  
+
 begin
 ---------------------------------------------------------------------
 -- PLL: 100 MHz
@@ -199,7 +199,7 @@ begin
   THE_RESET_COUNTER_PROC: process(CLK)
     begin
       if rising_edge(CLK) then
-        if pll_locked = '0' then
+        if MED_STAT_OP(13) = '1' or pll_locked = '0' then
           reset_counter  <= x"000F00";
           reset_internal <= '1';
           reset_startup  <= '1';
@@ -443,12 +443,12 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
     BUS_WRITE_ENABLE_OUT(2)           => flash_mem_write,
     BUS_DATA_OUT(2*32+31 downto 2*32) => flash_mem_data,
     BUS_ADDR_OUT(2*16+8 downto 2*16)  => flash_mem_addr,
-    BUS_TIMEOUT_OUT(2)                => open, 
+    BUS_TIMEOUT_OUT(2)                => open,
     BUS_DATA_IN(2*32+31 downto 2*32)  => flash_mem_data_out,
     BUS_DATAREADY_IN(2)               => very_last_reg_REGIO_READ,
     BUS_WRITE_ACK_IN(2)               => reg_REGIO_WRITE,
     BUS_NO_MORE_DATA_IN(2)            => '0',
-    BUS_UNKNOWN_ADDR_IN(2)            => '0',    
+    BUS_UNKNOWN_ADDR_IN(2)            => '0',
    --Debugging
     STAT_DEBUG                 => open
     );
@@ -464,7 +464,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
         if (flash_mem_addr(3 downto 0) = x"0") then
           write_cmd_register_in <= flash_mem_write;
           flash_mem_data_out <= cmd_register_in;
-          
+
         elsif (flash_mem_addr(3 downto 0) = x"1") then
           write_ctrl_register      <= flash_mem_write;
            flash_mem_data_out <= ctrl_register;
@@ -495,7 +495,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
           ctrl_register      <= ctrl_register;
         end if;
       end if;
-    end process;  
+    end process;
 ---------------------------------------------------------------------
 -- ADC
 ---------------------------------------------------------------------
@@ -569,7 +569,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
 -- 0xc0 0x1000 -> select compact mode data
 -- 0xc0 0x2000 -> select test data
 -- 0xc0 0xABCD2000 -> x"ABCD" test data number
-    
+
   PROC_GEN_TIMING : process(CLK_100)
     begin
       if rising_edge(CLK_100) then
@@ -594,7 +594,7 @@ THE_REGIO_BUS_HANDLER : trb_net16_regio_bus_handler
         PULSE_OUT     => pulse_reset_internal_logic);
 
  reset_mdc_addon_daq_bus_0  <= reset_internal or pulse_reset_internal_logic;
-    
+
     PULSE_BEGRUN_TRIGGER : edge_to_pulse
        port map (
          CLOCK         => CLK_100,
-- 
2.43.0