From 2610fca36fdbddd1bf63d929f79e1c58e11a23d7 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 12 Jan 2012 14:33:31 +0000 Subject: [PATCH] *** empty log message *** --- testbenches/hub_tb.vhd | 4 +- trb_net16_hub_base.vhd | 12 +- trb_net16_hub_logic_2.vhd | 527 ++++++++++++++++++++++++++++++++++++++ trb_net16_ibuf.vhd | 2 +- trb_net_components.vhd | 2 +- trb_net_sbuf.vhd | 2 + 6 files changed, 541 insertions(+), 8 deletions(-) create mode 100644 trb_net16_hub_logic_2.vhd diff --git a/testbenches/hub_tb.vhd b/testbenches/hub_tb.vhd index 65a1764..23391c7 100644 --- a/testbenches/hub_tb.vhd +++ b/testbenches/hub_tb.vhd @@ -384,7 +384,7 @@ begin apl_send_i(3) <= '1'; wait until rising_edge(CLK); wait for 1 ns; apl_send_i(3) <= '0'; - wait for 10 us; + wait for 5 us; end process; @@ -413,7 +413,7 @@ begin APL_DTYPE_IN => x"8000", APL_ERROR_PATTERN_IN => (others => '0'), APL_SEND_IN => apl_send_i, - APL_TARGET_ADDRESS_IN => (others => '1'), + APL_TARGET_ADDRESS_IN => (others => '1'), --x"f001f001f001f001", APL_DATA_OUT => open, APL_PACKET_NUM_OUT => open, APL_TYP_OUT => open, diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index 2039729..65e5705 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -569,7 +569,7 @@ MED_DATA_OUT <= buf_MED_DATA_OUT; IOBUF_CTRL_GEN((i+1)*32-1 downto i*32) <= (others => '0'); iobuf_stat_init_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0'); iobuf_stat_reply_obuf_debug_i((i+1)*32-1 downto i*32) <= (others => '0'); - + IOBUF_STAT_DATA_COUNTER((i+1)*32-1 downto i*32) <= (others => '0'); m_DATAREADY_OUT(i*2) <= '0'; m_DATA_OUT((i*2+1)*c_DATA_WIDTH-1 downto i*2*c_DATA_WIDTH) <= (others => '0'); @@ -953,6 +953,7 @@ end generate; HUB_REPLY_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0'); HUB_REPLY_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0'); HUB_REPLY_READ_IN(next_point_num-1 downto first_point_num) <= (others => '0'); + HUB_REPLY_READ_OUT(next_point_num-1 downto first_point_num) <= (others => '0'); HUB_INIT_PACKET_NUM_OUT(next_point_num*c_NUM_WIDTH-1 downto first_point_num*c_NUM_WIDTH) <= (others => '0'); HUB_INIT_DATA_OUT(next_point_num*c_DATA_WIDTH-1 downto first_point_num*c_DATA_WIDTH) <= (others => '0'); HUB_INIT_DATAREADY_OUT(next_point_num-1 downto first_point_num) <= (others => '0'); @@ -1254,7 +1255,7 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); --Usual common stat reg, trigger counters are not in use here HC_COMMON_STAT_REGS(19 downto 0) <= COMMON_STAT_REGS(19 downto 0); HC_COMMON_STAT_REGS(31 downto 20) <= TEMP_OUT; - HC_COMMON_STAT_REGS(255 downto 32) <= COMMON_STAT_REGS(255 downto 32); + HC_COMMON_STAT_REGS(287 downto 32) <= COMMON_STAT_REGS(287 downto 32); --Status Registers buf_HC_STAT_REGS(3*32+31 downto 0) <= buf_STAT_POINTS_locked; @@ -1462,8 +1463,11 @@ HUB_MED_CONNECTED(31 downto MII_NUMBER) <= (others => '1'); end if; end process; end generate; --- received_retransmit_requests(15 downto MII_NUMBER) <= (others => '0'); --- sent_retransmit_requests(15 downto MII_NUMBER) <= (others => '0'); + + gen_0s : for i in MII_NUMBER to 15 generate + received_retransmit_requests(i) <= (others => '0'); + sent_retransmit_requests(i) <= (others => '0'); + end generate; ------------------------------------ --STAT busy counters diff --git a/trb_net16_hub_logic_2.vhd b/trb_net16_hub_logic_2.vhd new file mode 100644 index 0000000..736a8a4 --- /dev/null +++ b/trb_net16_hub_logic_2.vhd @@ -0,0 +1,527 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; + +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb_net16_hub_func.all; + +entity trb_net16_hub_logic is + generic ( + --media interfaces + POINT_NUMBER : integer range 2 to 32 := 17; + MII_IS_UPLINK_ONLY : hub_mii_config_t := (others => c_NO) + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + --Internal interfaccs to IOBufs + INIT_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + INIT_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0) := (others => '0'); + INIT_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0) := (others => '0'); + INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0'); + INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0'); + INIT_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATAREADY_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0); + REPLY_READ_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0) := (others => '0'); + REPLY_DATAREADY_OUT : out std_logic_vector (POINT_NUMBER-1 downto 0) := (others => '0'); + REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0'); + REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH*POINT_NUMBER-1 downto 0) := (others => '0'); + REPLY_READ_IN : in std_logic_vector (POINT_NUMBER-1 downto 0); + --Status ports (for debugging) + STAT : out std_logic_vector (15 downto 0); + STAT_locked : out std_logic; + STAT_POINTS_locked : out std_logic_vector (31 downto 0); + STAT_TIMEOUT : out std_logic_vector (31 downto 0); + STAT_ERRORBITS : out std_logic_vector (31 downto 0); + STAT_ALL_ERRORBITS : out std_logic_vector (16*32-1 downto 0); + CTRL_TIMEOUT_TIME : in std_logic_vector (15 downto 0); + CTRL_activepoints : in std_logic_vector (31 downto 0) := (others => '1'); + CTRL_TIMER_TICK : in std_logic_vector (1 downto 0) + ); +end entity; + +architecture trb_net16_hub_logic_arch of trb_net16_hub_logic is + + attribute HGROUP : string; + attribute syn_keep : boolean; + + attribute HGROUP of trb_net16_hub_logic_arch : architecture is "HUBLOGIC_group"; + + signal config_wait_free_init_pool : unsigned(31 downto 0) := x"00010000"; --65ms + signal config_wait_reply : unsigned(31 downto 0) := x"00000400"; -- 1ms + + signal reset_i : std_logic; + signal timer_ms_tick : std_logic; + signal timer_us_tick : std_logic; + signal timer_us_reset : std_logic; + + type fsm_t is (IDLE, SELECT_INIT, FORWARD_INIT, SELECT_REPLY, WAIT_FOR_SELECT, FORWARD_REPLY, REPLY_TIMEOUT, + SEND_TRM, FINISHED); + signal currentstate : fsm_t; + + signal reply_dataready_in_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal reply_data_in_i : std_logic_vector(16*POINT_NUMBER-1 downto 0) := (others => '0'); + signal reply_packet_num_in_i : std_logic_vector(3*POINT_NUMBER-1 downto 0) := (others => '0'); + signal reply_read_out_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + + signal reply_reading_trm : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal reply_got_trm : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal TRM_packet : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + + signal init_select_enable : std_logic; + signal reply_select_enable : std_logic; + signal reply_select_input : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal act_init_port : integer range 0 to POINT_NUMBER-1; + signal act_reply_port : integer range 0 to POINT_NUMBER-1; + signal act_init_mask : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal act_reply_mask : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + +--Init Pool + signal init_pool_reading : std_logic; + signal init_pool_free : std_logic; + signal init_pool_dataready_in : std_logic; + signal init_pool_data_in : std_logic_vector(15 downto 0) := (others => '0'); + signal init_pool_packet_num_in : std_logic_vector(2 downto 0) := (others => '0'); + signal init_selected_dataready : std_logic; + signal init_selected_data : std_logic_vector(15 downto 0) := (others => '0'); + signal init_selected_packet_num : std_logic_vector(2 downto 0) := (others => '0'); + signal init_current_type : std_logic_vector(2 downto 0) := (others => '0'); + signal init_pool_data_out : std_logic_vector(15 downto 0) := (others => '0'); + signal init_pool_packet_num_out : std_logic_vector(2 downto 0) := (others => '0'); + signal init_pool_read_out : std_logic; + signal init_pool_dataready_out : std_logic; + signal init_read_out_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal init_has_read_from_pool : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + + +--Reply Pool + signal reply_selected_dataready : std_logic; + signal reply_selected_data : std_logic_vector(15 downto 0) := (others => '0'); + signal reply_selected_packet_num : std_logic_vector(2 downto 0) := (others => '0'); + signal reply_pool_reading : std_logic; + signal reply_pool_free : std_logic; + signal reply_pool_dataready_in : std_logic; + signal reply_pool_data_in : std_logic_vector(15 downto 0) := (others => '0'); + signal reply_pool_packet_num_in : std_logic_vector(2 downto 0) := (others => '0'); + signal reply_pool_data_out : std_logic_vector(15 downto 0) := (others => '0'); + signal reply_pool_packet_num_out : std_logic_vector(2 downto 0) := (others => '0'); + signal reply_pool_read_out : std_logic; + signal reply_pool_dataready_out : std_logic; + +--Control Signals + signal real_active_points : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal timer_us : unsigned(31 downto 0) := (others => '0'); + signal timeout_found : std_logic := '0'; + +--Reply Pool output + signal reply_mux_read_out_i : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal reply_open : std_logic; + + signal reading_trmF1 : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal reading_trmF2 : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal reading_trmF3 : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + signal REPLY_combined_trm_F1 : std_logic_vector(15 downto 0); + signal REPLY_combined_trm_F2 : std_logic_vector(15 downto 0); + signal REPLY_combined_trm_F3 : std_logic_vector(15 downto 0); + signal send_trm_cnt : integer; + + + signal timeout_ports : std_logic_vector(POINT_NUMBER-1 downto 0) := (others => '0'); + attribute syn_keep of reset_i : signal is true; + +begin + +---------------------------------- +--Sync input Signals +---------------------------------- + + reset_i <= RESET when rising_edge(CLK); + timer_us_tick <= CTRL_TIMER_TICK(0) when rising_edge(CLK); + timer_ms_tick <= CTRL_TIMER_TICK(1) when rising_edge(CLK); + + + PROC_TIMER : process begin wait until rising_edge(CLK); + if timer_us_reset = '1' then + timer_us <= (others => '0'); + elsif timer_us_tick = '1' then + timer_us <= timer_us + 1; + end if; + end process; + + config_wait_free_init_pool <= x"00" & unsigned(CTRL_TIMEOUT_TIME) & x"00"; --mult. by 256/1024, e.q. 1/4 of given value + config_wait_reply <= x"00" & "00" & unsigned(CTRL_TIMEOUT_TIME) & "000000"; --mult. by 64/1024, e.q. 1/16 of given value + + +---------------------------------- +--connect init input signals +---------------------------------- + + --choose from all init dataready the selected one + init_selected_dataready <= INIT_DATAREADY_IN(act_init_port); + init_selected_data <= INIT_DATA_IN(16*act_init_port+15 downto 16*act_init_port); + init_selected_packet_num <= INIT_PACKET_NUM_IN(3*act_init_port+2 downto 3*act_init_port); + + --only reading from active init port if pool reads + INIT_READ_OUT <= act_init_mask when init_pool_free = '1' and currentstate = FORWARD_INIT else (others => '0'); + + THE_INIT_SELECT : priority_arbiter + generic map( + INPUT_WIDTH => POINT_NUMBER + ) + port map( + CLK => CLK, + ENABLE => init_select_enable, + INPUT => INIT_DATAREADY_IN, + OUTPUT_VEC => act_init_mask, + OUTPUT_NUM => act_init_port + ); + + + reply_select_input <= REPLY_DATAREADY_IN and not reply_reading_trm and not TRM_packet; + + THE_REPLY_SELECT : priority_arbiter + generic map( + INPUT_WIDTH => POINT_NUMBER + ) + port map( + CLK => CLK, + ENABLE => reply_select_enable, + INPUT => reply_select_input, + OUTPUT_VEC => act_reply_mask, + OUTPUT_NUM => act_reply_port + ); + +---------------------------------- +--connect reply signals +---------------------------------- + + --choose from all reply data the selected one + reply_selected_dataready <= REPLY_DATAREADY_IN(act_reply_port); + reply_selected_data <= REPLY_DATA_IN(16*act_reply_port+15 downto 16*act_reply_port); + reply_selected_packet_num <= REPLY_PACKET_NUM_IN(3*act_reply_port+2 downto 3*act_reply_port); + + -- Reply read out + -- as long as there is no data available or if mux really reads or if reading TRM + reply_read_out_i <= reply_mux_read_out_i or reply_reading_trm; --not reply_dataready_in_i or + REPLY_READ_OUT <= reply_read_out_i; + + + gen_reply_con : for i in 0 to POINT_NUMBER-1 generate + reply_dataready_in_i(i) <= REPLY_DATAREADY_IN(i); + reply_data_in_i(i*16+15 downto i*16) <= REPLY_DATA_IN(i*16+15 downto i*16); + reply_packet_num_in_i(i*3+2 downto i*3) <= REPLY_PACKET_NUM_IN(i*3+2 downto i*3); + + TRM_packet(i) <= '1' when REPLY_DATA_IN(i*16+2 downto i*16) = TYPE_TRM and REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_H0 else '0'; + end generate; + + +---------------------------------- +--combine error pattern +---------------------------------- + + reply_reading_trm <= reply_reading_trm or TRM_packet when currentstate /= IDLE else (others => '0'); + reply_got_trm <= reply_got_trm or reading_trmF3 when currentstate /= IDLE else (others => '0'); + + gen_reading_trmFn : for i in 0 to POINT_NUMBER-1 generate + reading_trmF1(i) <= '1' when REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_F1 + and reply_reading_trm(i) = '1' and REPLY_DATAREADY_IN(i) = '1' else '0'; + reading_trmF2(i) <= '1' when REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_F2 + and reply_reading_trm(i) = '1' and REPLY_DATAREADY_IN(i) = '1' else '0'; + reading_trmF3(i) <= '1' when REPLY_PACKET_NUM_IN(i*3+2 downto i*3) = c_F3 + and reply_reading_trm(i) = '1' and REPLY_DATAREADY_IN(i) = '1' else '0'; + end generate; + + gen_combining_trm : for j in 0 to c_DATA_WIDTH-1 generate + process(CLK) + variable tmpF1, tmpF2, tmpF3 : std_logic; + begin + if rising_edge(CLK) then + if reset_i = '1' or currentstate = SELECT_INIT then + reply_combined_trm_f1(j) <= '0'; + reply_combined_trm_f2(j) <= '0'; + reply_combined_trm_f3(j) <= '0'; + else + tmpF1 := '0'; + tmpF2 := '0'; + tmpF3 := '0'; + for i in 0 to POINT_NUMBER-1 loop + tmpF1 := tmpF1 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF1(i)); + tmpF2 := tmpF2 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF2(i)); + tmpF3 := tmpF3 or (REPLY_DATA_IN(i*c_DATA_WIDTH+j) and reading_trmF3(i)); + end loop; + reply_combined_trm_f1(j) <= reply_combined_trm_f1(j) or tmpF1; + if j = 6 then + reply_combined_trm_f2(j) <= reply_combined_trm_f2(j) or tmpF2 or timeout_found; + else + reply_combined_trm_f2(j) <= reply_combined_trm_f2(j) or tmpF2; + end if; + reply_combined_trm_f3(j) <= reply_combined_trm_f3(j) or tmpF3; + end if; + end if; + end process; + end generate; + + timeout_found <= or_all(timeout_ports); + +---------------------------------- +--Controller +---------------------------------- + FSM : process begin + wait until rising_edge(CLK); +-- reply_mux_read_out_i <= (others => '0'); + reply_select_enable <= '0'; + init_pool_dataready_in <= '0'; + reply_pool_dataready_in <= '0'; + init_select_enable <= '0'; + timer_us_reset <= '0'; + reply_open <= '0'; + + + case currentstate is + when IDLE => + real_active_points <= CTRL_activepoints(POINT_NUMBER-1 downto 0); +-- reply_reading_trm <= (others => '0'); + if or_all(INIT_DATAREADY_IN and real_active_points) = '1' then + currentstate <= SELECT_INIT; + init_select_enable <= '1'; + end if; + + when SELECT_INIT => + currentstate <= FORWARD_INIT; + init_current_type <= (others => '0'); + + when FORWARD_INIT => + if init_pool_free = '1' then + if init_selected_packet_num = c_H0 then + init_current_type <= init_selected_data(2 downto 0); + end if; + timer_us_reset <= '1'; + init_pool_data_in <= init_selected_data; + init_pool_packet_num_in <= init_selected_packet_num; + init_pool_dataready_in <= init_selected_dataready; + if init_current_type = TYPE_TRM and init_selected_packet_num = c_F3 then + currentstate <= SELECT_REPLY; + end if; + else + if timer_us = config_wait_free_init_pool then + timeout_ports <= timeout_ports or act_init_mask; + real_active_points <= real_active_points and not INIT_READ_IN; + end if; + end if; + + when SELECT_REPLY => + init_read_out_i <= (others => '0'); + reply_select_enable <= '1'; + if or_all(REPLY_DATAREADY_IN and CTRL_activepoints(POINT_NUMBER-1 downto 0) and not reply_reading_trm) = '1' then + timer_us_reset <= '1'; + currentstate <= WAIT_FOR_SELECT; + end if; + if timer_us = config_wait_reply then + timeout_ports <= timeout_ports or (not reply_reading_trm and not TRM_packet and real_active_points); + +--TODO: add proper handling + end if; + if and_all(reply_got_trm or act_init_mask) = '1' then + currentstate <= SEND_TRM; + send_trm_cnt <= 4; + end if; + + when WAIT_FOR_SELECT => + currentstate <= FORWARD_REPLY; + reply_open <= '1'; + + when FORWARD_REPLY => + if TRM_packet(act_reply_port) = '1' then + currentstate <= SELECT_REPLY; + reply_pool_dataready_in <= '0'; + elsif timer_us = config_wait_reply then --assume alsways full packets due to error correction + real_active_points <= real_active_points and not act_reply_mask; + timer_us_reset <= '1'; + timeout_ports <= timeout_ports or act_reply_mask; + currentstate <= SELECT_REPLY; + else + reply_open <= '1'; + reply_pool_data_in <= reply_selected_data; + reply_pool_packet_num_in <= reply_selected_packet_num; + reply_pool_dataready_in <= reply_selected_dataready; + end if; + if reply_selected_dataready = '1' then + timer_us_reset <= '1'; + end if; + + when SEND_TRM => + case send_trm_cnt is + when 4 => + if reply_pool_free = '1' then + send_trm_cnt <= 0; + end if; + reply_pool_data_in <= x"0003"; + when 0 => + if reply_pool_free = '1' then + send_trm_cnt <= 1; + end if; + reply_pool_data_in <= x"0000"; + when 1 => + if reply_pool_free = '1' then + send_trm_cnt <= 2; + end if; + reply_pool_data_in <= reply_combined_trm_f1; + when 2 => + if reply_pool_free = '1' then + send_trm_cnt <= 3; + end if; + reply_pool_data_in <= reply_combined_trm_f2; + when 3 => + if reply_pool_free = '1' then + currentstate <= FINISHED; + end if; + reply_pool_data_in <= reply_combined_trm_f3; + when others => null; + end case; + reply_pool_dataready_in <= reply_pool_free; + reply_pool_packet_num_in <= std_logic_vector(to_unsigned(send_trm_cnt,3)); + + when FINISHED => + currentstate <= IDLE; + + when REPLY_TIMEOUT => + null; + end case; + end process; + +reply_mux_read_out_i(act_reply_port) <= reply_pool_free and reply_open; + + +---------------------------------- +--SBuf for init output +---------------------------------- + + INIT_POOL_SBUF: trb_net16_sbuf + generic map ( + Version => std_SBUF_VERSION + ) + port map ( + CLK => CLK, + RESET => reset_i, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => init_pool_dataready_in, + COMB_next_READ_OUT => init_pool_free, + COMB_READ_IN => '1', + COMB_DATA_IN => init_pool_data_in, + COMB_PACKET_NUM_IN => init_pool_packet_num_in, + SYN_DATAREADY_OUT => init_pool_dataready_out, + SYN_DATA_OUT => init_pool_data_out, + SYN_PACKET_NUM_OUT => init_pool_packet_num_out, + SYN_READ_IN => init_pool_read_out + ); + + init_pool_reading <= init_pool_free when rising_edge(CLK); + + init_pool_read_out <= and_all(INIT_READ_IN or init_has_read_from_pool); + --Which ports have read data from pool + gen_hasread: for i in 0 to POINT_NUMBER-1 generate + process(CLK) + begin + if rising_edge(CLK) then + if reset_i = '1' then + init_has_read_from_pool(i) <= '0'; + elsif MII_IS_UPLINK_ONLY(i) = c_YES or real_active_points(i) = '0' or act_init_port = i then + init_has_read_from_pool(i) <= '1'; + elsif init_pool_read_out = '1' then + init_has_read_from_pool(i) <= '0'; + elsif (init_pool_dataready_out = '1' and INIT_READ_IN(i) = '1') then + init_has_read_from_pool(i) <= '1'; + end if; + end if; + end process; + end generate; + + +---------------------------------- +--SBuf for reply output +---------------------------------- + + REPLY_POOL_SBUF: trb_net16_sbuf + generic map ( + Version => std_SBUF_VERSION + ) + port map ( + CLK => CLK, + RESET => reset_i, + CLK_EN => CLK_EN, + COMB_DATAREADY_IN => reply_pool_dataready_in, + COMB_next_READ_OUT => reply_pool_free, + COMB_READ_IN => '1', + COMB_DATA_IN => reply_pool_data_in, + COMB_PACKET_NUM_IN => reply_pool_packet_num_in, + SYN_DATAREADY_OUT => reply_pool_dataready_out, + SYN_DATA_OUT => reply_pool_data_out, + SYN_PACKET_NUM_OUT => reply_pool_packet_num_out, + SYN_READ_IN => reply_pool_read_out + ); + reply_pool_reading <= reply_pool_free when rising_edge(CLK); + reply_pool_read_out <= REPLY_READ_IN(act_init_port); + +---------------------------------- +--connect output signals +---------------------------------- + gen_init_output : for i in 0 to POINT_NUMBER-1 generate + INIT_DATA_OUT(16*i+15 downto 16*i) <= init_pool_data_out; + INIT_PACKET_NUM_OUT(3*i+2 downto 3*i) <= init_pool_packet_num_out; + INIT_DATAREADY_OUT(i) <= init_pool_dataready_out and not init_has_read_from_pool(i); + REPLY_DATA_OUT(16*i+15 downto 16*i) <= reply_pool_data_out; + REPLY_PACKET_NUM_OUT(3*i+2 downto 3*i)<= reply_pool_packet_num_out; + REPLY_DATAREADY_OUT(i) <= reply_pool_dataready_out and act_init_mask(i); + end generate; + + +---------------------------------- +--Status registers +---------------------------------- + + STAT_POINTS_locked(31 downto POINT_NUMBER) <= (others => '0'); + + proc_stat_errorbits : process begin + wait until rising_edge(CLK); + if currentstate /= IDLE then + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= not reply_got_trm or not real_active_points or not act_init_mask; + else + STAT_POINTS_locked(POINT_NUMBER-1 downto 0) <= (others => '0'); + end if; + + if currentstate = IDLE then + STAT_ERRORBITS <= reply_combined_trm_f1 & reply_combined_trm_f2; + end if; + end process; + + gen_monitoring_errorbits : process(CLK) + begin + if rising_edge(CLK) then + for i in 0 to POINT_NUMBER-1 loop + if reading_trmF1(i) = '1' then + STAT_ALL_ERRORBITS(i*32+31 downto i*32+16) <= REPLY_DATA_IN(i*16+15 downto i*16); + elsif reading_trmF2(i) = '1' then + STAT_ALL_ERRORBITS(i*32+15 downto i*32+0) <= REPLY_DATA_IN(i*16+15 downto i*16); + end if; + end loop; + end if; + end process; + STAT_ALL_ERRORBITS(15*32+31 downto POINT_NUMBER*32) <= (others => '0'); + + STAT_TIMEOUT(POINT_NUMBER-1 downto 0) <= timeout_ports; + STAT_TIMEOUT(31 downto POINT_NUMBER) <= (others => '0'); + + STAT_locked <= '0' when currentstate = IDLE else '1'; + + STAT <= (others => '0'); + + +end architecture; + diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index a08776c..25af82d 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -193,7 +193,7 @@ counter_match <= '1'; begin if rising_edge(CLK) then if RESET = '1' then - current_rec_buffer_size_out <= x"0"; + current_rec_buffer_size_out <= x"6"; reg_ack_init_internal <= '0'; reg_ack_reply_internal <= '0'; reg_read_out <= '0'; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index bf47f60..6e33b9c 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -2396,7 +2396,7 @@ component priority_arbiter is ENABLE : in std_logic; INPUT : in std_logic_vector(INPUT_WIDTH-1 downto 0); OUTPUT_VEC : out std_logic_vector(INPUT_WIDTH-1 downto 0); - OUTPUT_NUM : out integer + OUTPUT_NUM : out integer range 0 to INPUT_WIDTH-1 ); end component; diff --git a/trb_net_sbuf.vhd b/trb_net_sbuf.vhd index e3939bd..dcd085f 100644 --- a/trb_net_sbuf.vhd +++ b/trb_net_sbuf.vhd @@ -107,6 +107,8 @@ architecture trb_net_sbuf_arch of trb_net_sbuf is begin + DEBUG_OUT <= (others => '0'); + SYN_DATA_OUT <= current_b2_buffer; SYN_DATAREADY_OUT <= current_SYN_DATAREADY_OUT; -- 2.43.0