From 265547d53cbc0316881af4b91283a2dc142f3307 Mon Sep 17 00:00:00 2001 From: Manuel Penschuck Date: Thu, 16 Oct 2014 21:31:15 +0200 Subject: [PATCH] CTS: Included bigger CBMNET read-out buffer in project (and adopted placement), routed add-on input to TDC --- cts/config_default.vhd | 2 +- cts/trb3_central.prj | 2 +- cts/trb3_central.vhd | 1 + cts/trb3_central_constraints_3.lpf | 24 +++++++++++++++--------- cts/trb3_central_syn.fdc | 7 ++++--- 5 files changed, 22 insertions(+), 14 deletions(-) diff --git a/cts/config_default.vhd b/cts/config_default.vhd index d1c18bb..c784661 100644 --- a/cts/config_default.vhd +++ b/cts/config_default.vhd @@ -13,7 +13,7 @@ package config is --include TDC for all four trigger input lines constant INCLUDE_TDC : integer range c_NO to c_YES := c_YES; - constant TDC_CHANNEL_NUMBER : integer := 5; + constant TDC_CHANNEL_NUMBER : integer := 4; --Use 64 word ringbuffer instead of 128 word ringbuffer in TDC channels constant USE_64_FIFO : integer := c_YES; diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 25fb2c8..fdb025f 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -383,7 +383,7 @@ if {$INCLUDE_CBMNET == 1} { add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_tx_gear.vhd" add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_phy_ecp3.vhd" - add_file -vhdl -lib work "../cbmnet/cores/cbmnet_fifo_18x2k_dp.vhd" + add_file -vhdl -lib work "../cbmnet/cores/cbmnet_fifo_18x32k_dp.vhd" add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_trbnet_decoder.vhd" add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_event_packer.vhd" add_file -vhdl -lib work "./cbmnet_bridge/cbmnet_readout_fifo_ecp3.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index ef54f79..b6882ac 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -1659,6 +1659,7 @@ begin tdc_inputs(1) <= cbm_sync_pulser_i; tdc_inputs(2) <= cbm_sync_dlm_sensed_i; tdc_inputs(3) <= cbm_sync_timing_trigger_i; + tdc_inputs(4) <= NIM_IN(0); PROC_TDC_CTRL_REG : process diff --git a/cts/trb3_central_constraints_3.lpf b/cts/trb3_central_constraints_3.lpf index 70e1a17..6ea9981 100644 --- a/cts/trb3_central_constraints_3.lpf +++ b/cts/trb3_central_constraints_3.lpf @@ -17,15 +17,12 @@ FREQUENCY PORT "CLK_GPLL_LEFT" 200.000000 MHz ; FREQUENCY NET "GEN_CTS.THE_CTS/cts_trigger_out" 100.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_200_i" 200.0 MHz; FREQUENCY NET "THE_MAIN_PLL/clk_100_i_c" 100.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_RX_GEAR/cbm_clk_i_c" 125.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch0" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch1" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUT" 250.0 MHz; -FREQUENCY NET "GEN_CBMNET.THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; FREQUENCY NET "osc_int" 20.0 MHz; FREQUENCY PORT "CLK_PCLK_RIGHT" 200.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.1.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; @@ -34,7 +31,9 @@ FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.3.Channels/Channel200/FSM_RD_STATE[2 FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.4.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.5.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/ReferenceChannel/Channel200/FSM_RD_STATE[2]" 100.0 MHz; - +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/clk_tx_full_i" 250.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_RX_GEAR/CLK_RX_HALF_OUT_c" 125.0 MHz; +FREQUENCY NET "GEN_CBMNET.THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/CLK_RX_FULL_OUTz" 250.0 MHz; ################################################################# @@ -54,10 +53,17 @@ LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset[*]" 30.000000 ns ; #MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30.000000 ns ; -REGION "MEDIA_UPLINK" "R92C90" 22 76 DEVSIZE; +#REGION "MEDIA_UPLINK" "R100C115D" 20 60 DEVSIZE; LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; -LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; +#LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; + +UGROUP "THE_MEDIA_ONBOARD_GROUP" BBOX 23 56 + BLKNAME THE_MEDIA_ONBOARD; +LOCATE UGROUP "THE_MEDIA_ONBOARD_GROUP" SITE "R100C125D" ; + + + #REGION "MEDIA_ONBOARD" "R90C122" 20 40; #MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; @@ -77,7 +83,7 @@ MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/trg_sync" 20.000000 ns ; MULTICYCLE TO CELL "gen_mbs_vulom_as_etm_THE_MBS/error_reg" 20.000000 ns ; #TrbNet Hub -REGION "REGION_IOBUF" "R35C35D" 65 85 DEVSIZE; +REGION "REGION_IOBUF" "R35C20D" 65 85 DEVSIZE; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.3.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.1.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF/genINITOBUF1.INITOBUF/OBUF_group" REGION "REGION_IOBUF" ; @@ -242,8 +248,8 @@ PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; #BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_tx_mac*" ; #BLOCK PATH FROM CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "GBE/imp_gen.MAC/U1_LSC_ts_mac_core/U1_rx_mac*" ; -LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R105C110D"; -LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R76C85D"; +LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R100C100D"; +LOCATE UGROUP "CBMNET_BRIDGE_GROUP" SITE "R42C106D"; LOCATE COMP "THE_CBM_BRIDGE/THE_CBM_PHY/THE_SERDES/PCSD_INST" SITE "PCSA" ; diff --git a/cts/trb3_central_syn.fdc b/cts/trb3_central_syn.fdc index 21da57a..79d48fd 100644 --- a/cts/trb3_central_syn.fdc +++ b/cts/trb3_central_syn.fdc @@ -14,11 +14,8 @@ ###==== END Collections ###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) -create_clock -name {rclk125} {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8} create_clock -name {clk100} {n:THE_MAIN_PLL.CLKOP} -period {10} create_clock {n:THE_MAIN_PLL.CLKOK} -period {5} -create_clock {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.rx_full_clk_ch0} -period {4} -create_clock {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.tx_full_clk_ch0} -period {4} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch0} -period {10} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch1} -period {10} create_clock {n:THE_MEDIA_ONBOARD.gen_serdes_200\.THE_SERDES.refclkdiv2_rx_ch2} -period {10} @@ -29,6 +26,10 @@ create_clock {n:GBE.imp_gen\.serdes_intclk_gen\.PCS_SERDES.clk_int\.SERDES_GBE. create_clock {p:CLK_GPLL_RIGHT} -period {8} create_clock {p:CLK_PCLK_RIGHT} -period {5} +create_clock -name {rclk125} {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_RX_GEAR.CLK_125_OUT} -period {8} +create_clock {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.rx_full_clk_ch0} -period {4} +create_clock {n:GEN_CBMNET\.THE_CBM_BRIDGE.THE_CBM_PHY.THE_SERDES.tx_full_clk_ch0} -period {4} + ###==== END Clocks ###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) -- 2.43.0