From 26a33972b9434514616ce3b87c0a956af1f81d94 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 14 Nov 2022 13:54:43 +0100 Subject: [PATCH] the long and winding road --- gbe_trb/base/gbe_frame_constr.vhd | 31 +- gbe_trb/base/gbe_frame_receiver.vhd | 44 +-- gbe_trb/base/gbe_logic_wrapper.vhd | 23 -- gbe_trb/base/gbe_protocol_selector.vhd | 1 + gbe_trb/base/gbe_receive_control.vhd | 36 ++- gbe_trb/base/gbe_transmit_control.vhd | 105 +++---- gbe_trb/base/gbe_wrapper_fifo.vhd | 9 +- .../gbe_response_constructor_ARP.vhd | 15 +- .../gbe_response_constructor_DHCP.vhd | 56 ++-- .../gbe_response_constructor_Discovery.vhd | 2 +- .../gbe_response_constructor_Forward.vhd | 82 ++--- .../gbe_response_constructor_Ping.vhd | 87 +++--- .../gbe_response_constructor_SCTRL.vhd | 69 ++--- special/spi_databus_memory.vhd | 202 ++++++------ special/spi_flash_and_fpga_reload_record.vhd | 253 ++++++++------- special/spi_master.vhd | 290 +++++++++--------- trb_net16_api_base.vhd | 26 +- trb_net16_endpoint_standalone_sctrl.vhd | 47 +-- trb_net16_ibuf.vhd | 23 +- trb_net16_io_multiplexer.vhd | 60 ++-- trb_net16_iobuf.vhd | 34 +- trb_net16_obuf.vhd | 16 +- trb_net16_regIO.vhd | 205 +++++++------ trb_net16_sbuf.vhd | 28 +- 24 files changed, 845 insertions(+), 899 deletions(-) diff --git a/gbe_trb/base/gbe_frame_constr.vhd b/gbe_trb/base/gbe_frame_constr.vhd index 50fe120..41d2c46 100644 --- a/gbe_trb/base/gbe_frame_constr.vhd +++ b/gbe_trb/base/gbe_frame_constr.vhd @@ -33,7 +33,6 @@ entity gbe_frame_constr is FLAGS_OFFSET_IN : in std_logic_vector(15 downto 0); TTL_IN : in std_logic_vector(7 downto 0); PROTOCOL_IN : in std_logic_vector(7 downto 0); - FRAME_DELAY_IN : in std_logic_vector(31 downto 0); -- port for "RX ringbuffer" FT_TX_DATA_OUT : out std_logic_vector(8 downto 0); FT_TX_WR_OUT : out std_logic; @@ -73,8 +72,6 @@ architecture gbe_frame_constr_arch of gbe_frame_constr is signal ip_cs_temp_right : unsigned(15 downto 0); --- signal delay_ctr : std_logic_vector(31 downto 0); --- signal frame_delay_reg : std_logic_vector(31 downto 0); signal fpf_data_q : std_logic_vector(7 downto 0); signal fpf_wr_en_q : std_logic; signal fpf_eod_q : std_logic; @@ -209,12 +206,9 @@ begin end process PROC_CONSTRUCT; --find next state of construct machine --- PROC_CONSTRUCT_TRANSITIONS: process( CONSTRUCT_CS, delay_ctr, FRAME_DELAY_IN, START_OF_DATA_IN, --- END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, --- FRAME_TYPE_IN, DEST_UDP_PORT_IN) - PROC_CONSTRUCT_TRANSITIONS: process( CONSTRUCT_CS, START_OF_DATA_IN, - END_OF_DATA_IN, headers_int_counter, put_udp_headers, CUR_MAX, - FRAME_TYPE_IN, DEST_UDP_PORT_IN) + PROC_CONSTRUCT_TRANSITIONS: process( CONSTRUCT_CS, START_OF_DATA_IN, END_OF_DATA_IN, + headers_int_counter, put_udp_headers, CUR_MAX, + FRAME_TYPE_IN, DEST_UDP_PORT_IN ) begin CONSTRUCT_NS <= CONSTRUCT_CS; if( headers_int_counter = cur_max ) then --can be checked everytime - if not in use, counter and cur_max are 0 @@ -273,31 +267,12 @@ begin CONSTRUCT_NS <= DELAY; when DELAY => CONSTRUCT_NS <= IDLE; --- if (delay_ctr = FRAME_DELAY_IN) then --- CONSTRUCT_NS <= IDLE; --- else --- CONSTRUCT_NS <= DELAY; --- end if; - when others => CONSTRUCT_NS <= IDLE; end case; end if; end process PROC_CONSTRUCT_TRANSITIONS; --- PROC_DELAY_CTR: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- if ( (CONSTRUCT_CS = IDLE) or (CONSTRUCT_CS = CLEANUP) ) then --- delay_ctr <= (others => '0'); --- elsif( CONSTRUCT_CS = DELAY ) then --- delay_ctr <= delay_ctr + x"1"; --- end if; --- --- frame_delay_reg <= FRAME_DELAY_IN; --- end if; --- end process PROC_DELAY_CTR; - PROC_BSM_CONSTR: process( CONSTRUCT_CS ) begin --find maximum time in each state & set state bits diff --git a/gbe_trb/base/gbe_frame_receiver.vhd b/gbe_trb/base/gbe_frame_receiver.vhd index 7b8b48a..abfe514 100644 --- a/gbe_trb/base/gbe_frame_receiver.vhd +++ b/gbe_trb/base/gbe_frame_receiver.vhd @@ -1,11 +1,10 @@ -library IEEE; - use IEEE.std_logic_1164.all; - use IEEE.numeric_std.all; - use IEEE.std_logic_UNSIGNED.all; +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; library work; - use work.trb_net_std.all; - use work.gbe_protocols.all; + +-- BUG: include "BAD FRAME" in frame info vector for dropping stuff in second stage entity gbe_frame_receiver is port( @@ -31,6 +30,7 @@ entity gbe_frame_receiver is FR_FRAME_SIZE_OUT : out std_logic_vector(15 downto 0); -- interconnect to gbe_receive_control FR_PS_OUT : out std_logic_vector(7 downto 0); FR_FRAME_INFO_OUT : out std_logic_vector(7 downto 0); + FR_FRAME_AVAIL_OUT : out std_logic; -- FR_SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); FR_SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); @@ -124,6 +124,10 @@ architecture gbe_frame_receiver_arch of gbe_frame_receiver is signal fifo_one_q : std_logic_vector(71 downto 0); signal fifo_two_q : std_logic_vector(71 downto 0); + signal fifo_one_empty : std_logic; + signal fifo_two_empty : std_logic; + signal frame_avail : std_logic; + begin -- buffer incoming signals @@ -139,9 +143,9 @@ begin begin if ( RESET = '1' ) then DECODE_CS <= IDLE; - fifo_hd_wr <= '0'; - drop_frame <= '0'; - rst_bytes <= '1'; + fifo_hd_wr <= '0'; + drop_frame <= '0'; + rst_bytes <= '1'; elsif( rising_edge(CLK) ) then DECODE_CS <= DECODE_NS; fifo_hd_wr <= fifo_hd_wr_x; @@ -162,11 +166,11 @@ begin when IDLE => decode_fsm <= x"0"; - if( MAC_RX_EN_IN = '1' ) then - DECODE_NS <= STORE_HEADER; - else - DECODE_NS <= IDLE; - end if; + if( MAC_RX_EN_IN = '1' ) then + DECODE_NS <= STORE_HEADER; + else + DECODE_NS <= IDLE; + end if; when STORE_HEADER => decode_fsm <= x"1"; @@ -486,8 +490,8 @@ begin WrEn => fifo_hd_wr_q, RdEn => FR_GET_FRAME_IN, Reset => RESET, - Q => fifo_one_q, - Empty => open, -- BUG + Q => fifo_one_q, + Empty => fifo_one_empty, Full => open -- BUG ); @@ -510,8 +514,8 @@ begin WrEn => fifo_hd_wr_q, RdEn => FR_GET_FRAME_IN, Reset => RESET, - Q => fifo_two_q, - Empty => open, -- BUG + Q => fifo_two_q, + Empty => fifo_two_empty, Full => open -- BUG ); @@ -523,6 +527,9 @@ begin fr_ps <= fifo_two_q(55 downto 48); fr_info <= fifo_two_q(63 downto 56); + -- basically one FIFO status would be enough + frame_avail <= '1' when ((fifo_one_empty = '0') or (fifo_two_empty = '0')) else '0'; + PROC_OUT_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then @@ -533,6 +540,7 @@ begin FR_Q_OUT <= fr_q; FR_PS_OUT <= fr_ps; FR_FRAME_INFO_OUT <= fr_info; + FR_FRAME_AVAIL_OUT <= frame_avail; end if; end process PROC_OUT_SYNC; diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd index 26bed21..f75ab22 100644 --- a/gbe_trb/base/gbe_logic_wrapper.vhd +++ b/gbe_trb/base/gbe_logic_wrapper.vhd @@ -3,7 +3,6 @@ library ieee; use ieee.numeric_std.all; library work; --- use work.gbe_protocols.all; entity gbe_logic_wrapper is generic( @@ -145,7 +144,6 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is signal dhcp_done : std_logic; signal make_reset : std_logic; - signal frame_pause : std_logic_vector(31 downto 0); signal fr_ps : std_logic_vector(7 downto 0); signal fr_frame_info : std_logic_vector(7 downto 0); @@ -168,24 +166,6 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- ----- DEBUG_OUT(31 downto 0) <= (others => '0'); --- DEBUG_OUT(31 downto 28) <= debug_fr(31 downto 28); -- frame receiver state --- DEBUG_OUT(27 downto 24) <= debug_rc(3 downto 0); -- receive control state --- DEBUG_OUT(23 downto 20) <= debug_main(23 downto 20); -- redirect state --- DEBUG_OUT(19 downto 16) <= fr_ps(3 downto 0); --debug_main(27 downto 24); -- link state --- DEBUG_OUT(15) <= rc_loading_done; --- DEBUG_OUT(14) <= rc_frame_ready; --- DEBUG_OUT(13) <= fr_ps(4); --rc_frame_proto(4); -- ICMP --- DEBUG_OUT(12) <= fr_ps(1); --rc_frame_proto(1); -- DHCP --- DEBUG_OUT(11) <= fr_ps(0); --rc_frame_proto(0); -- ARP --- DEBUG_OUT(10) <= fr_get_frame; --- DEBUG_OUT(9) <= fr_frame_valid; --- DEBUG_OUT(8) <= fr_rd_en; --- DEBUG_OUT(7 downto 0) <= rc_q(7 downto 0); ---------------------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------------------------- --- DEBUG_OUT(31 downto 28) <= debug_fr(31 downto 28); --- DEBUG_OUT(27 downto 0) <= debug_main(27 downto 0); DEBUG_OUT(31 downto 0) <= debug_main(31 downto 0); --------------------------------------------------------------------------------------------------- --------------------------------------------------------------------------------------------------- @@ -342,7 +322,6 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is FLAGS_OFFSET_IN => fc_flags_offset, TTL_IN => x"40", PROTOCOL_IN => fc_protocol, - FRAME_DELAY_IN => frame_pause, FT_TX_DATA_OUT => FT_TX_DATA_OUT, FT_TX_WR_OUT => FT_TX_WR_OUT, FT_TX_FIFOFULL_IN => FT_TX_FIFOFULL_IN, @@ -350,8 +329,6 @@ architecture gbe_logic_wrapper_arch of gbe_logic_wrapper is MONITOR_TX_FRAMES_OUT => MONITOR_TX_FRAMES_OUT ); - frame_pause <= x"0000" & x"0000"; -- TAKE CARE!!! - THE_RECEIVE_CONTROL: entity work.gbe_receive_control port map( CLK => CLK_125_IN, diff --git a/gbe_trb/base/gbe_protocol_selector.vhd b/gbe_trb/base/gbe_protocol_selector.vhd index c49cf88..d32caa5 100644 --- a/gbe_trb/base/gbe_protocol_selector.vhd +++ b/gbe_trb/base/gbe_protocol_selector.vhd @@ -158,6 +158,7 @@ begin PS_RESPONSE_READY_OUT => resp_ready(0), PS_BUSY_OUT => busy(0), PS_SELECTED_IN => selected(0), + PS_FRAME_SIZE_IN => PS_FRAME_SIZE_IN, PS_SRC_MAC_ADDRESS_IN => PS_SRC_MAC_ADDRESS_IN, PS_SRC_IP_ADDRESS_IN => PS_SRC_IP_ADDRESS_IN, PS_SRC_UDP_PORT_IN => PS_SRC_UDP_PORT_IN, diff --git a/gbe_trb/base/gbe_receive_control.vhd b/gbe_trb/base/gbe_receive_control.vhd index a1b368a..182c83d 100644 --- a/gbe_trb/base/gbe_receive_control.vhd +++ b/gbe_trb/base/gbe_receive_control.vhd @@ -47,9 +47,9 @@ architecture gbe_receive_control_arch of gbe_receive_control is attribute syn_encoding : string; - type load_states is (IDLE, PREPARE, WAIT_ONE, READY); - signal load_current_state, load_next_state : load_states; - attribute syn_encoding of load_current_state : signal is "onehot"; + type LOAD_STATES is (IDLE, PREPARE, WAIT_ONE, READY); + signal LOAD_CS, LOAD_NS : LOAD_STATES; + attribute syn_encoding of LOAD_CS : signal is "onehot"; signal frames_received_ctr : unsigned(31 downto 0); signal frames_readout_ctr : unsigned(31 downto 0); @@ -69,58 +69,62 @@ begin RC_SRC_IP_ADDRESS_OUT <= FR_SRC_IP_ADDRESS_IN; RC_SRC_UDP_PORT_OUT <= FR_SRC_UDP_PORT_IN; RC_FRAME_INFO_OUT <= FR_FRAME_INFO_IN; - RC_FRAME_PROTO_OUT <= FR_PS_IN when (load_current_state /= IDLE) else (others => '0'); + RC_FRAME_PROTO_OUT <= FR_PS_IN when (LOAD_CS /= IDLE) else (others => '0'); LOAD_MACHINE_PROC: process( CLK, RESET ) begin if ( RESET = '1' ) then - load_current_state <= IDLE; + LOAD_CS <= IDLE; elsif( rising_edge(CLK) ) then - load_current_state <= load_next_state; + LOAD_CS <= LOAD_NS; end if; end process LOAD_MACHINE_PROC; - LOAD_MACHINE: process( load_current_state, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) + LOAD_MACHINE: process( LOAD_CS, frames_readout_ctr, frames_received_ctr, RC_LOADING_DONE_IN ) begin - case load_current_state is + case LOAD_CS is when IDLE => state <= x"1"; if( frames_readout_ctr /= frames_received_ctr ) then -- frame is still waiting in frame_receiver - load_next_state <= PREPARE; + LOAD_NS <= PREPARE; else - load_next_state <= IDLE; + LOAD_NS <= IDLE; end if; when PREPARE => -- prepare frame size state <= x"2"; - load_next_state <= WAIT_ONE; + LOAD_NS <= WAIT_ONE; when WAIT_ONE => state <= x"4"; - load_next_state <= READY; + LOAD_NS <= READY; when READY => -- wait for reading out the whole frame state <= x"3"; if( RC_LOADING_DONE_IN = '1' ) then - load_next_state <= IDLE; + LOAD_NS <= IDLE; else - load_next_state <= READY; + LOAD_NS <= READY; end if; + when others => + state <= x"f"; + LOAD_NS <= IDLE; + end case; end process LOAD_MACHINE; process( CLK ) begin if( rising_edge(CLK) ) then - if( load_current_state = PREPARE ) then + if( LOAD_CS = PREPARE ) then FR_GET_FRAME_OUT <= '1'; else FR_GET_FRAME_OUT <= '0'; end if; - if( (load_current_state = READY) and (RC_LOADING_DONE_IN = '0') ) then + if( (LOAD_CS = READY) and (RC_LOADING_DONE_IN = '0') ) then RC_FRAME_WAITING_OUT <= '1'; else RC_FRAME_WAITING_OUT <= '0'; diff --git a/gbe_trb/base/gbe_transmit_control.vhd b/gbe_trb/base/gbe_transmit_control.vhd index 4bddddc..ac45cfb 100644 --- a/gbe_trb/base/gbe_transmit_control.vhd +++ b/gbe_trb/base/gbe_transmit_control.vhd @@ -3,54 +3,52 @@ library IEEE; use IEEE.numeric_std.all; library work; --- use work.trb_net_std.all; --- use work.gbe_protocols.all; entity gbe_transmit_control is -port ( - CLK : in std_logic; - RESET : in std_logic; --- signal to/from main controller - TC_DATAREADY_IN : in std_logic; - TC_RD_EN_OUT : out std_logic; - TC_DATA_IN : in std_logic_vector(7 downto 0); - TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); - TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); - TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); - TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); - TC_DEST_IP_IN : in std_logic_vector(31 downto 0); - TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); - TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); - TC_SRC_IP_IN : in std_logic_vector(31 downto 0); - TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); - TC_TRANSMISSION_DONE_OUT : out std_logic; - TC_IDENT_IN : in std_logic_vector(15 downto 0); - TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); --- signal to/from frame constructor - FC_DATA_OUT : out std_logic_vector(7 downto 0); - FC_WR_EN_OUT : out std_logic; - FC_READY_IN : in std_logic; - FC_H_READY_IN : in std_logic; - FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); - FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); - FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter - FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); - FC_SOD_OUT : out std_logic; - FC_EOD_OUT : out std_logic; - FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); --- - DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); - SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); - SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); - SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); --- - MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); --- - DEBUG_OUT : out std_logic_vector(63 downto 0) -); + port ( + CLK : in std_logic; + RESET : in std_logic; + -- signal to/from main controller + TC_DATAREADY_IN : in std_logic; + TC_RD_EN_OUT : out std_logic; + TC_DATA_IN : in std_logic_vector(7 downto 0); + TC_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); + TC_FRAME_TYPE_IN : in std_logic_vector(15 downto 0); + TC_IP_PROTOCOL_IN : in std_logic_vector(7 downto 0); + TC_DEST_MAC_IN : in std_logic_vector(47 downto 0); + TC_DEST_IP_IN : in std_logic_vector(31 downto 0); + TC_DEST_UDP_IN : in std_logic_vector(15 downto 0); + TC_SRC_MAC_IN : in std_logic_vector(47 downto 0); + TC_SRC_IP_IN : in std_logic_vector(31 downto 0); + TC_SRC_UDP_IN : in std_logic_vector(15 downto 0); + TC_TRANSMISSION_DONE_OUT : out std_logic; + TC_IDENT_IN : in std_logic_vector(15 downto 0); + TC_MAX_FRAME_IN : in std_logic_vector(15 downto 0); + -- signal to/from frame constructor + FC_DATA_OUT : out std_logic_vector(7 downto 0); + FC_WR_EN_OUT : out std_logic; + FC_READY_IN : in std_logic; + FC_H_READY_IN : in std_logic; + FC_FRAME_TYPE_OUT : out std_logic_vector(15 downto 0); + FC_IP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_UDP_SIZE_OUT : out std_logic_vector(15 downto 0); + FC_IDENT_OUT : out std_logic_vector(15 downto 0); -- internal packet counter + FC_FLAGS_OFFSET_OUT : out std_logic_vector(15 downto 0); + FC_SOD_OUT : out std_logic; + FC_EOD_OUT : out std_logic; + FC_IP_PROTOCOL_OUT : out std_logic_vector(7 downto 0); + -- + DEST_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + DEST_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + DEST_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + SRC_MAC_ADDRESS_OUT : out std_logic_vector(47 downto 0); + SRC_IP_ADDRESS_OUT : out std_logic_vector(31 downto 0); + SRC_UDP_PORT_OUT : out std_logic_vector(15 downto 0); + -- + MONITOR_TX_PACKETS_OUT : out std_logic_vector(31 downto 0); + -- + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); end gbe_transmit_control; architecture gbe_transmit_control_arch of gbe_transmit_control is @@ -156,6 +154,10 @@ begin state <= x"a"; TRANSMIT_NS <= IDLE; + when others => + state <= x"f"; + TRANSMIT_NS <= IDLE; + end case; end process PROC_TRANSMIT_TRANSITIONS; @@ -221,8 +223,6 @@ begin else ip_size <= local_end + 1; end if; - else - ip_size <= ip_size; end if; end if; end process PROC_IP_SIZE; @@ -254,7 +254,7 @@ begin if ( TRANSMIT_CS = IDLE ) then packet_loaded_bytes <= x"0000"; elsif( TRANSMIT_CS = TRANSMIT ) then - packet_loaded_bytes <= packet_loaded_bytes + x"1"; + packet_loaded_bytes <= packet_loaded_bytes + 1; end if; end if; end process PROC_PACKET_LOADED_BYTES; @@ -290,14 +290,15 @@ begin mon_packets_sent_ctr <= (others => '0'); elsif( rising_edge(CLK) ) then if( TRANSMIT_CS = CLEANUP ) then - mon_packets_sent_ctr <= mon_packets_sent_ctr + x"1"; + mon_packets_sent_ctr <= mon_packets_sent_ctr + 1; end if; end if; end process PROC_PACKETS_SENT; MONITOR_TX_PACKETS_OUT <= mon_packets_sent_ctr; - DEBUG_OUT(3 downto 0) <= state; - DEBUG_OUT(4) <= FC_READY_IN; + DEBUG_OUT(63 downto 5) <= (others => '0'); + DEBUG_OUT(4) <= FC_READY_IN; + DEBUG_OUT(3 downto 0) <= state; end gbe_transmit_control_arch; diff --git a/gbe_trb/base/gbe_wrapper_fifo.vhd b/gbe_trb/base/gbe_wrapper_fifo.vhd index 1337a10..343c28f 100644 --- a/gbe_trb/base/gbe_wrapper_fifo.vhd +++ b/gbe_trb/base/gbe_wrapper_fifo.vhd @@ -3,7 +3,6 @@ library ieee; use ieee.numeric_std.all; library work; --- use work.gbe_protocols.all; entity gbe_wrapper_fifo is generic( @@ -219,7 +218,7 @@ begin DEBUG_OUT => DEBUG_OUT --open ); - NOSCTRL_MAP_GEN : if( LINK_HAS_SLOWCTRL = '0' ) generate + GEN_NOSCTRL_MAP: if( LINK_HAS_SLOWCTRL = '0' ) generate mlt_gsc_clk <= '0'; GSC_INIT_DATAREADY_OUT <= '0'; GSC_INIT_DATA_OUT <= (others => '0'); @@ -230,9 +229,9 @@ begin mlt_gsc_reply_data <= (others => '0'); mlt_gsc_reply_packet <= (others => '0'); mlt_gsc_busy <= '0'; - end generate NOSCTRL_MAP_GEN; + end generate GEN_NOSCTRL_MAP; - SCTRL_MAP_GEN : if( LINK_HAS_SLOWCTRL = '1' ) generate + GEN_SCTRL_MAP: if( LINK_HAS_SLOWCTRL = '1' ) generate mlt_gsc_clk <= GSC_CLK_IN; GSC_INIT_DATAREADY_OUT <= mlt_gsc_init_dataready; GSC_INIT_DATA_OUT <= mlt_gsc_init_data; @@ -243,6 +242,6 @@ begin mlt_gsc_reply_data <= GSC_REPLY_DATA_IN; mlt_gsc_reply_packet <= GSC_REPLY_PACKET_NUM_IN; mlt_gsc_busy <= GSC_BUSY_IN; - end generate SCTRL_MAP_GEN; + end generate GEN_SCTRL_MAP; end architecture gbe_wrapper_fifo_arch; diff --git a/gbe_trb/protocols/gbe_response_constructor_ARP.vhd b/gbe_trb/protocols/gbe_response_constructor_ARP.vhd index d30abef..ffde95d 100644 --- a/gbe_trb/protocols/gbe_response_constructor_ARP.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_ARP.vhd @@ -3,16 +3,14 @@ library ieee; use ieee.numeric_std.all; library work; - use work.gbe_protocols.all; - --- BUG: doesnt use FRAME_SIZE, but fixed length. +-- use work.gbe_protocols.all; -- BUG: check (length == 28) for correct request. -- BUG: check request type at all. entity gbe_response_constructor_ARP is - port ( + port( CLK : in std_logic; -- system clock RESET : in std_logic; MY_MAC_IN : in std_logic_vector(47 downto 0); @@ -23,6 +21,7 @@ entity gbe_response_constructor_ARP is PS_RESPONSE_READY_OUT : out std_logic; PS_BUSY_OUT : out std_logic; PS_SELECTED_IN : in std_logic; + PS_FRAME_SIZE_IN : in std_logic_vector(15 downto 0); PS_SRC_MAC_ADDRESS_IN : in std_logic_vector(47 downto 0); PS_SRC_IP_ADDRESS_IN : in std_logic_vector(31 downto 0); PS_SRC_UDP_PORT_IN : in std_logic_vector(15 downto 0); @@ -54,7 +53,6 @@ architecture gbe_response_constructor_ARP_arch of gbe_response_constructor_ARP i signal stats_current_state, stats_next_state : stats_states; attribute syn_encoding of stats_current_state : signal is "onehot"; - signal saved_opcode : std_logic_vector(15 downto 0); -- NOT USED signal saved_sender_ip : std_logic_vector(31 downto 0); signal saved_target_ip : std_logic_vector(31 downto 0); signal tc_data : std_logic_vector(8 downto 0); @@ -105,7 +103,7 @@ begin when DECIDE => state <= x"3"; - if( saved_target_ip = MY_IP_IN ) then + if( (saved_target_ip = MY_IP_IN) and (PS_FRAME_SIZE_IN = x"1c") ) then DISSECT_NS <= WAIT_FOR_LOAD; -- in case the request is not for me, drop it else @@ -157,17 +155,12 @@ begin PROC_SAVE_VALUES: process( CLK, RESET ) begin if ( RESET = '1' ) then - saved_opcode <= (others => '0'); saved_sender_ip <= (others => '0'); saved_target_ip <= (others => '0'); elsif( rising_edge(CLK) ) then if( DISSECT_CS = READ_FRAME ) then case dissect_ctr is - when x"06" => - saved_opcode(7 downto 0) <= PS_DATA_IN(7 downto 0); - when x"07" => - saved_opcode(15 downto 8) <= PS_DATA_IN(7 downto 0); when x"0e" => saved_sender_ip(7 downto 0) <= PS_DATA_IN(7 downto 0); when x"0f" => diff --git a/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd b/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd index 01606ac..827a35a 100644 --- a/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_DHCP.vhd @@ -3,7 +3,7 @@ library ieee; use ieee.numeric_std.all; library work; - use work.gbe_protocols.all; +-- use work.gbe_protocols.all; entity gbe_response_constructor_DHCP is port( @@ -44,7 +44,6 @@ entity gbe_response_constructor_DHCP is ); end gbe_response_constructor_DHCP; - architecture gbe_response_constructor_DHCP_arch of gbe_response_constructor_DHCP is attribute syn_encoding : string; @@ -233,6 +232,7 @@ begin end if; when others => + main_state <= x"f"; MAIN_NS <= BOOTING; end case; @@ -269,12 +269,11 @@ begin PROC_RECEIVE_TRANSITIONS: process( RECEIVE_CS, MAIN_CS, bootp_hdr, saved_dhcp_type, saved_transaction_id, PS_FRAME_INFO_IN, PS_DATA_IN, MY_MAC_IN, PS_ACTIVATE_IN, PS_WR_EN_IN, save_ctr ) begin - recv_state <= x"0"; - + case RECEIVE_CS is when IDLE => - recv_state <= x"1"; + recv_state <= x"0"; if( (PS_ACTIVATE_IN = '1') and (PS_WR_EN_IN = '1') ) then if( (MAIN_CS = WAITING_FOR_OFFER) or (MAIN_CS = WAITING_FOR_ACK) ) then -- ready to receive dhcp frame if( PS_FRAME_INFO_IN(0) = '1' ) then -- check if i'm the addressee (discards broadcasts also) @@ -290,7 +289,7 @@ begin end if; when SAVE_VALUES => - recv_state <= x"2"; + recv_state <= x"1"; -- BUG: fails on empty payload if ( PS_DATA_IN(8) = '1' ) then RECEIVE_NS <= CLEANUP; @@ -308,7 +307,7 @@ begin end if; when DISCARD => - recv_state <= x"3"; + recv_state <= x"2"; -- BUG: fails on empty payload if( PS_DATA_IN(8) = '1' ) then RECEIVE_NS <= CLEANUP; @@ -317,10 +316,11 @@ begin end if; when CLEANUP => - recv_state <= x"4"; + recv_state <= x"3"; RECEIVE_NS <= IDLE; when others => + recv_state <= x"f"; RECEIVE_NS <= IDLE; end case; @@ -456,12 +456,11 @@ begin PROC_CONSTRUCT_TRANSITIONS: process( CONSTRUCT_CS, MAIN_CS, load_ctr, PS_SELECTED_IN ) begin - cons_state <= x"0"; case CONSTRUCT_CS is when IDLE => - cons_state <= x"1"; + cons_state <= x"0"; if( (MAIN_CS = SENDING_DISCOVER) or (MAIN_CS = SENDING_REQUEST) ) then CONSTRUCT_NS <= WAIT_FOR_LOAD; else @@ -469,7 +468,7 @@ begin end if; when WAIT_FOR_LOAD => - cons_state <= x"2"; + cons_state <= x"1"; if( PS_SELECTED_IN = '1' ) then CONSTRUCT_NS <= BOOTP_HEADERS; else @@ -477,7 +476,7 @@ begin end if; when BOOTP_HEADERS => - cons_state <= x"3"; + cons_state <= x"2"; if( load_ctr = 11 ) then CONSTRUCT_NS <= CLIENT_IP; else @@ -485,7 +484,7 @@ begin end if; when CLIENT_IP => - cons_state <= x"4"; + cons_state <= x"3"; if( load_ctr = 15 ) then CONSTRUCT_NS <= YOUR_IP; else @@ -493,7 +492,7 @@ begin end if; when YOUR_IP => - cons_state <= x"5"; + cons_state <= x"4"; if( load_ctr = 19 ) then CONSTRUCT_NS <= ZEROS1; else @@ -501,7 +500,7 @@ begin end if; when ZEROS1 => - cons_state <= x"6"; + cons_state <= x"5"; if( load_ctr = 27 ) then CONSTRUCT_NS <= MY_MAC; else @@ -509,7 +508,7 @@ begin end if; when MY_MAC => - cons_state <= x"7"; + cons_state <= x"6"; if( load_ctr = 33 ) then CONSTRUCT_NS <= ZEROS2; else @@ -517,7 +516,7 @@ begin end if; when ZEROS2 => - cons_state <= x"8"; + cons_state <= x"7"; if( load_ctr = 235 ) then CONSTRUCT_NS <= VENDOR_VALS; else @@ -525,7 +524,7 @@ begin end if; when VENDOR_VALS => - cons_state <= x"9"; + cons_state <= x"8"; if( load_ctr = 257 ) then -- for discover it's enough of values if( MAIN_CS = SENDING_DISCOVER ) then @@ -539,7 +538,7 @@ begin end if; when VENDOR_VALS2 => - cons_state <= x"a"; + cons_state <= x"9"; if( load_ctr = 263 ) then CONSTRUCT_NS <= TERMINATION; else @@ -547,14 +546,15 @@ begin end if; when TERMINATION => - cons_state <= x"b"; + cons_state <= x"a"; CONSTRUCT_NS <= CLEANUP; when CLEANUP => - cons_state <= x"c"; + cons_state <= x"b"; CONSTRUCT_NS <= IDLE; when others => + cons_state <= x"f"; CONSTRUCT_NS <= IDLE; end case; @@ -657,7 +657,7 @@ begin -- fixed sizes for discover and request messages TC_FRAME_SIZE_OUT <= x"0103" when (MAIN_CS = SENDING_DISCOVER) else x"0109"; - TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip + TC_FRAME_TYPE_OUT <= x"0008"; -- swapped bytes TC_IDENT_OUT <= x"1" & std_logic_vector(sent_frames(11 downto 0)); PROC_SENT_FRAMES: process( CLK ) @@ -671,16 +671,4 @@ begin end if; end process PROC_SENT_FRAMES; - -- **** debug --- PROC_DEBUG: process( CLK ) --- begin --- if( rising_edge(CLK) ) then --- DEBUG_OUT(3 downto 0) <= cons_state; --- DEBUG_OUT(7 downto 4) <= main_state; --- DEBUG_OUT(11 downto 8) <= recv_state; --- end if; --- end process PROC_DEBUG; - - -- **** - end gbe_response_constructor_DHCP_arch; diff --git a/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd b/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd index 68872fa..05fa7ea 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Discovery.vhd @@ -3,7 +3,7 @@ library ieee; use ieee.numeric_std.all; library work; - use work.gbe_protocols.all; +-- use work.gbe_protocols.all; -- New protocol: will drop received frames and not send back yet diff --git a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd index 83b723b..6114395 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Forward.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Forward.vhd @@ -1,10 +1,10 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use IEEE.std_logic_UNSIGNED.all; library work; -use work.trb_net_std.all; +-- use work.trb_net_std.all; -- WARNING: data latency was wrong by one cycle (first byte not sent, last byte duplicated), and -- size was calculated wrong (one off). Works now FOR ME. To be tested carefully! @@ -62,9 +62,9 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F attribute syn_encoding : string; - type dissect_states is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); - signal dissect_current_state, dissect_next_state : dissect_states; - attribute syn_encoding of dissect_current_state: signal is "safe,gray"; + type DISSECT_STATES is (IDLE, SAVE, WAIT_FOR_LOAD, LOAD, CLEANUP); + signal DISSECT_CS, DISSECT_NS : DISSECT_STATES; + attribute syn_encoding of DISSECT_CS: signal is "safe,gray"; signal ff_wr_en : std_logic; signal ff_rd_en : std_logic; @@ -85,65 +85,69 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F PROC_DISSECT_FSM: process( CLK, RESET ) begin if ( RESET = '1' ) then - dissect_current_state <= IDLE; + DISSECT_CS <= IDLE; elsif( rising_edge(CLK) ) then - dissect_current_state <= dissect_next_state; + DISSECT_CS <= DISSECT_NS; end if; end process PROC_DISSECT_FSM; - PROC_DISSECT_TRANSITIONS: process( dissect_current_state, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN ) + PROC_DISSECT_TRANSITIONS: process( DISSECT_CS, FWD_SOP_IN, FWD_EOP_IN, ff_q, ff_rd_lock, PS_SELECTED_IN ) begin - case dissect_current_state is + case DISSECT_CS is when IDLE => - state <= x"1"; - if (FWD_SOP_IN = '1') then - dissect_next_state <= SAVE; + state <= x"0"; + if( FWD_SOP_IN = '1' ) then + DISSECT_NS <= SAVE; else - dissect_next_state <= IDLE; + DISSECT_NS <= IDLE; end if; when SAVE => - state <= x"2"; - if (FWD_EOP_IN = '1') then - dissect_next_state <= WAIT_FOR_LOAD; + state <= x"1"; + if( FWD_EOP_IN = '1' ) then + DISSECT_NS <= WAIT_FOR_LOAD; else - dissect_next_state <= SAVE; + DISSECT_NS <= SAVE; end if; when WAIT_FOR_LOAD => - state <= x"3"; - if (PS_SELECTED_IN = '0') then - dissect_next_state <= LOAD; + state <= x"2"; + if( PS_SELECTED_IN = '0' ) then + DISSECT_NS <= LOAD; else - dissect_next_state <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; end if; when LOAD => - state <= x"4"; - if (ff_q(8) = '1') and (ff_rd_lock = '0') then - dissect_next_state <= CLEANUP; + state <= x"3"; + if( (ff_q(8) = '1') and (ff_rd_lock = '0') ) then + DISSECT_NS <= CLEANUP; else - dissect_next_state <= LOAD; + DISSECT_NS <= LOAD; end if; when CLEANUP => - state <= x"5"; - dissect_next_state <= IDLE; + state <= x"4"; + DISSECT_NS <= IDLE; + when others => + state <= x"f"; + DISSECT_NS <= IDLE; + end case; end process PROC_DISSECT_TRANSITIONS; - PS_BUSY_OUT <= '0' when dissect_current_state = IDLE else '1'; + PS_BUSY_OUT <= '0' when DISSECT_CS = IDLE else '1'; ff_wr_en <= '1' when (FWD_DATA_VALID_IN = '1') else '0'; - local_eop <= '1' when (dissect_current_state = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0'; + local_eop <= '1' when (DISSECT_CS = SAVE and FWD_EOP_IN = '1' and FWD_DATA_VALID_IN = '1') else '0'; PROC_FF_RD_LOCK: process( CLK, RESET ) begin if ( RESET = '1' ) then ff_rd_lock <= '1'; elsif( rising_edge(CLK) ) then - if( dissect_current_state = LOAD and ff_rd_en = '1' ) then + if( DISSECT_CS = LOAD and ff_rd_en = '1' ) then ff_rd_lock <= '0'; else ff_rd_lock <= '1'; @@ -168,7 +172,7 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F TC_DATA_OUT <= ff_q when rising_edge(CLK); - PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = LOAD) else '0'; + PS_RESPONSE_READY_OUT <= '1' when (DISSECT_CS = LOAD) else '0'; TC_FRAME_SIZE_OUT <= resp_bytes_ctr; TC_FRAME_TYPE_OUT <= x"0008"; @@ -186,15 +190,15 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F if ( RESET = '1' ) then resp_bytes_ctr <= (others => '0'); elsif( rising_edge(CLK) ) then - if ( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then resp_bytes_ctr <= (others => '0'); - elsif( dissect_current_state = SAVE and FWD_DATA_VALID_IN = '1' ) then + elsif( DISSECT_CS = SAVE and FWD_DATA_VALID_IN = '1' ) then resp_bytes_ctr <= resp_bytes_ctr + x"1"; end if; FWD_FULL_OUT <= ff_full; - if( dissect_current_state = IDLE ) then + if( DISSECT_CS = IDLE ) then FWD_READY_OUT <= '1'; else FWD_READY_OUT <= '0'; @@ -208,7 +212,7 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F if ( RESET = '1' ) then rec_frames <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then + if( DISSECT_CS = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then rec_frames <= rec_frames + x"1"; end if; end if; @@ -219,7 +223,7 @@ architecture gbe_response_constructor_Forward_arch of gbe_response_constructor_F if ( RESET = '1' ) then sent_frames <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = WAIT_FOR_LOAD and PS_SELECTED_IN = '0' ) then + if( DISSECT_CS = WAIT_FOR_LOAD and PS_SELECTED_IN = '0' ) then sent_frames <= sent_frames + x"1"; end if; end if; diff --git a/gbe_trb/protocols/gbe_response_constructor_Ping.vhd b/gbe_trb/protocols/gbe_response_constructor_Ping.vhd index 2165d00..6101005 100644 --- a/gbe_trb/protocols/gbe_response_constructor_Ping.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_Ping.vhd @@ -3,7 +3,7 @@ library ieee; use ieee.numeric_std.all; library work; - use work.gbe_protocols.all; +-- use work.gbe_protocols.all; -- BUG: answers always with PING REPLY. No choice on TYPE/CODE is made! @@ -46,13 +46,9 @@ architecture gbe_response_constructor_Ping_arch of gbe_response_constructor_Ping attribute syn_encoding : string; - type dissect_states is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); - signal dissect_current_state, dissect_next_state : dissect_states; - attribute syn_encoding of dissect_current_state: signal is "onehot"; - - type stats_states is (IDLE, LOAD_SENT, LOAD_RECEIVED, CLEANUP); - signal stats_current_state, stats_next_state : stats_states; - attribute syn_encoding of stats_current_state : signal is "onehot"; + type DISSECT_STATES is (IDLE, READ_FRAME, WAIT_FOR_LOAD, LOAD_FRAME, CLEANUP); + signal DISSECT_CS, DISSECT_NS : DISSECT_STATES; + attribute syn_encoding of DISSECT_CS: signal is "onehot"; signal state : std_logic_vector(3 downto 0); @@ -79,47 +75,56 @@ begin PROC_DISSECT_FSM: process( CLK, RESET ) begin if ( RESET = '1' ) then - dissect_current_state <= IDLE; + DISSECT_CS <= IDLE; elsif( rising_edge(CLK) ) then - dissect_current_state <= dissect_next_state; + DISSECT_CS <= DISSECT_NS; end if; end process PROC_DISSECT_FSM; - PROC_DISSECT_TRANSITIONS: process( dissect_current_state, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length ) + PROC_DISSECT_TRANSITIONS: process( DISSECT_CS, PS_WR_EN_IN, PS_SELECTED_IN, PS_ACTIVATE_IN, PS_DATA_IN, data_ctr, data_length ) begin - case dissect_current_state is + case DISSECT_CS is when IDLE => + state <= x"0"; if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then - dissect_next_state <= READ_FRAME; + DISSECT_NS <= READ_FRAME; else - dissect_next_state <= IDLE; + DISSECT_NS <= IDLE; end if; when READ_FRAME => + state <= x"1"; if( PS_DATA_IN(8) = '1' ) then - dissect_next_state <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; else - dissect_next_state <= READ_FRAME; + DISSECT_NS <= READ_FRAME; end if; when WAIT_FOR_LOAD => + state <= x"2"; if( PS_SELECTED_IN = '1' ) then - dissect_next_state <= LOAD_FRAME; + DISSECT_NS <= LOAD_FRAME; else - dissect_next_state <= WAIT_FOR_LOAD; + DISSECT_NS <= WAIT_FOR_LOAD; end if; when LOAD_FRAME => + state <= x"3"; if( data_ctr = data_length + 1 ) then - dissect_next_state <= CLEANUP; + DISSECT_NS <= CLEANUP; else - dissect_next_state <= LOAD_FRAME; + DISSECT_NS <= LOAD_FRAME; end if; when CLEANUP => - dissect_next_state <= IDLE; + state <= x"4"; + DISSECT_NS <= IDLE; + when others => + state <= x"f"; + DISSECT_NS <= IDLE; + end case; end process PROC_DISSECT_TRANSITIONS; @@ -128,11 +133,11 @@ begin if ( RESET = '1' ) then data_ctr <= 2; elsif( rising_edge(CLK) ) then - if ( (dissect_current_state = IDLE) or (dissect_current_state = WAIT_FOR_LOAD) ) then + if ( (DISSECT_CS = IDLE) or (DISSECT_CS = WAIT_FOR_LOAD) ) then data_ctr <= 2; - elsif( (dissect_current_state = READ_FRAME) and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then -- in case of saving data from incoming frame + elsif( (DISSECT_CS = READ_FRAME) and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then -- in case of saving data from incoming frame data_ctr <= data_ctr + 1; - elsif( (dissect_current_state = LOAD_FRAME) and (PS_SELECTED_IN = '1') and (TC_RD_EN_IN = '1') ) then -- in case of constructing response + elsif( (DISSECT_CS = LOAD_FRAME) and (PS_SELECTED_IN = '1') and (TC_RD_EN_IN = '1') ) then -- in case of constructing response data_ctr <= data_ctr + 1; end if; end if; @@ -143,7 +148,7 @@ begin if ( RESET = '1' ) then data_length <= 1; elsif( rising_edge(CLK) ) then - if (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then + if( (DISSECT_CS = READ_FRAME) and (PS_DATA_IN(8) = '1') ) then data_length <= data_ctr; end if; end if; @@ -155,18 +160,18 @@ begin saved_headers <= (others => '0'); saved_data <= (others => '0'); elsif( rising_edge(CLK) ) then - if ( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then saved_headers <= (others => '0'); saved_data <= (others => '0'); - elsif( dissect_current_state = IDLE and PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' ) then + elsif( (DISSECT_CS = IDLE) and (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then saved_headers(7 downto 0) <= PS_DATA_IN(7 downto 0); - elsif( dissect_current_state = READ_FRAME ) then - if (data_ctr < 9) then -- headers + elsif( DISSECT_CS = READ_FRAME ) then + if ( data_ctr < 9 ) then -- headers saved_headers(data_ctr * 8 - 1 downto (data_ctr - 1) * 8) <= PS_DATA_IN(7 downto 0); - elsif (data_ctr > 8) then -- data + elsif( data_ctr > 8 ) then -- data saved_data((data_ctr - 8) * 8 - 1 downto (data_ctr - 8 - 1) * 8) <= PS_DATA_IN(7 downto 0); end if; - elsif( dissect_current_state = LOAD_FRAME ) then + elsif( DISSECT_CS = LOAD_FRAME ) then saved_headers(7 downto 0) <= x"00"; saved_headers(23 downto 16) <= checksum(7 downto 0); saved_headers(31 downto 24) <= checksum(15 downto 8); @@ -184,14 +189,14 @@ begin checksum_lll(15 downto 0) <= (others => '0'); checksum_rrr(15 downto 0) <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = IDLE ) then + if ( DISSECT_CS = IDLE ) then checksum_l(19 downto 0) <= (others => '0'); checksum_r(19 downto 0) <= (others => '0'); checksum_ll(15 downto 0) <= (others => '0'); checksum_rr(15 downto 0) <= (others => '0'); checksum_lll(15 downto 0) <= (others => '0'); checksum_rrr(15 downto 0) <= (others => '0'); - elsif( (dissect_current_state = READ_FRAME) and (data_ctr > 4) ) then + elsif( (DISSECT_CS = READ_FRAME) and (data_ctr > 4) ) then if (std_logic_vector(to_unsigned(data_ctr, 1)) = "0") then checksum_l <= checksum_l + unsigned(PS_DATA_IN(7 downto 0)); else @@ -201,14 +206,14 @@ begin checksum_lll <= checksum_lll; checksum_rr <= checksum_rr; checksum_rrr <= checksum_rrr; - elsif( dissect_current_state = WAIT_FOR_LOAD ) then + elsif( DISSECT_CS = WAIT_FOR_LOAD ) then checksum_ll <= x"0000" + checksum_l(7 downto 0) + checksum_r(19 downto 8); checksum_rr <= x"0000" + checksum_r(7 downto 0) + checksum_l(19 downto 8); checksum_l <= checksum_l; checksum_lll <= checksum_lll; checksum_r <= checksum_r; checksum_rrr <= checksum_rrr; - elsif( dissect_current_state = LOAD_FRAME and data_ctr = 2 ) then + elsif( DISSECT_CS = LOAD_FRAME and data_ctr = 2 ) then checksum_lll <= x"0000" + checksum_ll(7 downto 0) + checksum_rr(15 downto 8); checksum_rrr <= x"0000" + checksum_rr(7 downto 0) + checksum_ll(15 downto 8); checksum_l <= checksum_l; @@ -227,7 +232,7 @@ begin if( rising_edge(CLK) ) then tc_data(8) <= '0'; - if( dissect_current_state = LOAD_FRAME ) then + if( DISSECT_CS = LOAD_FRAME ) then if (data_ctr < 10) then -- headers for i in 0 to 7 loop tc_data(i) <= saved_headers((data_ctr - 2) * 8 + i); @@ -254,13 +259,13 @@ begin PROC_PS_RESPONSE_SYNC: process( CLK ) begin if( rising_edge(CLK) ) then - if( (dissect_current_state = WAIT_FOR_LOAD) or (dissect_current_state = LOAD_FRAME) or (dissect_current_state = CLEANUP) ) then + if( (DISSECT_CS = WAIT_FOR_LOAD) or (DISSECT_CS = LOAD_FRAME) or (DISSECT_CS = CLEANUP) ) then PS_RESPONSE_READY_OUT <= '1'; else PS_RESPONSE_READY_OUT <= '0'; end if; - if( dissect_current_state = IDLE ) then + if( DISSECT_CS = IDLE ) then PS_BUSY_OUT <= '0'; else PS_BUSY_OUT <= '1'; @@ -280,7 +285,7 @@ begin PROC_ADDR: process( CLK ) begin if( rising_edge(CLK) ) then - if( dissect_current_state = READ_FRAME ) then + if( DISSECT_CS = READ_FRAME ) then TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; end if; @@ -292,12 +297,10 @@ begin if ( RESET = '1' ) then sent_frames <= (others => '0'); elsif( rising_edge(CLK) ) then - if( dissect_current_state = CLEANUP ) then + if( DISSECT_CS = CLEANUP ) then sent_frames <= sent_frames + 1; end if; end if; end process PROC_SENT_FRAMES; end gbe_response_constructor_Ping_arch; - - diff --git a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd index 50145c2..edf528a 100644 --- a/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd +++ b/gbe_trb/protocols/gbe_response_constructor_SCTRL.vhd @@ -4,7 +4,7 @@ library ieee; library work; use work.trb_net_std.all; - use work.gbe_protocols.all; +-- use work.gbe_protocols.all; entity gbe_response_constructor_SCTRL is generic( @@ -122,8 +122,8 @@ architecture gbe_response_constructor_SCTRL_arch of gbe_response_constructor_SCT signal tx_cnt : std_logic_vector(15 downto 0); -- TO BE REMOVED LATER. - signal delay_ctr : unsigned(13 downto 0); - signal delay_done : std_logic; +-- signal delay_ctr : unsigned(13 downto 0); +-- signal delay_done : std_logic; -- TEST signal saved_dst_mac : std_logic_vector(47 downto 0); @@ -243,7 +243,7 @@ begin PROC_PACKET_NUM: process( CLK ) begin if( rising_edge(CLK) ) then - if( DISSECT_CS = IDLE ) then + if ( DISSECT_CS = IDLE ) then packet_num <= "100"; elsif( (GSC_INIT_READ_IN = '1') and (rx_fifo_rd = '1') and (packet_num = "100") and (DISSECT_CS /= READ_FRAME) ) then -- JM: BUG zaehlt schon hoch beim fifo_rd weil read schon 1 ist. read geht aber nur auf 1 wenn dataready auf 1 ist @@ -378,7 +378,7 @@ begin TX_LOADED_CTR_PROC: process( CLK ) begin if( rising_edge(CLK) ) then - if( DISSECT_CS = IDLE ) then + if ( DISSECT_CS = IDLE ) then tx_loaded_ctr <= x"0000"; elsif( (DISSECT_CS = LOAD_FRAME) and (PS_SELECTED_IN = '1') and (TC_RD_EN_IN = '1') ) then tx_loaded_ctr <= tx_loaded_ctr + 1; @@ -406,19 +406,15 @@ begin end process PS_RESPONSE_SYNC; TC_FRAME_TYPE_OUT <= x"0008"; -- byte swapped --- TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; TC_DEST_MAC_OUT <= saved_dst_mac; TC_DEST_IP_OUT <= PS_SRC_IP_ADDRESS_IN; TC_DEST_UDP_OUT <= PS_SRC_UDP_PORT_IN; --- TC_DEST_UDP_OUT(7 downto 0) <= PS_SRC_UDP_PORT_IN(15 downto 8); --- TC_DEST_UDP_OUT(15 downto 8) <= PS_SRC_UDP_PORT_IN(7 downto 0); TC_SRC_MAC_OUT <= MY_MAC_IN; TC_SRC_IP_OUT <= MY_IP_IN; TC_SRC_UDP_OUT <= x"9065"; -- byte swapped TC_IP_PROTOCOL_OUT <= x"11"; TC_IDENT_OUT <= x"3" & std_logic_vector(reply_ctr(11 downto 0)); - - TC_FRAME_SIZE_OUT <= std_logic_vector(tx_data_ctr); + TC_FRAME_SIZE_OUT <= std_logic_vector(tx_data_ctr); DISSECT_MACHINE_PROC: process( CLK, RESET ) begin @@ -433,15 +429,14 @@ begin DISSECT_MACHINE: process( DISSECT_CS, reset_detected, too_much_data, PS_WR_EN_IN, PS_ACTIVATE_IN, PS_DATA_IN, PS_SELECTED_IN, GSC_INIT_READ_IN, GSC_REPLY_DATAREADY_IN, tx_loaded_ctr, - tx_data_ctr, rx_fifo_q, GSC_BUSY_IN, delay_done ) + tx_data_ctr, rx_fifo_q, GSC_BUSY_IN ) begin - state <= x"0"; store_mac_x <= '0'; case DISSECT_CS is when IDLE => - state <= x"1"; + state <= x"0"; if( (PS_WR_EN_IN = '1') and (PS_ACTIVATE_IN = '1') ) then DISSECT_NS <= READ_FRAME; store_mac_x <= '1'; @@ -450,7 +445,7 @@ begin end if; when READ_FRAME => - state <= x"2"; + state <= x"1"; if ( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '0') ) then DISSECT_NS <= WAIT_FOR_HUB; elsif( (PS_DATA_IN(8) = '1') and (GSC_INIT_READ_IN = '1') ) then @@ -460,7 +455,7 @@ begin end if; when WAIT_FOR_HUB => - state <= x"3"; + state <= x"2"; if( GSC_INIT_READ_IN = '1' ) then DISSECT_NS <= LOAD_TO_HUB; else @@ -468,7 +463,7 @@ begin end if; when LOAD_TO_HUB => - state <= x"4"; + state <= x"3"; if( (rx_fifo_q(17) = '1') and (GSC_INIT_READ_IN = '1') ) then if( reset_detected = '1' ) then DISSECT_NS <= CLEANUP; @@ -480,7 +475,7 @@ begin end if; when WAIT_FOR_RESPONSE => - state <= x"5"; + state <= x"4"; if( GSC_REPLY_DATAREADY_IN = '1' ) then DISSECT_NS <= SAVE_RESPONSE; else @@ -488,7 +483,7 @@ begin end if; when SAVE_RESPONSE => - state <= x"6"; + state <= x"5"; if( (GSC_REPLY_DATAREADY_IN = '0') and (GSC_BUSY_IN = '0') ) then if( too_much_data = '0' ) then -- DISSECT_NS <= WAIT_FOR_LOAD; @@ -501,12 +496,12 @@ begin end if; when DELAY => - state <= x"a"; - if( delay_done = '1' ) then + state <= x"6"; +-- if( delay_done = '1' ) then DISSECT_NS <= WAIT_FOR_LOAD; - else - DISSECT_NS <= DELAY; - end if; +-- else +-- DISSECT_NS <= DELAY; +-- end if; when WAIT_FOR_LOAD => state <= x"7"; @@ -528,25 +523,27 @@ begin state <= x"9"; DISSECT_NS <= IDLE; - when others => DISSECT_NS <= IDLE; + when others => + state <= x"f"; + DISSECT_NS <= IDLE; end case; end process DISSECT_MACHINE; - -- JUST FOR TESTING. TO BE REMOVED. - PROC_DELAY_CTR: process( CLK ) - begin - if( rising_edge(CLK) ) then - if( DISSECT_CS /= DELAY ) then - delay_ctr <= (others => '0'); - else - delay_ctr <= delay_ctr + 1; - end if; - end if; - end process PROC_DELAY_CTR; +-- -- JUST FOR TESTING. TO BE REMOVED. +-- PROC_DELAY_CTR: process( CLK ) +-- begin +-- if( rising_edge(CLK) ) then +-- if( DISSECT_CS /= DELAY ) then +-- delay_ctr <= (others => '0'); +-- else +-- delay_ctr <= delay_ctr + 1; +-- end if; +-- end if; +-- end process PROC_DELAY_CTR; -- delay_done <= std_logic(delay_ctr(13)); - delay_done <= std_logic(delay_ctr(4)); +-- delay_done <= std_logic(delay_ctr(4)); -- reset request packet detection RESET_DETECTED_PROC: process( CLK ) diff --git a/special/spi_databus_memory.vhd b/special/spi_databus_memory.vhd index d392bfd..6403213 100644 --- a/special/spi_databus_memory.vhd +++ b/special/spi_databus_memory.vhd @@ -1,11 +1,11 @@ library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity spi_databus_memory is port( @@ -49,107 +49,107 @@ architecture Behavioral of spi_databus_memory is begin ---------------------------------------------------------- --- Debugging -- ---------------------------------------------------------- -stat(63 downto 0) <= (others => '0'); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- -STATE_MEM: process( CLK_IN ) -begin - if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - CURRENT_STATE <= SLEEP; - bus_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - bus_ack <= bus_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; - end if; - end if; -end process STATE_MEM; - --- Transition matrix -TRANSFORM: process(CURRENT_STATE, BUS_READ_IN, BUS_WRITE_IN ) -begin - NEXT_STATE <= SLEEP; - bus_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => - if ( (BUS_READ_IN = '1') ) then - NEXT_STATE <= RD_RDY; - store_rd_x <= '1'; - elsif( (BUS_WRITE_IN = '1') ) then - NEXT_STATE <= WR_RDY; - store_wr_x <= '1'; + --------------------------------------------------------- + -- Debugging -- + --------------------------------------------------------- + stat(63 downto 0) <= (others => '0'); + + --------------------------------------------------------- + -- Statemachine -- + --------------------------------------------------------- + STATE_MEM: process( CLK_IN ) + begin + if( rising_edge(CLK_IN) ) then + if( RESET_IN = '1' ) then + CURRENT_STATE <= SLEEP; + bus_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; else - NEXT_STATE <= SLEEP; + CURRENT_STATE <= NEXT_STATE; + bus_ack <= bus_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; end if; - - when RD_RDY => - NEXT_STATE <= RD_ACK; - - when WR_RDY => - NEXT_STATE <= WR_ACK; - - when RD_ACK => - if( BUS_READ_IN = '0' ) then - NEXT_STATE <= DONE; - bus_ack_x <= '1'; - else + end if; + end process STATE_MEM; + + -- Transition matrix + TRANSFORM: process(CURRENT_STATE, BUS_READ_IN, BUS_WRITE_IN ) + begin + NEXT_STATE <= SLEEP; + bus_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => + if ( (BUS_READ_IN = '1') ) then + NEXT_STATE <= RD_RDY; + store_rd_x <= '1'; + elsif( (BUS_WRITE_IN = '1') ) then + NEXT_STATE <= WR_RDY; + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + + when RD_RDY => NEXT_STATE <= RD_ACK; - bus_ack_x <= '1'; - end if; - when WR_ACK => - if( BUS_WRITE_IN = '0' ) then - NEXT_STATE <= DONE; - bus_ack_x <= '1'; - else + when WR_RDY => NEXT_STATE <= WR_ACK; - bus_ack_x <= '1'; - end if; - when DONE => - NEXT_STATE <= SLEEP; - - when others => - NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - -THE_BUS_SPI_DPRAM: spi_dpram_32_to_8 -port map( - DATAINA => BUS_DATA_IN, - ADDRESSA => BUS_ADDR_IN, - CLOCKA => CLK_IN, - CLOCKENA => '1', - WRA => store_wr, - RESETA => RESET_IN, - QA => buf_bus_data_out, - -- B side is state machine - DATAINB => BRAM_RD_D_IN, - ADDRESSB => BRAM_ADDR_IN, - CLOCKB => CLK_IN, - CLOCKENB => '1', - WRB => BRAM_WE_IN, - RESETB => RESET_IN, - QB => BRAM_WR_D_OUT -); - --- output signals -BUS_DATA_OUT <= buf_bus_data_out; -BUS_ACK_OUT <= bus_ack; + when RD_ACK => + if( BUS_READ_IN = '0' ) then + NEXT_STATE <= DONE; + bus_ack_x <= '1'; + else + NEXT_STATE <= RD_ACK; + bus_ack_x <= '1'; + end if; + + when WR_ACK => + if( BUS_WRITE_IN = '0' ) then + NEXT_STATE <= DONE; + bus_ack_x <= '1'; + else + NEXT_STATE <= WR_ACK; + bus_ack_x <= '1'; + end if; + + when DONE => + NEXT_STATE <= SLEEP; + + when others => + NEXT_STATE <= SLEEP; + end case; + end process TRANSFORM; + + --------------------------------------------------------- + -- data handling -- + --------------------------------------------------------- + + THE_BUS_SPI_DPRAM: entity spi_dpram_32_to_8 + port map( + DATAINA => BUS_DATA_IN, + ADDRESSA => BUS_ADDR_IN, + CLOCKA => CLK_IN, + CLOCKENA => '1', + WRA => store_wr, + RESETA => RESET_IN, + QA => buf_bus_data_out, + -- B side is state machine + DATAINB => BRAM_RD_D_IN, + ADDRESSB => BRAM_ADDR_IN, + CLOCKB => CLK_IN, + CLOCKENB => '1', + WRB => BRAM_WE_IN, + RESETB => RESET_IN, + QB => BRAM_WR_D_OUT + ); + + -- output signals + BUS_DATA_OUT <= buf_bus_data_out; + BUS_ACK_OUT <= bus_ack; end Behavioral; diff --git a/special/spi_flash_and_fpga_reload_record.vhd b/special/spi_flash_and_fpga_reload_record.vhd index 96c1250..b9d73ff 100644 --- a/special/spi_flash_and_fpga_reload_record.vhd +++ b/special/spi_flash_and_fpga_reload_record.vhd @@ -1,11 +1,10 @@ - -LIBRARY ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity spi_flash_and_fpga_reload_record is @@ -56,127 +55,127 @@ architecture flash_reboot_arch of spi_flash_and_fpga_reload_record is begin -BUS_TX.ack <= dat_dataready or dat_write_ack; - -THE_BUS_HANDLER : trb_net16_regio_bus_handler - generic map( - PORT_NUMBER => 2, - PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"), - PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) - ) - port map( - CLK => CLK_IN, - RESET => RESET_IN, - - DAT_ADDR_IN(8 downto 0) => BUS_RX.addr(8 downto 0), - DAT_ADDR_IN(15 downto 9)=>(others => '0'), - DAT_DATA_IN => BUS_RX.data, - DAT_DATA_OUT => BUS_TX.data, - DAT_READ_ENABLE_IN => BUS_RX.read, - DAT_WRITE_ENABLE_IN => BUS_RX.write, - DAT_TIMEOUT_IN => '0', - DAT_DATAREADY_OUT => dat_dataready, - DAT_WRITE_ACK_OUT => dat_write_ack, - DAT_NO_MORE_DATA_OUT => BUS_TX.nack, - DAT_UNKNOWN_ADDR_OUT => BUS_TX.unknown, - - --Bus Handler (SPI CTRL) - --Bus Handler (SPI Memory) - BUS_READ_ENABLE_OUT(0) => spictrl_read_en, - BUS_READ_ENABLE_OUT(1) => spimem_read_en, - BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, - BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, - BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, - BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, - BUS_ADDR_OUT(0*16) => spictrl_addr, - BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, - BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, - BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, - BUS_TIMEOUT_OUT(0) => open, - BUS_TIMEOUT_OUT(1) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, - BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, - BUS_DATAREADY_IN(0) => spictrl_ack, - BUS_DATAREADY_IN(1) => spimem_ack, - BUS_WRITE_ACK_IN(0) => spictrl_ack, - BUS_WRITE_ACK_IN(1) => spimem_ack, - BUS_NO_MORE_DATA_IN(0) => spictrl_busy, - BUS_NO_MORE_DATA_IN(1) => '0', - BUS_UNKNOWN_ADDR_IN(0) => '0', - BUS_UNKNOWN_ADDR_IN(1) => '0', + BUS_TX.ack <= dat_dataready or dat_write_ack; + + THE_BUS_HANDLER: entity trb_net16_regio_bus_handler + generic map( + PORT_NUMBER => 2, + PORT_ADDRESSES => (0 => x"0000", 1 => x"0100", others => x"0000"), + PORT_ADDR_MASK => (0 => 1, 1 => 6, others => 0) + ) + port map( + CLK => CLK_IN, + RESET => RESET_IN, + + DAT_ADDR_IN(8 downto 0) => BUS_RX.addr(8 downto 0), + DAT_ADDR_IN(15 downto 9)=>(others => '0'), + DAT_DATA_IN => BUS_RX.data, + DAT_DATA_OUT => BUS_TX.data, + DAT_READ_ENABLE_IN => BUS_RX.read, + DAT_WRITE_ENABLE_IN => BUS_RX.write, + DAT_TIMEOUT_IN => '0', + DAT_DATAREADY_OUT => dat_dataready, + DAT_WRITE_ACK_OUT => dat_write_ack, + DAT_NO_MORE_DATA_OUT => BUS_TX.nack, + DAT_UNKNOWN_ADDR_OUT => BUS_TX.unknown, + + --Bus Handler (SPI CTRL) + --Bus Handler (SPI Memory) + BUS_READ_ENABLE_OUT(0) => spictrl_read_en, + BUS_READ_ENABLE_OUT(1) => spimem_read_en, + BUS_WRITE_ENABLE_OUT(0) => spictrl_write_en, + BUS_WRITE_ENABLE_OUT(1) => spimem_write_en, + BUS_DATA_OUT(0*32+31 downto 0*32) => spictrl_data_in, + BUS_DATA_OUT(1*32+31 downto 1*32) => spimem_data_in, + BUS_ADDR_OUT(0*16) => spictrl_addr, + BUS_ADDR_OUT(0*16+15 downto 0*16+1) => open, + BUS_ADDR_OUT(1*16+5 downto 1*16) => spimem_addr, + BUS_ADDR_OUT(1*16+15 downto 1*16+6) => open, + BUS_TIMEOUT_OUT(0) => open, + BUS_TIMEOUT_OUT(1) => open, + BUS_DATA_IN(0*32+31 downto 0*32) => spictrl_data_out, + BUS_DATA_IN(1*32+31 downto 1*32) => spimem_data_out, + BUS_DATAREADY_IN(0) => spictrl_ack, + BUS_DATAREADY_IN(1) => spimem_ack, + BUS_WRITE_ACK_IN(0) => spictrl_ack, + BUS_WRITE_ACK_IN(1) => spimem_ack, + BUS_NO_MORE_DATA_IN(0) => spictrl_busy, + BUS_NO_MORE_DATA_IN(1) => '0', + BUS_UNKNOWN_ADDR_IN(0) => '0', + BUS_UNKNOWN_ADDR_IN(1) => '0', + + STAT_DEBUG => open + ); + + + THE_SPI_MASTER: entity spi_master + port map( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + -- Slave bus + BUS_READ_IN => spictrl_read_en, + BUS_WRITE_IN => spictrl_write_en, + BUS_BUSY_OUT => spictrl_busy, + BUS_ACK_OUT => spictrl_ack, + BUS_ADDR_IN(0) => spictrl_addr, + BUS_DATA_IN => spictrl_data_in, + BUS_DATA_OUT => spictrl_data_out, + -- SPI connections + SPI_CS_OUT => SPI_CS_OUT, + SPI_SDI_IN => SPI_SDI_IN, + SPI_SDO_OUT => SPI_SDO_OUT, + SPI_SCK_OUT => SPI_SCK_OUT, + -- BRAM for read/write data + BRAM_A_OUT => spi_bram_addr, + BRAM_WR_D_IN => spi_bram_wr_d, + BRAM_RD_D_OUT => spi_bram_rd_d, + BRAM_WE_OUT => spi_bram_we, + -- Status lines + STAT => spi_debug --open + ); + + DEBUG_OUT(0) <= spictrl_read_en; + DEBUG_OUT(1) <= spictrl_write_en; + DEBUG_OUT(2) <= spictrl_ack; + DEBUG_OUT(3) <= spictrl_busy; + DEBUG_OUT(4) <= spimem_read_en; + DEBUG_OUT(5) <= spimem_write_en; + DEBUG_OUT(6) <= spimem_ack; + DEBUG_OUT(7) <= spi_debug(0); -- spi_start + DEBUG_OUT(8) <= spi_debug(1); -- spi_busy + + DEBUG_OUT(31 downto 9) <= (others => '0'); - STAT_DEBUG => open - ); - - -THE_SPI_MASTER: spi_master - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - -- Slave bus - BUS_READ_IN => spictrl_read_en, - BUS_WRITE_IN => spictrl_write_en, - BUS_BUSY_OUT => spictrl_busy, - BUS_ACK_OUT => spictrl_ack, - BUS_ADDR_IN(0) => spictrl_addr, - BUS_DATA_IN => spictrl_data_in, - BUS_DATA_OUT => spictrl_data_out, - -- SPI connections - SPI_CS_OUT => SPI_CS_OUT, - SPI_SDI_IN => SPI_SDI_IN, - SPI_SDO_OUT => SPI_SDO_OUT, - SPI_SCK_OUT => SPI_SCK_OUT, - -- BRAM for read/write data - BRAM_A_OUT => spi_bram_addr, - BRAM_WR_D_IN => spi_bram_wr_d, - BRAM_RD_D_OUT => spi_bram_rd_d, - BRAM_WE_OUT => spi_bram_we, - -- Status lines - STAT => spi_debug --open - ); - - DEBUG_OUT(0) <= spictrl_read_en; - DEBUG_OUT(1) <= spictrl_write_en; - DEBUG_OUT(2) <= spictrl_ack; - DEBUG_OUT(3) <= spictrl_busy; - DEBUG_OUT(4) <= spimem_read_en; - DEBUG_OUT(5) <= spimem_write_en; - DEBUG_OUT(6) <= spimem_ack; - DEBUG_OUT(7) <= spi_debug(0); -- spi_start - DEBUG_OUT(8) <= spi_debug(1); -- spi_busy - - DEBUG_OUT(31 downto 9) <= (others => '0'); - --- data memory for SPI accesses -THE_SPI_MEMORY: spi_databus_memory - port map( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - -- Slave bus - BUS_ADDR_IN => spimem_addr, - BUS_READ_IN => spimem_read_en, - BUS_WRITE_IN => spimem_write_en, - BUS_ACK_OUT => spimem_ack, - BUS_DATA_IN => spimem_data_in, - BUS_DATA_OUT => spimem_data_out, - -- state machine connections - BRAM_ADDR_IN => spi_bram_addr, - BRAM_WR_D_OUT => spi_bram_wr_d, - BRAM_RD_D_IN => spi_bram_rd_d, - BRAM_WE_IN => spi_bram_we, - -- Status lines - STAT => open - ); - ---------------------------------------------------------------------------- --- Reboot FPGA ---------------------------------------------------------------------------- -THE_FPGA_REBOOT : fpga_reboot - port map( - CLK => CLK_IN, - RESET => RESET_IN, - DO_REBOOT => DO_REBOOT_IN, - PROGRAMN => PROGRAMN - ); + -- data memory for SPI accesses + THE_SPI_MEMORY: entity spi_databus_memory + port map( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + -- Slave bus + BUS_ADDR_IN => spimem_addr, + BUS_READ_IN => spimem_read_en, + BUS_WRITE_IN => spimem_write_en, + BUS_ACK_OUT => spimem_ack, + BUS_DATA_IN => spimem_data_in, + BUS_DATA_OUT => spimem_data_out, + -- state machine connections + BRAM_ADDR_IN => spi_bram_addr, + BRAM_WR_D_OUT => spi_bram_wr_d, + BRAM_RD_D_IN => spi_bram_rd_d, + BRAM_WE_IN => spi_bram_we, + -- Status lines + STAT => open + ); + + --------------------------------------------------------------------------- + -- Reboot FPGA + --------------------------------------------------------------------------- + THE_FPGA_REBOOT: entity fpga_reboot + port map( + CLK => CLK_IN, + RESET => RESET_IN, + DO_REBOOT => DO_REBOOT_IN, + PROGRAMN => PROGRAMN + ); end architecture; diff --git a/special/spi_master.vhd b/special/spi_master.vhd index 31d6f82..c35df83 100644 --- a/special/spi_master.vhd +++ b/special/spi_master.vhd @@ -1,11 +1,11 @@ library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_ARITH.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity spi_master is port( @@ -77,160 +77,160 @@ architecture Behavioral of spi_master is begin -process(clk_in) + PROC_SYNC: process( clk_in ) begin if rising_edge(clk_in) then reset_i <= reset_in; end if; - end process; - ---------------------------------------------------------- --- SPI master -- ---------------------------------------------------------- - -THE_SPI_SLIM: spi_slim -port map( - SYSCLK => clk_in, - RESET => reset_i, - -- Command interface - START_IN => spi_start, -- not really nice, but should work - BUSY_OUT => spi_busy, - CMD_IN => reg_ctrl_data(31 downto 24), - ADH_IN => reg_ctrl_data(23 downto 16), - ADM_IN => reg_ctrl_data(15 downto 8), - ADL_IN => reg_ctrl_data(7 downto 0), - MAX_IN => reg_status_data(31 downto 24), - TXDATA_IN => bram_wr_d_in, - TX_RD_OUT => open, -- not needed - RXDATA_OUT => bram_rd_d_out, - RX_WR_OUT => bram_we_out, - TX_RX_A_OUT => bram_a_out, - -- SPI interface - SPI_SCK_OUT => spi_sck_out, - SPI_CS_OUT => spi_cs_out, - SPI_SDI_IN => spi_sdi_in, - SPI_SDO_OUT => spi_sdo_out, - -- DEBUG - CLK_EN_OUT => open, -- not needed - BSM_OUT => spi_bsm, - DEBUG_OUT => spi_debug --open -- BUG -); - ---------------------------------------------------------- --- Statemachine -- ---------------------------------------------------------- -STATE_MEM: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if( reset_i = '1' ) then - CURRENT_STATE <= SLEEP; - bus_busy <= '0'; - bus_ack <= '0'; - store_wr <= '0'; - store_rd <= '0'; - else - CURRENT_STATE <= NEXT_STATE; - bus_busy <= bus_busy_x; - bus_ack <= bus_ack_x; - store_wr <= store_wr_x; - store_rd <= store_rd_x; + end process PROC_SYNC; + + --------------------------------------------------------- + -- SPI master -- + --------------------------------------------------------- + + THE_SPI_SLIM: entity spi_slim + port map( + SYSCLK => clk_in, + RESET => reset_i, + -- Command interface + START_IN => spi_start, -- not really nice, but should work + BUSY_OUT => spi_busy, + CMD_IN => reg_ctrl_data(31 downto 24), + ADH_IN => reg_ctrl_data(23 downto 16), + ADM_IN => reg_ctrl_data(15 downto 8), + ADL_IN => reg_ctrl_data(7 downto 0), + MAX_IN => reg_status_data(31 downto 24), + TXDATA_IN => bram_wr_d_in, + TX_RD_OUT => open, -- not needed + RXDATA_OUT => bram_rd_d_out, + RX_WR_OUT => bram_we_out, + TX_RX_A_OUT => bram_a_out, + -- SPI interface + SPI_SCK_OUT => spi_sck_out, + SPI_CS_OUT => spi_cs_out, + SPI_SDI_IN => spi_sdi_in, + SPI_SDO_OUT => spi_sdo_out, + -- DEBUG + CLK_EN_OUT => open, -- not needed + BSM_OUT => spi_bsm, + DEBUG_OUT => spi_debug --open -- BUG + ); + + --------------------------------------------------------- + -- Statemachine -- + --------------------------------------------------------- + PROC_STATE_MEM: process( clk_in ) + begin + if( rising_edge(clk_in) ) then + if( reset_i = '1' ) then + CURRENT_STATE <= SLEEP; + bus_busy <= '0'; + bus_ack <= '0'; + store_wr <= '0'; + store_rd <= '0'; + else + CURRENT_STATE <= NEXT_STATE; + bus_busy <= bus_busy_x; + bus_ack <= bus_ack_x; + store_wr <= store_wr_x; + store_rd <= store_rd_x; + end if; end if; - end if; -end process STATE_MEM; + end process PROC_STATE_MEM; -TRANSFORM: process(CURRENT_STATE, bus_read_in, bus_write_in, spi_busy, bus_addr_in ) -begin - NEXT_STATE <= SLEEP; - bus_busy_x <= '0'; - bus_ack_x <= '0'; - store_wr_x <= '0'; - store_rd_x <= '0'; - case CURRENT_STATE is - when SLEEP => - if ( (spi_busy = '0') and (bus_read_in = '1') ) then - NEXT_STATE <= DONE; - store_rd_x <= '1'; - elsif( (spi_busy = '0') and (bus_write_in = '1') ) then - NEXT_STATE <= DONE; - store_wr_x <= '1'; - elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then - NEXT_STATE <= SLEEP; -- CMD register is busy protected - bus_busy_x <= '1'; - elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then - NEXT_STATE <= SLEEP; -- CMD register is busy protected - bus_busy_x <= '1'; - elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then - NEXT_STATE <= DONE; -- STATUS register is not - store_rd_x <= '1'; - elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then - NEXT_STATE <= DONE; -- STATUS register is not - store_wr_x <= '1'; + PROC_TRANSFORM: process( CURRENT_STATE, bus_read_in, bus_write_in, spi_busy, bus_addr_in ) + begin + NEXT_STATE <= SLEEP; + bus_busy_x <= '0'; + bus_ack_x <= '0'; + store_wr_x <= '0'; + store_rd_x <= '0'; + case CURRENT_STATE is + when SLEEP => + if ( (spi_busy = '0') and (bus_read_in = '1') ) then + NEXT_STATE <= DONE; + store_rd_x <= '1'; + elsif( (spi_busy = '0') and (bus_write_in = '1') ) then + NEXT_STATE <= DONE; + store_wr_x <= '1'; + elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_read_in = '1') ) then + NEXT_STATE <= SLEEP; -- CMD register is busy protected + bus_busy_x <= '1'; + elsif( (bus_addr_in(0) = '0') and (spi_busy = '1') and (bus_write_in = '1') ) then + NEXT_STATE <= SLEEP; -- CMD register is busy protected + bus_busy_x <= '1'; + elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_read_in = '1') ) then + NEXT_STATE <= DONE; -- STATUS register is not + store_rd_x <= '1'; + elsif( (bus_addr_in(0) = '1') and (spi_busy = '1') and (bus_write_in = '1') ) then + NEXT_STATE <= DONE; -- STATUS register is not + store_wr_x <= '1'; + else + NEXT_STATE <= SLEEP; + end if; + when DONE => + NEXT_STATE <= SLEEP; + bus_ack_x <= '1'; + when others => + NEXT_STATE <= SLEEP; + end case; + end process PROC_TRANSFORM; + + --------------------------------------------------------- + -- data handling -- + --------------------------------------------------------- + + -- register write + PROC_WRITE_REG: process( clk_in ) + begin + if( rising_edge(clk_in) ) then + if ( reset_i = '1' ) then + reg_ctrl_data <= (others => '0'); + reg_status_data <= (others => '0'); + spi_start <= '0'; + elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then + reg_ctrl_data <= bus_data_in; + spi_start <= spi_start_x; + elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then + reg_status_data <= bus_data_in; + spi_start <= spi_start_x; else - NEXT_STATE <= SLEEP; + spi_start <= spi_start_x; end if; - when DONE => - NEXT_STATE <= SLEEP; - bus_ack_x <= '1'; - when others => - NEXT_STATE <= SLEEP; - end case; -end process TRANSFORM; - ---------------------------------------------------------- --- data handling -- ---------------------------------------------------------- - --- register write -THE_WRITE_REG_PROC: process( clk_in ) -begin - if( rising_edge(clk_in) ) then - if ( reset_i = '1' ) then - reg_ctrl_data <= (others => '0'); - reg_status_data <= (others => '0'); - spi_start <= '0'; - elsif( (store_wr = '1') and (bus_addr_in(0) = '0') ) then - reg_ctrl_data <= bus_data_in; - spi_start <= spi_start_x; - elsif( (store_wr = '1') and (bus_addr_in(0) = '1') ) then - reg_status_data <= bus_data_in; - spi_start <= spi_start_x; - else - spi_start <= spi_start_x; end if; - end if; -end process THE_WRITE_REG_PROC; + end process PROC_WRITE_REG; -spi_start_x <= '1' when ( (store_wr = '1') and (bus_addr_in(0) = '0') ) else '0'; + spi_start_x <= '1' when ( (store_wr = '1') and (bus_addr_in(0) = '0') ) else '0'; --- register read -THE_READ_REG_PROC: process( clk_in ) + -- register read + PROC_READ_REG: process( clk_in ) begin - if( rising_edge(clk_in) ) then - if ( reset_i = '1' ) then - reg_bus_data_out <= (others => '0'); - elsif( (store_rd = '1') and (bus_addr_in(0) = '0') ) then - reg_bus_data_out <= reg_ctrl_data; - elsif( (store_rd = '1') and (bus_addr_in(0) = '1') ) then - reg_bus_data_out(31 downto 24) <= reg_status_data(31 downto 24); - reg_bus_data_out(23 downto 16) <= x"00"; - reg_bus_data_out(15 downto 8) <= x"00"; - reg_bus_data_out(7 downto 0) <= spi_bsm; - end if; + if( rising_edge(clk_in) ) then + if ( reset_i = '1' ) then + reg_bus_data_out <= (others => '0'); + elsif( (store_rd = '1') and (bus_addr_in(0) = '0') ) then + reg_bus_data_out <= reg_ctrl_data; + elsif( (store_rd = '1') and (bus_addr_in(0) = '1') ) then + reg_bus_data_out(31 downto 24) <= reg_status_data(31 downto 24); + reg_bus_data_out(23 downto 16) <= x"00"; + reg_bus_data_out(15 downto 8) <= x"00"; + reg_bus_data_out(7 downto 0) <= spi_bsm; end if; - end process THE_READ_REG_PROC; + end if; + end process PROC_READ_REG; --- debug signals -status_data(31 downto 24) <= spi_bsm; -status_data(23) <= spi_start; -status_data(22 downto 0) <= (others => '0'); + -- debug signals + status_data(31 downto 24) <= spi_bsm; + status_data(23) <= spi_start; + status_data(22 downto 0) <= (others => '0'); --- output signals -bus_ack_out <= bus_ack; -bus_busy_out <= bus_busy; -bus_data_out <= reg_bus_data_out; + -- output signals + bus_ack_out <= bus_ack; + bus_busy_out <= bus_busy; + bus_data_out <= reg_bus_data_out; -stat(31 downto 2) <= spi_debug(31 downto 2); -stat(1) <= spi_busy; -stat(0) <= spi_start; + stat(31 downto 2) <= spi_debug(31 downto 2); + stat(1) <= spi_busy; + stat(0) <= spi_start; end Behavioral; diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 991b11a..ce3f0fc 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -1,11 +1,11 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity trb_net16_api_base is generic ( @@ -194,7 +194,7 @@ begin -- termination for active api --------------------------------------- genterm: if API_TYPE = c_API_ACTIVE generate - TrbNetTerm: trb_net16_term + TrbNetTerm: entity trb_net16_term generic map( USE_APL_PORT => 0, SECURE_MODE => 0 @@ -225,7 +225,7 @@ begin --------------------------------------- -- a sbuf (to_int direction) --------------------------------------- - SBUF: trb_net16_sbuf + SBUF: entity trb_net16_sbuf generic map ( VERSION => SBUF_VERSION) port map ( @@ -261,7 +261,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; --------------------------------------- -- a sbuf (to_apl direction) --------------------------------------- - SBUF_TO_APL: trb_net16_sbuf + SBUF_TO_APL: entity trb_net16_sbuf generic map ( VERSION => SBUF_VERSION) port map ( @@ -280,7 +280,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; STAT_BUFFER => sbuf_status(1) ); - SBUF_TO_APL2: trb_net_sbuf + SBUF_TO_APL2: entity trb_net_sbuf generic map ( VERSION => SBUF_VERSION, DATA_WIDTH => 3) @@ -400,7 +400,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; -- fifo to apl --------------------------------------- - FIFO_TO_APL: trb_net16_fifo + FIFO_TO_APL: entity trb_net16_fifo generic map ( DEPTH => FIFO_TO_APL_DEPTH, USE_VENDOR_CORES => USE_VENDOR_CORES) @@ -478,7 +478,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; --------------------------------------- GEN_FIFO_TO_INT: if FIFO_TO_INT_DEPTH >0 generate - FIFO_TO_INT: trb_net16_fifo + FIFO_TO_INT: entity trb_net16_fifo generic map ( DEPTH => FIFO_TO_INT_DEPTH, USE_VENDOR_CORES => USE_VENDOR_CORES) @@ -498,7 +498,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; end generate; GEN_DUMMY_FIFO_TO_INT: if FIFO_TO_INT_DEPTH =0 generate - FIFO_TO_INT: trb_net16_dummy_fifo + FIFO_TO_INT: entity trb_net16_dummy_fifo port map ( CLK => CLK, RESET => RESET, diff --git a/trb_net16_endpoint_standalone_sctrl.vhd b/trb_net16_endpoint_standalone_sctrl.vhd index e186f7c..e2082b1 100644 --- a/trb_net16_endpoint_standalone_sctrl.vhd +++ b/trb_net16_endpoint_standalone_sctrl.vhd @@ -1,13 +1,13 @@ -- endpoint for stand-along GbE with only slow control library ieee; -use ieee.std_logic_1164.all; -use ieee.numeric_std.all; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.config.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; + use work.config.all; entity trb_net16_endpoint_standalone_sctrl is generic ( @@ -98,7 +98,7 @@ architecture arch of trb_net16_endpoint_standalone_sctrl is begin - DAT_PASSIVE_API: trb_net16_api_base + DAT_PASSIVE_API: entity trb_net16_api_base generic map ( API_TYPE => c_API_PASSIVE, FIFO_TO_INT_DEPTH => FIFO_TO_INT_DEPTH, @@ -165,7 +165,7 @@ begin -- Hack from Jan... GSC_BUSY_OUT <= '1' when stat_fifo_to_int_i(31 downto 29) /= "000" else '0'; - regIO : trb_net16_regIO + regIO: entity trb_net16_regIO generic map( NUM_STAT_REGS => 0, NUM_CTRL_REGS => 0, @@ -251,22 +251,23 @@ begin ------------------------------------------------- assert REGIO_USE_1WIRE_INTERFACE /= c_NO report "No ID chip is not supported" severity error; assert REGIO_USE_1WIRE_INTERFACE /= c_MONITOR report "Onewire monitor is not supported" severity error; - - gen_XilinxDNA : if REGIO_USE_1WIRE_INTERFACE = c_XDNA generate - XilinxDNA : trb_net_xdna - port map( - CLK => CLK, - RESET => RESET, - DATA_OUT => buf_IDRAM_DATA_IN, - ADDR_OUT => buf_IDRAM_ADDR_IN, - WRITE_OUT=> buf_IDRAM_WR_IN, - TEMP_OUT => temperature_i, - ID_OUT => unique_id_i - ); - end generate; + assert if REGIO_USE_1WIRE_INTERFACE /= c_XDNA report "Xilinx XDNA is not supported" severity error; + +-- gen_XilinxDNA : if REGIO_USE_1WIRE_INTERFACE = c_XDNA generate +-- XilinxDNA: entity trb_net_xdna +-- port map( +-- CLK => CLK, +-- RESET => RESET, +-- DATA_OUT => buf_IDRAM_DATA_IN, +-- ADDR_OUT => buf_IDRAM_ADDR_IN, +-- WRITE_OUT=> buf_IDRAM_WR_IN, +-- TEMP_OUT => temperature_i, +-- ID_OUT => unique_id_i +-- ); +-- end generate; gen_1wire : if REGIO_USE_1WIRE_INTERFACE = c_YES generate - onewire_interface : trb_net_onewire + onewire_interface: entity trb_net_onewire generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 @@ -288,7 +289,7 @@ begin end generate; gen_i2c : if REGIO_USE_1WIRE_INTERFACE = c_I2C generate - i2c_interface : trb_net_i2cwire + i2c_interface: entity trb_net_i2cwire generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 @@ -311,7 +312,7 @@ begin end generate; gen_i2c_tc : if REGIO_USE_1WIRE_INTERFACE = c_I2C_TC generate - i2c_interface2 : trb_net_i2cwire2 + i2c_interface2: entity trb_net_i2cwire2 generic map( USE_TEMPERATURE_READOUT => c_YES, CLK_PERIOD => 10 diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index c6be94a..76d303a 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -1,14 +1,14 @@ -- for a description see HADES wiki -- http://hades-wiki.gsi.de/cgi-bin/view/DaqSlowControl/TrbNetIBUF -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.numeric_std.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.numeric_std.all; + use IEEE.std_logic_UNSIGNED.all; library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity trb_net16_ibuf is generic ( @@ -231,7 +231,7 @@ counter_match <= '1'; ------------------------ --the input fifo ------------------------ - THE_FIFO: trb_net16_fifo + THE_FIFO: entity trb_net16_fifo generic map ( DEPTH => DEPTH ) @@ -310,7 +310,7 @@ counter_match <= '1'; ------------------------ gen_crc : if USE_CHECKSUM = c_YES generate - THE_CRC : trb_net_CRC + THE_CRC: entity trb_net_CRC port map( CLK => CLK, RESET => CRC_RESET, @@ -346,9 +346,6 @@ counter_match <= '1'; CRC_active <= '0'; end generate; - - - ------------------------ --Handle FiFo output ------------------------ @@ -477,7 +474,7 @@ counter_match <= '1'; --Output logic ------------------------ gen_init_sbuf : if INIT_CAN_RECEIVE_DATA = c_YES generate - SBUF_INIT: trb_net16_sbuf + SBUF_INIT: entity trb_net16_sbuf generic map ( Version => SBUF_VERSION ) @@ -514,7 +511,7 @@ counter_match <= '1'; end generate; gen_reply_sbuf : if REPLY_CAN_RECEIVE_DATA = c_YES generate - SBUF_REPLY: trb_net16_sbuf + SBUF_REPLY: entity trb_net16_sbuf generic map ( Version => SBUF_VERSION ) diff --git a/trb_net16_io_multiplexer.vhd b/trb_net16_io_multiplexer.vhd index 5cf6ff5..261d166 100644 --- a/trb_net16_io_multiplexer.vhd +++ b/trb_net16_io_multiplexer.vhd @@ -1,11 +1,11 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity trb_net16_io_multiplexer is @@ -201,7 +201,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is buf_INT_PACKET_NUM_IN(i*3+2 downto i*3) <= INT_PACKET_NUM_IN(i*3+2 downto i*3); end generate; gen_input_sbuf : if USE_INPUT_SBUF(i) = c_YES generate - THE_SBUF : trb_net16_sbuf + THE_SBUF: entity trb_net16_sbuf generic map ( VERSION => 5 ) @@ -226,7 +226,7 @@ architecture trb_net16_io_multiplexer_arch of trb_net16_io_multiplexer is -ARBITER: trb_net_priority_arbiter + ARBITER: entity trb_net_priority_arbiter generic map ( WIDTH => 2**c_MUX_WIDTH ) @@ -286,35 +286,33 @@ ARBITER: trb_net_priority_arbiter process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - endpoint_locked <= '0'; - else - endpoint_locked <= next_endpoint_locked; - end if; + begin + if rising_edge(CLK) then + if RESET = '1' then + endpoint_locked <= '0'; + else + endpoint_locked <= next_endpoint_locked; end if; - end process; - - + end if; + end process; process(CLK) - begin - if rising_edge(CLK) then - if RESET = '1' then - current_mux_packet_number <= c_H0; - elsif mux_read = '1' then - if current_mux_packet_number = c_max_word_number then - current_mux_packet_number <= (others => '0'); - else - current_mux_packet_number <= current_mux_packet_number + 1; - end if; + begin + if rising_edge(CLK) then + if RESET = '1' then + current_mux_packet_number <= c_H0; + elsif mux_read = '1' then + if current_mux_packet_number = c_max_word_number then + current_mux_packet_number <= (others => '0'); + else + current_mux_packet_number <= current_mux_packet_number + 1; end if; end if; - end process; + end if; + end process; - MUX_SBUF: trb_net16_sbuf + MUX_SBUF: entity trb_net16_sbuf generic map ( VERSION => std_SBUF_VERSION ) diff --git a/trb_net16_iobuf.vhd b/trb_net16_iobuf.vhd index 3bc038e..f02e703 100644 --- a/trb_net16_iobuf.vhd +++ b/trb_net16_iobuf.vhd @@ -1,11 +1,11 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; - +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; --CTRL_STAT(0) : reset packet counter in IBUF @@ -93,10 +93,10 @@ architecture trb_net16_iobuf_arch of trb_net16_iobuf is attribute syn_hier of trb_net16_iobuf_arch : architecture is "firm"; -- internal signals for the INITIBUF - signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! - signal IBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0); - signal INITOBUF_stat_buffer, INITOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); - signal REPLYOBUF_stat_buffer, REPLYOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); + signal IBUF_error: STD_LOGIC_VECTOR (2 downto 0); -- error watch needed! + signal IBUF_stat_buffer : STD_LOGIC_VECTOR (31 downto 0); + signal INITOBUF_stat_buffer, INITOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); + signal REPLYOBUF_stat_buffer, REPLYOBUF_ctrl_buffer: STD_LOGIC_VECTOR (31 downto 0); signal ibuf_dataready_in, ibuf_read_out : std_logic; signal buf_stat_buffer_counter : std_logic_vector (31 downto 0); signal buf_stat_data_counter : std_logic_vector (31 downto 0); @@ -107,7 +107,7 @@ begin MED_READ_OUT <= ibuf_read_out; -- MED_REPLY_READ_OUT <= ibuf_read_out; - THE_IBUF : trb_net16_ibuf + THE_IBUF: entity trb_net16_ibuf generic map ( DEPTH => IBUF_DEPTH, USE_VENDOR_CORES => USE_VENDOR_CORES, @@ -143,7 +143,7 @@ begin end generate; GEN_TERM_IBUF: if IBUF_DEPTH=0 generate - THE_IBUF : trb_net16_term_ibuf + THE_IBUF: entity trb_net16_term_ibuf generic map( SBUF_VERSION => SBUF_VERSION, SECURE_MODE => c_YES @@ -172,7 +172,7 @@ begin genINITOBUF1 : if INIT_CAN_SEND_DATA = 1 generate - INITOBUF : trb_net16_obuf + INITOBUF: entity trb_net16_obuf generic map ( DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH, USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, @@ -200,7 +200,7 @@ begin end generate; genINITOBUF2 : if INIT_CAN_SEND_DATA = 0 generate gen_INITOBUF3 : if USE_ACKNOWLEDGE = 1 generate - INITOBUF : trb_net16_obuf_nodata + INITOBUF: entity trb_net16_obuf_nodata port map ( CLK => CLK, RESET => RESET, @@ -225,7 +225,7 @@ begin genREPLYOBUF1 : if REPLY_CAN_SEND_DATA = 1 generate - REPLYOBUF : trb_net16_obuf + REPLYOBUF: entity trb_net16_obuf generic map ( DATA_COUNT_WIDTH => OBUF_DATA_COUNT_WIDTH, USE_ACKNOWLEDGE => USE_ACKNOWLEDGE, @@ -254,7 +254,7 @@ begin genREPLYOBUF2 : if REPLY_CAN_SEND_DATA = 0 generate gen_REPLYOBUF3 : if USE_ACKNOWLEDGE = 1 generate - REPLYOBUF : trb_net16_obuf_nodata + REPLYOBUF: entity trb_net16_obuf_nodata port map ( CLK => CLK, RESET => RESET, diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 63ba7b1..63570c1 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -1,9 +1,10 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -use ieee.numeric_std.all; +library IEEE; + use IEEE.std_logic_1164.all; + use ieee.numeric_std.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; entity trb_net16_obuf is @@ -169,7 +170,7 @@ begin --------------------------------------------------------------------- -- The SBUF to buffer data to the multiplexer --------------------------------------------------------------------- - THE_SBUF : trb_net16_sbuf + THE_SBUF: entity trb_net16_sbuf generic map ( VERSION => SBUF_VERSION ) @@ -299,7 +300,7 @@ begin -- CRC generator --------------------------------------------------------------------- GEN_CRC : if USE_CHECKSUM = 1 generate - CRC_gen : trb_net_CRC + CRC_gen: entity trb_net_CRC port map( CLK => CLK, RESET => CRC_RESET, @@ -566,4 +567,5 @@ begin STAT_DEBUG(22 downto 21) <= std_logic_vector(TRANSMITTED_BUFFERS); STAT_DEBUG(25 downto 23) <= REC_BUFFER_SIZE_IN(2 downto 0); STAT_DEBUG(31 downto 26) <= (others => '0'); + end architecture; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 27d1870..b706c2e 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -1,12 +1,13 @@ -LIBRARY IEEE; -USE IEEE.std_logic_1164.ALL; -USE IEEE.std_logic_ARITH.ALL; -USE IEEE.std_logic_UNSIGNED.ALL; +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; -use work.version.all; -use work.config.all; + use work.trb_net_std.all; +-- use work.trb_net_components.all; + use work.version.all; + use work.config.all; entity trb_net16_regIO is generic ( @@ -194,7 +195,7 @@ begin --------------------------------------------------------------------- --5bit address decoder for registers --------------------------------------------------------------------- - pattern_gen_inst: trb_net_pattern_gen + THE_PATTERN_GEN: entity trb_net_pattern_gen generic map( WIDTH => 5 ) @@ -208,7 +209,7 @@ begin -- trbnet addresses --------------------------------------------------------------------- - the_addresses: trb_net16_addresses + THE_ADDRESSES: entity trb_net16_addresses generic map( INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, @@ -660,7 +661,7 @@ begin end process; - reg_fsm: process( CLK ) + PROC_REG_FSM: process( CLK ) begin if rising_edge(CLK) then if RESET = '1' then @@ -706,13 +707,13 @@ begin dat_data_counter <= next_dat_data_counter; end if; end if; - end process; + end process PROC_REG_FSM; --------------------------------------------------------------------- -- Packet Numbers --------------------------------------------------------------------- - reg_packet_counter: process( CLK ) + PROC_REG_PACKET_COUNTER: process( CLK ) begin if rising_edge(CLK) then if RESET = '1' then @@ -721,9 +722,9 @@ begin packet_counter <= next_packet_counter; end if; end if; - end process; + end process PROC_REG_PACKET_COUNTER; - next_packet_counter_proc: process( API_READ_IN, buf_API_DATAREADY_OUT, packet_counter ) + PROC_NEXT_PACKET_COUNTER: process( API_READ_IN, buf_API_DATAREADY_OUT, packet_counter ) begin if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then if packet_counter = "011" then @@ -734,12 +735,12 @@ begin else next_packet_counter <= packet_counter; end if; - end process; + end process PROC_NEXT_PACKET_COUNTER; --------------------------------------------------------------------- -- Generate output to API --------------------------------------------------------------------- - process( CLK ) + PROC_API_OUTPUT: process( CLK ) begin if rising_edge(CLK) then if RESET = '1' then @@ -755,11 +756,11 @@ begin buf_API_DATA_OUT <= next_API_DATA_OUT; end if; end if; - end process; + end process PROC_API_OUTPUT; --combine signals from regio and addresses - process(current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT, - ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT) + PROC_COMBINE: process( current_state, ADR_READ_OUT, buf_API_READ_OUT, ADR_SEND_OUT, ADR_DATA_OUT, ADR_DATAREADY_OUT, + ADR_PACKET_NUM_OUT, buf_API_SEND_OUT, buf_API_DATA_OUT, buf_API_DATAREADY_OUT, buf_API_PACKET_NUM_OUT ) begin if current_state = ADDRESS_RECV or current_state = ADDRESS_ACK then combined_API_READ_OUT <= ADR_READ_OUT; @@ -774,7 +775,7 @@ begin combined_API_DATAREADY_OUT <= buf_API_DATAREADY_OUT; combined_API_PACKET_NUM_OUT <= buf_API_PACKET_NUM_OUT; end if; - end process; + end process PROC_COMBINE; buf_API_ERROR_PATTERN_OUT(31 downto 19) <= (others => '0'); buf_API_ERROR_PATTERN_OUT(18) <= nomoredata; @@ -788,27 +789,27 @@ begin -- Read from DAT port --------------------------------------------------------------------- --save Dataready_in in case API can not read immediately - process( CLK ) - begin - if rising_edge(CLK) then - if RESET = '1' or current_state = IDLE then - DAT_DATAREADY_IN_before <= '0'; - elsif DAT_DATAREADY_IN = '1' then - DAT_DATAREADY_IN_before <= '1'; - elsif (API_READ_IN = '1' and buf_API_DATAREADY_OUT = '1')then - DAT_DATAREADY_IN_before <= '0'; - end if; + PROC_DATAREADY: process( CLK ) + begin + if rising_edge(CLK) then + if RESET = '1' or current_state = IDLE then + DAT_DATAREADY_IN_before <= '0'; + elsif DAT_DATAREADY_IN = '1' then + DAT_DATAREADY_IN_before <= '1'; + elsif (API_READ_IN = '1' and buf_API_DATAREADY_OUT = '1')then + DAT_DATAREADY_IN_before <= '0'; end if; - end process; - - process( CLK ) - begin - if rising_edge(CLK) then - if DAT_DATAREADY_IN = '1' then - buf_DAT_DATA_IN <= DAT_DATA_IN; - end if; + end if; + end process PROC_DATAREADY; + + PROC_BUF_DATA: process( CLK ) + begin + if rising_edge(CLK) then + if DAT_DATAREADY_IN = '1' then + buf_DAT_DATA_IN <= DAT_DATA_IN; end if; - end process; + end if; + end process PROC_BUF_DATA; --------------------------------------------------------------------- -- User defined CTRL registers @@ -840,15 +841,15 @@ begin --------------------------------------------------------------------- gen_strobe_ctrl_regs : if std_COMCTRLREG >= 1 generate process(CLK) - begin - if rising_edge(CLK) then - if COMMON_REGISTERS_OUT_write_enable(0) = '1' then - buf_COMMON_CTRL_REG_OUT(31 downto 0) <= saved_Reg_high & saved_Reg_low; - else - buf_COMMON_CTRL_REG_OUT(31 downto 0) <= (others => '0'); - end if; + begin + if rising_edge(CLK) then + if COMMON_REGISTERS_OUT_write_enable(0) = '1' then + buf_COMMON_CTRL_REG_OUT(31 downto 0) <= saved_Reg_high & saved_Reg_low; + else + buf_COMMON_CTRL_REG_OUT(31 downto 0) <= (others => '0'); end if; - end process; + end if; + end process; end generate; gen_normal_ctrl_regs : if std_COMCTRLREG > 1 generate @@ -877,44 +878,44 @@ begin -- Global Time Register --------------------------------------------------------------------- - proc_global_time : process(CLK) - begin - if rising_edge(CLK) then - TIMER_MS_TICK <= '0'; - if global_time_write = '1' then - global_time_i <= saved_Reg_high & saved_Reg_low; - elsif us_tick_i = '1' then - global_time_i <= global_time_i + 1; - if global_time_i(9 downto 0) = "0000000000" then - TIMER_MS_TICK <= '1'; - end if; + proc_global_time: process(CLK) + begin + if rising_edge(CLK) then + TIMER_MS_TICK <= '0'; + if global_time_write = '1' then + global_time_i <= saved_Reg_high & saved_Reg_low; + elsif us_tick_i = '1' then + global_time_i <= global_time_i + 1; + if global_time_i(9 downto 0) = "0000000000" then + TIMER_MS_TICK <= '1'; end if; end if; - end process; + end if; + end process; proc_us_tick : process(CLK) - begin - if rising_edge(CLK) then - if local_time_i = conv_std_logic_vector(CLOCK_FREQ - 1,8) then - local_time_i <= (others => '0'); - us_tick_i <= '1'; - else - local_time_i <= local_time_i + 1; - us_tick_i <= '0'; - end if; + begin + if rising_edge(CLK) then + if local_time_i = conv_std_logic_vector(CLOCK_FREQ - 1,8) then + local_time_i <= (others => '0'); + us_tick_i <= '1'; + else + local_time_i <= local_time_i + 1; + us_tick_i <= '0'; end if; - end process; + end if; + end process; proc_time_since_trg : process(CLK) - begin - if rising_edge(CLK) then - if TRIGGER_MONITOR = '1' then - time_since_last_trg_i <= (others => '0'); - else - time_since_last_trg_i <= time_since_last_trg_i + 1; - end if; + begin + if rising_edge(CLK) then + if TRIGGER_MONITOR = '1' then + time_since_last_trg_i <= (others => '0'); + else + time_since_last_trg_i <= time_since_last_trg_i + 1; end if; - end process; + end if; + end process; GLOBAL_TIME <= global_time_i; LOCAL_TIME <= local_time_i; @@ -924,30 +925,30 @@ begin --------------------------------------------------------------------- -- ROM with board information --------------------------------------------------------------------- - board_rom : entity work.rom_16x16 - generic map( - INIT0 => COMPILE_TIME_LIB(15 downto 0), - INIT1 => COMPILE_TIME_LIB(31 downto 16), - INIT2 => INCLUDED_FEATURES(15 downto 0), - INIT3 => INCLUDED_FEATURES(31 downto 16), - INIT4 => HARDWARE_VERSION(15 downto 0), - INIT5 => HARDWARE_VERSION(31 downto 16), - INIT6 => INCLUDED_FEATURES(47 downto 32), - INIT7 => INCLUDED_FEATURES(63 downto 48), - INIT8 => x"00" & BROADCAST_SPECIAL_ADDR, - INIT9 => INIT_ADDRESS, - INITA => x"0000", - INITB => x"0000", - INITC => x"0000", - INITD => x"0000", - INITE => x"0000", - INITF => x"0000" - ) - port map( - CLK => CLK, - a => rom_read_addr, - dout => rom_read_dout - ); + THE_BOARD_ROM: entity work.rom_16x16 + generic map( + INIT0 => COMPILE_TIME_LIB(15 downto 0), + INIT1 => COMPILE_TIME_LIB(31 downto 16), + INIT2 => INCLUDED_FEATURES(15 downto 0), + INIT3 => INCLUDED_FEATURES(31 downto 16), + INIT4 => HARDWARE_VERSION(15 downto 0), + INIT5 => HARDWARE_VERSION(31 downto 16), + INIT6 => INCLUDED_FEATURES(47 downto 32), + INIT7 => INCLUDED_FEATURES(63 downto 48), + INIT8 => x"00" & BROADCAST_SPECIAL_ADDR, + INIT9 => INIT_ADDRESS, + INITA => x"0000", + INITB => x"0000", + INITC => x"0000", + INITD => x"0000", + INITE => x"0000", + INITF => x"0000" + ) + port map( + CLK => CLK, + a => rom_read_addr, + dout => rom_read_dout + ); --------------------------------------------------------------------- diff --git a/trb_net16_sbuf.vhd b/trb_net16_sbuf.vhd index 21b93b9..1d3105f 100644 --- a/trb_net16_sbuf.vhd +++ b/trb_net16_sbuf.vhd @@ -1,12 +1,11 @@ -LIBRARY IEEE; -USE IEEE.STD_LOGIC_1164.ALL; -USE IEEE.STD_LOGIC_ARITH.ALL; -USE IEEE.STD_LOGIC_UNSIGNED.ALL; - +library IEEE; + use IEEE.std_logic_1164.all; + use IEEE.std_logic_arith.all; + use IEEE.std_logic_unsigned.all; + library work; -use work.trb_net_std.all; -use work.trb_net_components.all; - + use work.trb_net_std.all; + --use work.trb_net_components.all; ------------------------------------------------------------------------------- -- Single buffer with one more buffer to keep the speed of the datalink @@ -25,7 +24,6 @@ use work.trb_net_components.all; -- the same logic. ------------------------------------------------------------------------------- - entity trb_net16_sbuf is generic ( VERSION : integer := 0 @@ -65,7 +63,7 @@ begin gen_version_0 : if VERSION = 0 generate - sbuf: trb_net_sbuf + sbuf: entity trb_net_sbuf generic map( DATA_WIDTH => 19 ) @@ -86,7 +84,7 @@ begin end generate; gen_version_2 : if VERSION = 2 generate - sbuf: trb_net_sbuf2 + sbuf: entity trb_net_sbuf2 generic map( DATA_WIDTH => 19 ) @@ -107,7 +105,7 @@ begin end generate; gen_version_3 : if VERSION = 3 generate - sbuf: trb_net_sbuf3 + sbuf: entity trb_net_sbuf3 generic map( DATA_WIDTH => 19 ) @@ -128,7 +126,7 @@ begin end generate; gen_version_4 : if VERSION = 4 generate - sbuf: trb_net_sbuf4 + sbuf: entity trb_net_sbuf4 generic map( DATA_WIDTH => 19 ) @@ -149,7 +147,7 @@ begin end generate; gen_version_5 : if VERSION = 5 generate - sbuf: trb_net_sbuf5 + sbuf: entity trb_net_sbuf5 port map( CLK => CLK, RESET => RESET, @@ -169,7 +167,7 @@ begin end generate; gen_version_6 : if VERSION = 6 generate - sbuf: trb_net_sbuf6 + sbuf: entity trb_net_sbuf6 port map( CLK => CLK, RESET => RESET, -- 2.43.0