From 272835582d93d2c475e55f51cab3eab6c95b83fd Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 26 Sep 2017 10:33:59 +0200 Subject: [PATCH] slightly better handling of different port number for input logic --- base/code/input_statistics.vhd | 6 +++--- base/code/input_to_trigger_logic_record.vhd | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/base/code/input_statistics.vhd b/base/code/input_statistics.vhd index c6eb8c7..8e872ec 100644 --- a/base/code/input_statistics.vhd +++ b/base/code/input_statistics.vhd @@ -33,7 +33,7 @@ signal inp_reg : std_logic_vector(INPUTS-1 downto 0); signal inp_reg_last : std_logic_vector(INPUTS-1 downto 0); signal inp_inv : std_logic_vector(INPUTS-1 downto 0); signal inp_stretch : std_logic_vector(INPUTS-1 downto 0); -signal inp_reg_95 : std_logic_vector(95 downto 0); +signal inp_reg_95 : std_logic_vector(95 downto 0) := (others => '0'); signal trigger_fifo, trigger_fifo_buf : std_logic; signal trigger_fifo_real, trigger_fifo_external : std_logic := '0'; @@ -51,8 +51,8 @@ signal fifo_read : std_logic_vector(LAST_FIFO_NUM downto 0); signal fifo_wait,fifo_wait2,fifo_wait3 : std_logic; signal fifo_empty : std_logic_vector(LAST_FIFO_NUM downto 0); signal fifo_write : std_logic; -signal fifo_select : integer range 0 to 95; -signal fifo_in_sel : integer range 0 to 95; +signal fifo_select : integer range 0 to INPUTS-1; +signal fifo_in_sel : integer range 0 to INPUTS-1; type cnt_t is array(0 to INPUTS-1) of unsigned(23 downto 0); diff --git a/base/code/input_to_trigger_logic_record.vhd b/base/code/input_to_trigger_logic_record.vhd index 584d91d..295a8dc 100644 --- a/base/code/input_to_trigger_logic_record.vhd +++ b/base/code/input_to_trigger_logic_record.vhd @@ -232,7 +232,7 @@ gen_mult : if OUTPUTS >= 2 generate begin wait until rising_edge(CLK); m := 0; - for i in 0 to INPUTS-1 loop + for i in 0 to 31 loop --was INPUTS-1 @ 09.17 if inp_verylong(i) = '1' and multiplicity_enable(i) = '1' then m := m + 1; end if; -- 2.43.0