From 27ee17b13a88e21e21dc1df16054c8a01868fa39 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 14 Apr 2022 10:02:37 +0200 Subject: [PATCH] added I2C to Mimosis design --- mimosis/config_compile_frankfurt.pl | 2 +- mimosis/cores/pll_200_160/pll_200_160.ipx | 8 ++ mimosis/cores/pll_200_160/pll_200_160.lpc | 16 +-- mimosis/cores/pll_200_160/pll_200_160.vhd | 21 ++-- mimosis/par.p2t | 2 +- mimosis/trb5sc_mimosis.vhd | 143 ++++++++++++++++++++-- pinout/trb5sc_hdmi.lpf | 8 +- 7 files changed, 168 insertions(+), 32 deletions(-) create mode 100644 mimosis/cores/pll_200_160/pll_200_160.ipx diff --git a/mimosis/config_compile_frankfurt.pl b/mimosis/config_compile_frankfurt.pl index 62708aa..04d1fbf 100644 --- a/mimosis/config_compile_frankfurt.pl +++ b/mimosis/config_compile_frankfurt.pl @@ -8,7 +8,7 @@ TOPNAME => "trb5sc_mimosis", lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; lm_license_file_for_par => "1702\@jspc29", lattice_path => '/d/jspc29/lattice/diamond/3.11_x64', -synplify_path => '/d/jspc29/lattice/synplify/P-2019.09-SP1/', +synplify_path => '/d/jspc29/lattice/synplify/R-2020.09-SP1/', nodelist_file => '../nodelist_frankfurt.txt', pinout_file => 'trb5sc_hdmi', diff --git a/mimosis/cores/pll_200_160/pll_200_160.ipx b/mimosis/cores/pll_200_160/pll_200_160.ipx new file mode 100644 index 0000000..43fe758 --- /dev/null +++ b/mimosis/cores/pll_200_160/pll_200_160.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/mimosis/cores/pll_200_160/pll_200_160.lpc b/mimosis/cores/pll_200_160/pll_200_160.lpc index 012e538..defee1c 100644 --- a/mimosis/cores/pll_200_160/pll_200_160.lpc +++ b/mimosis/cores/pll_200_160/pll_200_160.lpc @@ -14,10 +14,10 @@ CoreStatus=Demo CoreName=PLL CoreRevision=5.8 ModuleName=pll_200_160 -SourceFormat=vhdl +SourceFormat=VHDL ParameterFileVersion=1.0 -Date=07/02/2021 -Time=12:07:59 +Date=11/12/2021 +Time=15:18:43 [Parameters] Verilog=0 @@ -43,11 +43,11 @@ CLKOS_TOL=0.0 CLKOS_DIV=2 CLKOS_ACTUAL_FREQ=320.000000 CLKOS_MUXB=DISABLED -CLKOS2_Enable=DISABLED -CLKOS2_FREQ=100.00 +CLKOS2_Enable=ENABLED +CLKOS2_FREQ=40.00 CLKOS2_TOL=0.0 -CLKOS2_DIV=1 -CLKOS2_ACTUAL_FREQ= +CLKOS2_DIV=16 +CLKOS2_ACTUAL_FREQ=40.000000 CLKOS2_MUXC=DISABLED CLKOS3_Enable=DISABLED CLKOS3_FREQ=100.00 @@ -90,4 +90,4 @@ PLL_LOCK_STK=DISABLED PLL_USE_SMI=DISABLED [Command] -cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 +cmd_line= -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 diff --git a/mimosis/cores/pll_200_160/pll_200_160.vhd b/mimosis/cores/pll_200_160/pll_200_160.vhd index 29449d8..6759858 100644 --- a/mimosis/cores/pll_200_160/pll_200_160.vhd +++ b/mimosis/cores/pll_200_160/pll_200_160.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond (64-bit) 3.11.2.446 +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 -- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.11_x64/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -phase_cntl STATIC -fb_mode 1 -fdc /local/trb/git/trb5sc/mimosis/cores/pll_200_160/pll_200_160.fdc +--/d/jspc29/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_200_160 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 200 -fclkop 160 -fclkop_tol 0.0 -fclkos 320 -fclkos_tol 0.0 -phases 0 -fclkos2 40.00 -fclkos2_tol 0.0 -phases2 0 -phase_cntl STATIC -fb_mode 1 --- Fri Jul 2 12:08:04 2021 +-- Fri Nov 12 15:18:43 2021 library IEEE; use IEEE.std_logic_1164.all; @@ -13,7 +13,8 @@ entity pll_200_160 is port ( CLKI: in std_logic; CLKOP: out std_logic; - CLKOS: out std_logic); + CLKOS: out std_logic; + CLKOS2: out std_logic); end pll_200_160; architecture Structure of pll_200_160 is @@ -21,16 +22,19 @@ architecture Structure of pll_200_160 is -- internal signal declarations signal REFCLK: std_logic; signal LOCK: std_logic; + signal CLKOS2_t: std_logic; signal CLKOS_t: std_logic; signal CLKOP_t: std_logic; signal scuba_vhi: std_logic; signal scuba_vlo: std_logic; + attribute FREQUENCY_PIN_CLKOS2 : string; attribute FREQUENCY_PIN_CLKOS : string; attribute FREQUENCY_PIN_CLKOP : string; attribute FREQUENCY_PIN_CLKI : string; attribute ICP_CURRENT : string; attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOS2 of PLLInst_0 : label is "40.000000"; attribute FREQUENCY_PIN_CLKOS of PLLInst_0 : label is "320.000000"; attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "160.000000"; attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "200.000000"; @@ -52,15 +56,15 @@ begin generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, - CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1, + CLKOS2_CPHASE=> 15, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 1, CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 3, PLL_LOCK_MODE=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", - OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "ENABLED", OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "ENABLED", OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, - CLKOS2_DIV=> 1, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4, + CLKOS2_DIV=> 16, CLKOS_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 4, CLKI_DIV=> 5, FEEDBK_PATH=> "CLKOP") port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, @@ -68,9 +72,10 @@ begin STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, - CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + CLKOS2=>CLKOS2_t, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, REFCLK=>REFCLK, CLKINTFB=>open); + CLKOS2 <= CLKOS2_t; CLKOS <= CLKOS_t; CLKOP <= CLKOP_t; end Structure; diff --git a/mimosis/par.p2t b/mimosis/par.p2t index 9e4ef4d..cd64b6a 100644 --- a/mimosis/par.p2t +++ b/mimosis/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 2 +-t 3 -c 2 -e 2 -i 10 diff --git a/mimosis/trb5sc_mimosis.vhd b/mimosis/trb5sc_mimosis.vhd index af8f783..98bca21 100644 --- a/mimosis/trb5sc_mimosis.vhd +++ b/mimosis/trb5sc_mimosis.vhd @@ -43,12 +43,14 @@ entity trb5sc_mimosis is H2 : inout std_logic_vector(4 downto 0); H3 : inout std_logic_vector(4 downto 0); H4 : inout std_logic_vector(4 downto 0); - H5 : inout std_logic_vector(4 downto 0); + H5 : inout std_logic_vector(3 downto 0); H6 : inout std_logic_vector(4 downto 0); H7 : inout std_logic_vector(4 downto 0); PIN : inout std_logic_vector(8 downto 1); + MIMOSIS_SCL, MIMOSIS_SDA : inout std_logic; + --ADC ADC_SCLK : out std_logic; ADC_NCS : out std_logic; @@ -95,7 +97,7 @@ architecture arch of trb5sc_mimosis is attribute syn_keep : boolean; attribute syn_preserve : boolean; - signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320 : std_logic; + signal clk_sys, clk_full, clk_full_osc, clk_160, clk_320, clk_40 : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; @@ -118,8 +120,8 @@ architecture arch of trb5sc_mimosis is signal readout_rx : READOUT_RX; signal readout_tx : readout_tx_array_t(0 to 0); - signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx : CTRLBUS_TX; - signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx : CTRLBUS_RX; + signal ctrlbus_tx, bustdc_tx, bussci_tx, bustools_tx, bustc_tx, busthresh_tx, bus_master_in, busmimosis_tx, busi2c_tx : CTRLBUS_TX; + signal ctrlbus_rx, bustdc_rx, bussci_rx, bustools_rx, bustc_rx, busthresh_rx, bus_master_out, busmimosis_rx, busi2c_rx : CTRLBUS_RX; signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); @@ -139,6 +141,14 @@ architecture arch of trb5sc_mimosis is signal inp_i : std_logic_vector( 7 downto 0); signal dummy : std_logic_vector( 1 downto 0); + + signal i2c_reg_0, i2c_reg_1 : std_logic_vector(31 downto 0); + signal i2c_reg_2 : std_logic_vector(31 downto 0); + signal i2c_reg_4, i2c_reg_5 : std_logic_vector(31 downto 0); + signal mimosis_scl_drv, mimosis_sda_drv : std_logic; + signal i2c_go_100, i2c_go : std_logic; + signal i2c_reg_5_40 : std_logic_vector(31 downto 0); + begin @@ -174,10 +184,12 @@ THE_160_PLL : entity work.pll_200_160 port map( CLKI => clk_full_osc, CLKOP => clk_160, - CLKOS => clk_320 + CLKOS => clk_320, + CLKOS2=> clk_40 ); H5(3) <= clk_320; +RJ(0) <= clk_40; --------------------------------------------------------------------------- -- TrbNet Uplink @@ -284,12 +296,11 @@ H5(3) <= clk_320; -- Bus Handler --------------------------------------------------------------------------- - THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record generic map( - PORT_NUMBER => 4, - PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 5 => x"c000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, 5 => 12, others => 0), + PORT_NUMBER => 5, + PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"de00", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 12, 4 => 5, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -303,12 +314,12 @@ H5(3) <= clk_320; BUS_RX(1) => bussci_rx, --SCI Serdes BUS_RX(2) => bustc_rx, --Clock switch BUS_RX(3) => busmimosis_rx, --- BUS_RX(4) => bustdc_rx, + BUS_RX(4) => busi2c_rx, BUS_TX(0) => bustools_tx, BUS_TX(1) => bussci_tx, BUS_TX(2) => bustc_tx, BUS_TX(3) => busmimosis_tx, --- BUS_TX(4) => bustdc_tx, + BUS_TX(4) => busi2c_tx, STAT_DEBUG => open ); @@ -364,7 +375,113 @@ H5(3) <= clk_320; FLASH_HOLD <= '1'; FLASH_WP <= '1'; +--------------------------------------------------------------------------- +-- I2C +--------------------------------------------------------------------------- +THE_I2C : entity work.i2c_slim + port map( + CLOCK => clk_40, + RESET => reset_i, + -- I2C command / setup + I2C_GO_IN => i2c_go, + ACTION_IN => i2c_reg_1(8), -- '0' -> write, '1' -> read + WORD_IN => i2c_reg_1(0), -- '0' -> byte, '1' -> word + I2C_SPEED_IN => i2c_reg_0(5 downto 0), -- speed adjustment (to be defined) + I2C_ADDR_IN => i2c_reg_2(7 downto 0), -- I2C address byte (R/W bit is ignored) + I2C_CMD_IN => i2c_reg_2(15 downto 8), -- I2C command byte (sent after address byte) + I2C_DW_IN => i2c_reg_2(31 downto 16),-- data word for write command + I2C_DR_OUT => i2c_reg_4(15 downto 0), -- data word from read command + STATUS_OUT => i2c_reg_4(23 downto 16), + VALID_OUT => i2c_reg_4(31), + I2C_BUSY_OUT => i2c_reg_4(30), + I2C_DONE_OUT => i2c_reg_4(29), + -- I2C connections + SDA_IN => PIN(4), + SDA_OUT => mimosis_sda_drv, + SCL_IN => PIN(3), + SCL_OUT => mimosis_scl_drv, + -- Debug + BSM_OUT => i2c_reg_4(28 downto 24) +); + +-- I2C signal open collector driver +PIN(4) <= '0' when (mimosis_sda_drv = '0') else 'Z'; +PIN(3) <= '0' when (mimosis_scl_drv = '0') else 'Z'; +H5(1) <= i2c_reg_5_40(0); --MIMOSIS_SYNC +PIN(1) <= i2c_reg_5_40(4); --MIMOSIS_START +PIN(2) <= i2c_reg_5_40(8); --MIMOSIS_RESET + +PROC_I2C_REGS : process begin + wait until rising_edge(CLK_SYS); + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '0'; + busi2c_tx.nack <= '0'; + busi2c_tx.data <= (others => '0'); + i2c_go_100 <= '0'; + + if busi2c_rx.write = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + i2c_reg_0 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + i2c_reg_1 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + i2c_reg_2 <= busi2c_rx.data; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + i2c_go_100 <= busi2c_rx.data(0); + elsif busi2c_rx.addr(3 downto 0) = x"5" then + i2c_reg_5 <= busi2c_rx.data; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + elsif busi2c_rx.read = '1' then + busi2c_tx.ack <= '1'; + if busi2c_rx.addr(3 downto 0) = x"0" then + busi2c_tx.data <= i2c_reg_0; + elsif busi2c_rx.addr(3 downto 0) = x"1" then + busi2c_tx.data <= i2c_reg_1; + elsif busi2c_rx.addr(3 downto 0) = x"2" then + busi2c_tx.data <= i2c_reg_2; + elsif busi2c_rx.addr(3 downto 0) = x"3" then + busi2c_tx.data <= (others => '0'); + elsif busi2c_rx.addr(3 downto 0) = x"4" then + busi2c_tx.data <= i2c_reg_4; + elsif busi2c_rx.addr(3 downto 0) = x"5" then + busi2c_tx.data <= i2c_reg_5; + else + busi2c_tx.ack <= '0'; + busi2c_tx.unknown <= '1'; + end if; + end if; +end process; + + THE_I2C_GO_SYNC : pulse_sync + port map( + CLK_A_IN => clk_sys, + RESET_A_IN => reset_i, + PULSE_A_IN => i2c_go_100, + CLK_B_IN => clk_40, + RESET_B_IN => reset_i, + PULSE_B_OUT => i2c_go + ); + + THE_MIMOSIS_SIGNAL_SYNC : signal_sync + generic map( + WIDTH => 32, + DEPTH => 2 + ) + port map( + RESET => reset_i, + CLK0 => clk_sys, + CLK1 => clk_40, + D_IN => i2c_reg_5, + D_OUT => i2c_reg_5_40 + ); + + + --------------------------------------------------------------------------- -- LED --------------------------------------------------------------------------- @@ -381,7 +498,7 @@ H5(3) <= clk_320; TEST(14) <= flash_ncs_i; FLASH_NCS <= flash_ncs_i; - --------------------------------------------------------------------------- +--------------------------------------------------------------------------- -- Output stage --------------------------------------------------------------------------- THE_OUT : entity work.testout @@ -409,7 +526,7 @@ H5(3) <= clk_320; when 3 => out_data <= x"0000"; when 4 => out_data <= x"5555"; when 5 => out_data <= x"5555"; - when 6 => out_data <= x"5555";--sdummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy; + when 6 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy; when 7 => out_data <= x"5555";--dummy & dummy & dummy & dummy & dummy & dummy & dummy & dummy; end case; end process; diff --git a/pinout/trb5sc_hdmi.lpf b/pinout/trb5sc_hdmi.lpf index a6d2520..3a8bb93 100644 --- a/pinout/trb5sc_hdmi.lpf +++ b/pinout/trb5sc_hdmi.lpf @@ -78,7 +78,13 @@ LOCATE COMP "H5[2]" SITE "N32" ; #was "FE_DIFF[4]" LOCATE COMP "H7[2]" SITE "U31" ; #was "FE_DIFF[5]" LOCATE COMP "H5[3]" SITE "R32" ; #was "FE_DIFF[6]" LOCATE COMP "H7[3]" SITE "W30" ; #was "FE_DIFF[7]" -LOCATE COMP "H5[4]" SITE "T32" ; #was "FE_DIFF[8]" +#LOCATE COMP "H5[4]" SITE "T32" ; #was "FE_DIFF[8]" + +LOCATE COMP "MIMOSIS_SCL" SITE "T32" ; #was "FE_DIFF[8]" +LOCATE COMP "MIMOSIS_SDA" SITE "U32" ; #was "FE_DIFF[8]" +IOBUF PORT "MIMOSIS_SCL" IO_TYPE=LVCMOS25 ; +IOBUF PORT "MIMOSIS_SDA" IO_TYPE=LVCMOS25 ; + # LOCATE COMP "FE_DIFF[9]" SITE "V32" ; #was "FE_DIFF[9]" LOCATE COMP "H7[4]" SITE "Y26" ; #was "FE_DIFF[10]" # LOCATE COMP "FE_DIFF[11]" SITE "Y28" ; #was "FE_DIFF[11]" -- 2.43.0