From 2845b7eaa4f9636b83d1161c420ede9ccbb48ede Mon Sep 17 00:00:00 2001 From: Peter Lemmens Date: Thu, 26 Sep 2013 10:15:31 +0200 Subject: [PATCH] This works... now and then. Trbnet can quite reliably be started with optical link disconnected. Once working it is stable. Soda_source: SOB-faker is now clocked with recovered clock to make it async. This works nicely. Transmitted data is always correct. Client: often starts-up somehow out of phase. It receives the last 3 bytes of 4 and the 4th=0x00. Reset problem? --- soda_client.ldf | 6 +++ soda_client.lpf | 2 + soda_source.ldf | 24 ++++++---- soda_source.lpf | 2 + source/TB_soda_chain.vhd | 5 +- source/posedge_to_pulse.vhd | 79 ++++++++++++++++--------------- source/soda_components.vhd | 4 +- source/soda_packet_builder.vhd | 17 +++---- source/soda_reply_handler.vhd | 3 -- source/soda_source.vhd | 57 ++++++---------------- source/soda_superburst_gen.vhd | 2 +- source/trb3_periph_sodaclient.vhd | 2 +- source/trb3_periph_sodasource.vhd | 19 ++++---- 13 files changed, 100 insertions(+), 122 deletions(-) diff --git a/soda_client.ldf b/soda_client.ldf index 874c4b5..9b9b10f 100644 --- a/soda_client.ldf +++ b/soda_client.ldf @@ -320,6 +320,12 @@ + + + + + + diff --git a/soda_client.lpf b/soda_client.lpf index 2de909c..8a14f16 100644 --- a/soda_client.lpf +++ b/soda_client.lpf @@ -1,3 +1,4 @@ +rvl_alias "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; @@ -264,3 +265,4 @@ MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns; MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +BLOCK JTAGPATHS; diff --git a/soda_source.ldf b/soda_source.ldf index a9f9e31..369f753 100644 --- a/soda_source.ldf +++ b/soda_source.ldf @@ -17,9 +17,6 @@ - - - @@ -38,12 +35,21 @@ - + + + + + + + + + + @@ -302,19 +308,19 @@ - + - + - + - + - + diff --git a/soda_source.lpf b/soda_source.lpf index 2de909c..8a14f16 100644 --- a/soda_source.lpf +++ b/soda_source.lpf @@ -1,3 +1,4 @@ +rvl_alias "clk_raw_internal" "clk_raw_internal"; BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; @@ -264,3 +265,4 @@ MULTICYCLE FROM CELL "THE_SODA_SOURCE/sci*" 20 ns; MULTICYCLE TO CELL "THE_SODA_SOURCE/wa_pos*" 20 ns; MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +BLOCK JTAGPATHS; diff --git a/source/TB_soda_chain.vhd b/source/TB_soda_chain.vhd index 0ada9e4..52967e6 100644 --- a/source/TB_soda_chain.vhd +++ b/source/TB_soda_chain.vhd @@ -18,8 +18,8 @@ end entity; architecture TestBench of TB_soda_chain is -- Clock period definitions - constant sysclk_period: time:= 5ns; - constant sodaclk_period: time:= 4.999ns; + constant sysclk_period: time:= 10ns; + constant sodaclk_period: time:= 5ns; --Inputs @@ -61,6 +61,7 @@ begin THE_SODA_SOURCE : soda_source port map( SYSCLK => sys_clk_S, + SODACLK => soda_clk_S, RESET => rst_S, CLEAR => '0', CLK_EN => '1', diff --git a/source/posedge_to_pulse.vhd b/source/posedge_to_pulse.vhd index 1bdc601..6e51e67 100644 --- a/source/posedge_to_pulse.vhd +++ b/source/posedge_to_pulse.vhd @@ -19,53 +19,54 @@ use IEEE.STD_LOGIC_ARITH.all; use IEEE.STD_LOGIC_UNSIGNED.all; entity posedge_to_pulse is - port ( - clock_in : in std_logic; - clock_out : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic - ); + port ( + IN_CLK : in std_logic; + OUT_CLK : in std_logic; + CLK_EN : in std_logic; + SIGNAL_IN : in std_logic; + PULSE_OUT : out std_logic + ); end posedge_to_pulse; architecture behavioral of posedge_to_pulse is - signal resetff : std_logic := '0'; - signal last_signal_in : std_logic := '0'; - signal qff : std_logic := '0'; - signal qff1 : std_logic := '0'; - signal qff2 : std_logic := '0'; - signal qff3 : std_logic := '0'; -begin + signal resetff : std_logic := '0'; + signal last_signal_in : std_logic := '0'; + signal qff : std_logic := '0'; + signal qff1 : std_logic := '0'; + signal qff2 : std_logic := '0'; + signal qff3 : std_logic := '0'; + begin -process (clock_in) -begin - if rising_edge(clock_in) then - if resetff='1' then - qff <= '0'; - elsif (en_clk='1') and ((signal_in='1') and (qff='0') and (last_signal_in='0')) then - qff <= '1'; - else - qff <= qff; + process (IN_CLK) + begin + if rising_edge(IN_CLK) then + if resetff='1' then + qff <= '0'; + elsif (CLK_EN='1') and ((SIGNAL_IN='1') and (qff='0') and (last_signal_in='0')) then + qff <= '1'; + else + qff <= qff; + end if; + last_signal_in <= SIGNAL_IN; end if; - last_signal_in <= signal_in; - end if; -end process; -resetff <= qff2; + end process; -process (clock_out) -begin - if rising_edge(clock_out) then - if qff3='0' and qff2='1' then - pulse <= '1'; - else - pulse <= '0'; + resetff <= qff2; + + process (OUT_CLK) + begin + if rising_edge(OUT_CLK) then + if qff3='0' and qff2='1' then + PULSE_OUT <= '1'; + else + PULSE_OUT <= '0'; + end if; + qff3 <= qff2; + qff2 <= qff1; + qff1 <= qff; end if; - qff3 <= qff2; - qff2 <= qff1; - qff1 <= qff; - end if; -end process; + end process; end behavioral; diff --git a/source/soda_components.vhd b/source/soda_components.vhd index 3825aad..a378d25 100644 --- a/source/soda_components.vhd +++ b/source/soda_components.vhd @@ -42,7 +42,7 @@ package soda_components is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection - LINK_PHASE : natural range 0 to 1 := 0; + LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0'); SODA_CMD_STROBE_IN : in std_logic := '0'; -- START_OF_SUPERBURST : in std_logic := '0'; SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); @@ -251,7 +251,7 @@ package soda_components is IN_CLK : in std_logic; OUT_CLK : in std_logic; CLK_EN : in std_logic; - SINGAL_IN : in std_logic; + SIGNAL_IN : in std_logic; PULSE_OUT : out std_logic ); end component; diff --git a/source/soda_packet_builder.vhd b/source/soda_packet_builder.vhd index d86a6b0..3f68c1e 100644 --- a/source/soda_packet_builder.vhd +++ b/source/soda_packet_builder.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; @@ -15,7 +16,7 @@ entity soda_packet_builder is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection - LINK_PHASE : natural range 0 to 1 := 0; + LINK_PHASE_IN : in std_logic_vector(1 downto 0) := (others => '0'); SODA_CMD_STROBE_IN : in std_logic := '0'; -- START_OF_SUPERBURST : in std_logic := '0'; SUPER_BURST_NR_IN : in std_logic_vector(30 downto 0) := (others => '0'); @@ -80,13 +81,13 @@ begin case packet_state_S is when c_IDLE => if (START_OF_SUPERBURST='1') then - if (LINK_PHASE=0) then + if (LINK_PHASE_IN = "00") then packet_state_S <= c_BST1; else packet_state_S <= c_WAIT4BST1; end if; elsif (soda_cmd_strobe_S='1') then - if (LINK_PHASE=0) then + if (LINK_PHASE_IN = "00") then packet_state_S <= c_CMD1; else packet_state_S <= c_WAIT4CMD1; @@ -94,14 +95,8 @@ begin else packet_state_S <= c_IDLE; end if; --- when c_IDLE => --- if (START_OF_SUPERBURST='1') then --- packet_state_S <= c_BST1; --- elsif (soda_cmd_strobe_S='1') then --- packet_state_S <= c_CMD1; --- end if; when c_WAIT4BST1 => - if (LINK_PHASE=0) then + if (LINK_PHASE_IN = "00") then packet_state_S <= c_BST1; else packet_state_S <= c_WAIT4BST1; @@ -127,7 +122,7 @@ begin packet_state_S <= c_CMD1; end if; when c_WAIT4CMD1 => - if (LINK_PHASE=0) then + if (LINK_PHASE_IN = "00") then packet_state_S <= c_CMD1; else packet_state_S <= c_WAIT4CMD1; diff --git a/source/soda_reply_handler.vhd b/source/soda_reply_handler.vhd index db11bd8..3c341ae 100644 --- a/source/soda_reply_handler.vhd +++ b/source/soda_reply_handler.vhd @@ -15,13 +15,10 @@ entity soda_reply_handler is CLEAR : in std_logic; -- asynchronous reset CLK_EN : in std_logic; --Internal Connection --- LAST_PACKET _IN : in t_PACKET_TYPE_SENT := c_NO_PACKET; EXPECTED_REPLY_IN : in std_logic_vector(7 downto 0) := (others => '0'); RX_DLM_IN : in std_logic := '0'; RX_DLM_WORD_IN : in std_logic_vector(7 downto 0) := (others => '0'); REPLY_VALID_OUT : out std_logic := '0'; --- SUPERBURST_ERROR_OUT : out std_logic := '0'; --- CRC_ERROR_OUT : out std_logic := '0'; REPLY_OK_OUT : out std_logic := '0' ); end soda_reply_handler; diff --git a/source/soda_source.vhd b/source/soda_source.vhd index e7aa09b..ded23a0 100644 --- a/source/soda_source.vhd +++ b/source/soda_source.vhd @@ -1,6 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; @@ -35,18 +36,8 @@ end soda_source; architecture Behavioral of soda_source is -component posedge_to_pulse is - port ( - clock_in : in std_logic; - clock_out : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic - ); -end component; - --SODA - signal link_phase_S : natural range 0 to 1 := 0; + signal link_phase_S : std_logic_vector(1 downto 0) := (others => '0'); signal soda_cmd_word_S : std_logic_vector(30 downto 0) := (others => '0'); signal soda_cmd_strobe_S : std_logic := '0'; signal soda_cmd_strobe_sodaclk_S : std_logic := '0'; @@ -57,7 +48,7 @@ end component; type t_STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: t_STATES; - signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET; +-- signal last_packet_sent_S : t_PACKET_TYPE_SENT := c_NO_PACKET; -- slave bus signals signal bus_ack_x : std_logic; @@ -102,7 +93,7 @@ begin CLEAR => '0', CLK_EN => CLK_EN, --Internal Connection - LINK_PHASE => link_phase_S, + LINK_PHASE_IN => link_phase_S, SODA_CMD_STROBE_IN => soda_cmd_strobe_sodaclk_S, START_OF_SUPERBURST => start_of_superburst_S, SUPER_BURST_NR_IN => super_burst_nr_S, @@ -120,7 +111,6 @@ begin CLEAR => '0', CLK_EN => '1', --Internal Connection --- LAST_PACKET => last_packet_sent_S, EXPECTED_REPLY_IN => expected_reply_S, RX_DLM_IN => RX_DLM_IN, RX_DLM_WORD_IN => RX_DLM_WORD_IN, @@ -158,31 +148,15 @@ begin begin if rising_edge(SODACLK) then if( RESET = '1' ) then - link_phase_S <= 0; + link_phase_S <= (0 => '1', others => '0'); elsif (link_phase_S < 1) then link_phase_S <= link_phase_S + 1; else - link_phase_S <= 0; + link_phase_S <= (others => '0'); end if; end if; end process; ------------------------------------------------------------ --- Transmission history for reply-checking -- ------------------------------------------------------------ --- packet_history_proc : process(SYSCLK) --- begin --- if rising_edge(SYSCLK) then --- if( RESET = '1' ) then --- last_packet_sent_S <= c_NO_PACKET; --- elsif (start_of_superburst_S='1') then --- last_packet_sent_S <= c_BST_PACKET; --- elsif (soda_cmd_strobe_S='1') then --- last_packet_sent_S <= c_CMD_PACKET; --- end if; --- end if; --- end process; - --------------------------------------------------------- -- RegIO Statemachine --------------------------------------------------------- @@ -248,12 +222,14 @@ begin end case; end process TRANSFORM; -posedge_to_pulse1: posedge_to_pulse port map( - clock_in => SYSCLK, - clock_out => SODACLK, - en_clk => '1', - signal_in => soda_cmd_strobe_S, - pulse => soda_cmd_strobe_sodaclk_S); +soda_cmd_strobe_posedge_to_pulse: posedge_to_pulse + port map( + IN_CLK => SYSCLK, + OUT_CLK => SODACLK, + CLK_EN => '1', + SIGNAL_IN => soda_cmd_strobe_S, + PULSE_OUT => soda_cmd_strobe_sodaclk_S + ); --------------------------------------------------------- -- data handling -- @@ -274,8 +250,6 @@ posedge_to_pulse1: posedge_to_pulse port map( elsif( (store_wr = '1') and (SODA_ADDR_IN = "0001") ) then soda_cmd_strobe_S <= '0'; LEDregister_i <= SODA_DATA_IN; --- elsif( (store_wr = '1') and (SODA_ADDR_IN = "0010") ) then --- TEST_LINE_i <= SODA_DATA_IN; else soda_cmd_strobe_S <= '0'; end if; @@ -297,15 +271,12 @@ posedge_to_pulse1: posedge_to_pulse port map( buf_bus_data_out <= calib_register_S; elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then buf_bus_data_out <= LEDregister_i; --- elsif( (store_rd = '1') and (SODA_ADDR_IN = "0011") ) then --- buf_bus_data_out <= TEST_LINE_i; end if; end if; end process THE_READ_REG_PROC; -- output signals LEDS_OUT <= LEDregister_i(3 downto 0); --- TEST_LINE <= TEST_LINE_i(15 downto 0); SODA_DATA_OUT <= buf_bus_data_out; SODA_ACK_OUT <= bus_ack; diff --git a/source/soda_superburst_gen.vhd b/source/soda_superburst_gen.vhd index 2bad6c7..94f2553 100644 --- a/source/soda_superburst_gen.vhd +++ b/source/soda_superburst_gen.vhd @@ -2,7 +2,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; -use ieee.std_logic_signed.all; +use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; diff --git a/source/trb3_periph_sodaclient.vhd b/source/trb3_periph_sodaclient.vhd index d9c7e58..d6c282f 100644 --- a/source/trb3_periph_sodaclient.vhd +++ b/source/trb3_periph_sodaclient.vhd @@ -280,7 +280,7 @@ end generate; --------------------------------------------------------------------------- THE_ENDPOINT : trb_net16_endpoint_hades_full_handler generic map( - USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), +-- USE_CHANNEL => (c_YES,c_YES,c_NO,c_YES), REGIO_NUM_STAT_REGS => REGIO_NUM_STAT_REGS, --4, --16 stat reg REGIO_NUM_CTRL_REGS => REGIO_NUM_CTRL_REGS, --3, --8 cotrol reg ADDRESS_MASK => x"FFFF", diff --git a/source/trb3_periph_sodasource.vhd b/source/trb3_periph_sodasource.vhd index 3a91b43..ab2a589 100644 --- a/source/trb3_periph_sodasource.vhd +++ b/source/trb3_periph_sodasource.vhd @@ -216,12 +216,7 @@ architecture trb3_periph_sodasource_arch of trb3_periph_sodasource is --SODA signal SOB_S : std_logic := '0'; --- signal soda_cmd_word_S : std_logic_vector(31 downto 0) := (others => '0'); --- signal soda_cmd_strobe_S : std_logic := '0'; --- signal SOS_S : std_logic := '0'; --- signal super_burst_nr_S : std_logic_vector(30 downto 0) := (others => '0'); -- from super-burst-nr-generator --- signal dlm_word_S : std_logic_vector(7 downto 0) := (others => '0'); --- signal dlm_valid_S : std_logic; + begin --------------------------------------------------------------------------- @@ -454,10 +449,12 @@ THE_HUB : trb_net16_hub_base BUS_TIMEOUT_OUT(2) => open, BUS_TIMEOUT_OUT(3) => open, - BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, - BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, - BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out, - BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out, + BUS_DATA_IN(0*32+31 downto 0*32) => spimem_data_out, + BUS_DATA_IN(1*32+7 downto 1*32) => sci1_data_out, + BUS_DATA_IN(1*32+31 downto 1*32+8) => (others => '0'), + BUS_DATA_IN(2*32+7 downto 2*32) => sci2_data_out, + BUS_DATA_IN(2*32+31 downto 2*32+8) => (others => '0'), + BUS_DATA_IN(3*32+31 downto 3*32) => soda_data_out, BUS_DATAREADY_IN(0) => spimem_dataready_out, BUS_DATAREADY_IN(1) => sci1_ack, @@ -573,7 +570,7 @@ THE_SYNC_LINK : med_ecp3_sfp_sync_down THE_SOB_SOURCE : soda_start_of_burst_faker port map( - SYSCLK => clk_raw_internal, + SYSCLK => soda_rx_clock_half, --clk_raw_internal, RESET => reset_i, SODA_BURST_PULSE_OUT => SOB_S ); -- 2.43.0