From 298b362a1779bc7fefd725b83e9c0ad14f3b964e Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 17 May 2022 15:02:29 +0200 Subject: [PATCH] first changes to implement DS to TOMcat --- prototype/config.vhd | 50 +++++++----- prototype/tomcat_template.prj | 32 +++++--- prototype/tomcat_template.vhd | 149 +++++++++++++++++++++++----------- 3 files changed, 152 insertions(+), 79 deletions(-) diff --git a/prototype/config.vhd b/prototype/config.vhd index 6d9e431..d75e230 100644 --- a/prototype/config.vhd +++ b/prototype/config.vhd @@ -8,11 +8,39 @@ package config is ------------------------------------------------------------------------------ --Begin of design configuration ------------------------------------------------------------------------------ ---set to 0 for backplane serdes, set to 1 for SFP serdes - constant SERDES_NUM : integer := 1; +-- FPGA type + constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 + + constant FPGA_SIZE : string := "85KUM"; + +-- Link speed + constant LINK_SPEED : integer := 125; -- 125: 1.25Gbps, 200: 2.00Gbps + +-- select channel 0 or 1 in DCU + constant SERDES_NUM : integer := 0; + +-- Address settings + constant INIT_ADDRESS : std_logic_vector := x"F770"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"30"; + +-- I/O specific + constant INCLUDE_UART : integer := c_NO; --300 slices + constant INCLUDE_SPI : integer := c_NO; --300 slices + constant INCLUDE_LCD : integer := c_NO; --800 slices + constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices + +-- input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 + constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 + constant TRIG_GEN_INPUT_NUM : integer := 32; + constant TRIG_GEN_OUTPUT_NUM : integer := 4; + constant MONITOR_INPUT_NUM : integer := 32; + +------------------------------------------------------------------------------------------------- +------------------------------------------------------------------------------------------------- +------------------------------------------------------------------------------------------------- --TDC settings - constant FPGA_TYPE : integer := 5; --3: ECP3, 5: ECP5 constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement constant NUM_TDC_CHANNELS : integer range 1 to 65 := 5; -- number of tdc channels per module constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 2; --the nearest power of two, for convenience reasons @@ -40,23 +68,7 @@ package config is --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; ---Address settings - constant INIT_ADDRESS : std_logic_vector := x"F770"; - constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"30"; - constant INCLUDE_UART : integer := c_NO; --300 slices - constant INCLUDE_SPI : integer := c_NO; --300 slices - constant INCLUDE_LCD : integer := c_NO; --800 slices - constant INCLUDE_DEBUG_INTERFACE: integer := c_NO; --300 slices - - --input monitor and trigger generation logic - constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; --400 slices @32->2 - constant INCLUDE_STATISTICS : integer := c_NO; --1300 slices, 1 RAM @32 - constant TRIG_GEN_INPUT_NUM : integer := 32; - constant TRIG_GEN_OUTPUT_NUM : integer := 4; - constant MONITOR_INPUT_NUM : integer := 32; - - constant FPGA_SIZE : string := "85KUM"; ------------------------------------------------------------------------------ --End of design configuration diff --git a/prototype/tomcat_template.prj b/prototype/tomcat_template.prj index 4ff4008..068408d 100644 --- a/prototype/tomcat_template.prj +++ b/prototype/tomcat_template.prj @@ -123,23 +123,29 @@ add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" #Media interface -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_rx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp5_sfp_sync_RS.vhd" ######################################### -#channel 1, SFP -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_1/serdes_sync_0.vhd" -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_inv/serdes_sync_0.vhd" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_inv/serdes_sync_0.vhd" +# 125MHz files +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_125M.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_125M_inv_5G/serdes_sync_0_125M.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_125M_softlogic.v" +# 200MHz files +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs_200M.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/chan0_0_200M_inv_5G/serdes_sync_0_200M.vhd" +add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_200M_softlogic.v" ########################################## -add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" -add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" +#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs.vhd" +#add_file -verilog -lib work "../../trbnet/media_interfaces/ecp5/serdes_sync_0_softlogic.v" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp5/pcs2.vhd" diff --git a/prototype/tomcat_template.vhd b/prototype/tomcat_template.vhd index bf7a0ce..af307f6 100644 --- a/prototype/tomcat_template.vhd +++ b/prototype/tomcat_template.vhd @@ -8,7 +8,7 @@ use work.config.all; use work.trb_net_std.all; use work.trb_net_components.all; use work.trb3_components.all; -use work.med_sync_define.all; +use work.med_sync_define_RS.all; entity tomcat_template is port( @@ -63,7 +63,6 @@ architecture arch of tomcat_template is signal clk_sys : std_logic; signal clk_full : std_logic; signal clk_full_osc : std_logic; - signal clk_cal : std_logic; signal GSR_N : std_logic; signal reset_i : std_logic; signal clear_i : std_logic; @@ -97,26 +96,17 @@ architecture arch of tomcat_template is attribute syn_preserve of GSR_N : signal is true; signal testctr : unsigned(31 downto 0); - -begin -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -THE_TESTCTR_PROC: process( clk_cal ) -begin - if( rising_edge(clk_cal) ) then - testctr <= testctr + 1; - end if; -end process THE_TESTCTR_PROC; + signal link_clock : std_logic; + signal init_quad : std_logic; + signal master_clk_i : std_logic; + signal tx_pll_lol_dual_a : std_logic; + signal tx_clk_avail_i : std_logic; + signal word_sync_i : std_logic; + signal tx_pcs_rst_i : std_logic; + signal link_tx_ready_i : std_logic; -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger" --- at least 100ns! - -INTCOM(9 downto 1) <= std_logic_vector(testctr(8 downto 0)); - -TIMING_TEST <= std_logic(testctr(31)); +begin ------------------------------------------------------------------------------- -- Clock & Reset Handling @@ -137,45 +127,110 @@ TIMING_TEST <= std_logic(testctr(31)); DEBUG_OUT => debug_clock_reset ); - THE_CAL_PLL : entity work.pll_in125_out50 - port map( - CLKI => CLK_125, - CLKOP => clk_cal - ); + init_quad <= not GSR_N; + + -- select link speed, wrong values are catched in media interface + link_clock <= CLK_125 when (LINK_SPEED = 125) else + clk_full_osc when (LINK_SPEED = 200) else + '0'; ------------------------------------------------------------------------------- -- TrbNet Uplink ------------------------------------------------------------------------------- - THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync + THE_MEDIA_INTERFACE : entity work.med_ecp5_sfp_sync_RS generic map( SERDES_NUM => 0, - IS_SYNC_SLAVE => c_YES + IS_MODE => c_IS_SLAVE ) port map( - CLK_REF_FULL => clk_full_osc, - CLK_INTERNAL_FULL => clk_full_osc, - SYSCLK => clk_sys, - RESET => reset_i, - CLEAR => clear_i, - --Internal Connection - MEDIA_MED2INT => med2int(0), - MEDIA_INT2MED => int2med(0), - --Sync operation - RX_DLM => open, - RX_DLM_WORD => open, - TX_DLM => open, - TX_DLM_WORD => open, + -- Clocks and reset + CLK_REF_FULL => link_clock, + SYSCLK => clk_sys, + CLEAR => init_quad, + RESET => reset_i, + -- Media Interface TX/RX + MEDIA_MED2INT => med2int(0), + MEDIA_INT2MED => int2med(0), + -- komma operation + RX_DLM_OUT => open, + RX_DLM_WORD_OUT => open, + TX_DLM_IN => '0', + TX_DLM_WORD_IN => x"00", + RX_RST_OUT => open, + RX_RST_WORD_OUT => open, + TX_RST_IN => '0', + TX_RST_WORD_IN => x"00", + -- phase measurement + PING_OUT => open, + PONG_OUT => open, + PONG_CLK_OUT => open, + -- sync operation + WORD_SYNC_IN => word_sync_i, + WORD_SYNC_OUT => word_sync_i, + MASTER_CLK_IN => master_clk_i, + MASTER_CLK_OUT => master_clk_i, + LINK_TX_NULL_IN => '0', + LINK_RX_NULL_OUT => open, + TX_PLL_LOL_OUT => tx_pll_lol_dual_a, + TX_CLK_AVAIL_OUT => tx_clk_avail_i, + TX_PCS_RST_IN => tx_pcs_rst_i, + SYNC_TX_PLL_IN => '0', + LINK_TX_READY_IN => link_tx_ready_i, + DISABLE_LINK_IN => '0', + WAP_REQUESTED_IN => x"0", --SFP Connection - SD_PRSNT_N_IN => SFP_MOD_0, - SD_LOS_IN => SFP_LOS, - SD_TXDIS_OUT => SFP_TX_DIS, + SD_PRSNT_N_IN => SFP_MOD_0, + SD_LOS_IN => SFP_LOS, + SD_TXDIS_OUT => SFP_TX_DIS, --Control Interface - BUS_RX => bussci_rx, - BUS_TX => bussci_tx, + BUS_RX => bussci_rx, + BUS_TX => bussci_tx, -- Status and control port - STAT_DEBUG => med_stat_debug(63 downto 0), - CTRL_DEBUG => open + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open, + DEBUG_OUT => open ); + + THE_MAIN_TX_RST: main_tx_reset_RS + port map ( + CLEAR => init_quad, + CLK_REF => link_clock, + TX_PLL_LOL_QD_A_IN => tx_pll_lol_dual_a, + TX_PLL_LOL_QD_B_IN => '0', + TX_PLL_LOL_QD_C_IN => '0', + TX_PLL_LOL_QD_D_IN => '0', + TX_CLOCK_AVAIL_IN => tx_clk_avail_i, + TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, + SYNC_TX_QUAD_OUT => open, + LINK_TX_READY_OUT => link_tx_ready_i, + STATE_OUT => open + ); + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +THE_TESTCTR_PROC: process( clk_sys ) +begin + if( rising_edge(clk_sys) ) then + testctr <= testctr + 1; + end if; +end process THE_TESTCTR_PROC; + +------------------------------------------------------------------------------- +------------------------------------------------------------------------------- +trigger_in_i <= INTCOM(0); -- BUG: we need a "timing trigger" +-- at least 100ns! + +INTCOM(9 downto 1) <= std_logic_vector(testctr(8 downto 0)); + +TIMING_TEST <= std_logic(testctr(31)); ------------------------------------------------------------------------------- -- Endpoint -- 2.43.0