From 2a24f86d7a47818b46a94f2700142ea5062b4026 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 15 Jun 2022 13:43:55 +0200 Subject: [PATCH] adjust DiRICH trigger generation possibility to FF, similar to DiRICH5s1 --- dirich/code/input_multiplicity_trigger.vhd | 116 +++++++++++++++------ dirich/dirich.lpf | 8 ++ dirich/dirich.vhd | 4 +- 3 files changed, 95 insertions(+), 33 deletions(-) diff --git a/dirich/code/input_multiplicity_trigger.vhd b/dirich/code/input_multiplicity_trigger.vhd index 6577f1f..1b94637 100644 --- a/dirich/code/input_multiplicity_trigger.vhd +++ b/dirich/code/input_multiplicity_trigger.vhd @@ -22,13 +22,24 @@ end entity; architecture behaviour of input_multiplicity_trigger is signal stretched_input : std_logic_vector (31 downto 0) := x"00000000"; + signal stretched_input_q : std_logic_vector (31 downto 0) := x"00000000"; signal multiplicity : std_logic_vector ( 4 downto 0) := "00000"; - signal sum_stretched_input : std_logic_vector (5 downto 0) := "000000"; signal trigger_direct : std_logic := '0'; signal trigger_stretch : std_logic := '0'; - + signal stretch : std_logic_vector(3 downto 0) := "0000"; signal stretch_trigSign : std_logic_vector(3 downto 0) := "0000"; + + signal invert_trigOut : std_logic := '0'; + signal enable_trigOut : std_logic := '0'; + + signal invert : std_logic_vector(31 downto 0); + signal enable : std_logic_vector(31 downto 0); + + signal add_0, add_1, add_2 : std_logic_vector (5 downto 0) := "000000"; + signal add_3, add_4, add_5 : std_logic_vector (5 downto 0) := "000000"; + signal add_6, add_7, add_all : std_logic_vector (5 downto 0) := "000000"; + signal add_all_0, add_all_1 : std_logic_vector (5 downto 0) := "000000"; begin @@ -38,33 +49,60 @@ begin CLK => CLK, RESET => RESET, INPUT => INPUT(i), + INVERT => invert(i), + ENABLE => enable(i), OUTPUT => stretched_input(i), STRETCH => stretch ); + -- Synch eventually asynchr. output signal to CLK + stretched_input_q(i) <= stretched_input(i) when rising_edge(CLK); end generate GEN_STRETCH; + + + THE_MULT_TRIGGER : process + begin + wait until rising_edge(CLK); - - sum_stretched_input <= ("00000" & stretched_input( 0)) + ("00000" & stretched_input( 1)) - + ("00000" & stretched_input( 2)) + ("00000" & stretched_input( 3)) - + ("00000" & stretched_input( 4)) + ("00000" & stretched_input( 5)) - + ("00000" & stretched_input( 6)) + ("00000" & stretched_input( 7)) - + ("00000" & stretched_input( 8)) + ("00000" & stretched_input( 9)) - + ("00000" & stretched_input(10)) + ("00000" & stretched_input(11)) - + ("00000" & stretched_input(12)) + ("00000" & stretched_input(13)) - + ("00000" & stretched_input(14)) + ("00000" & stretched_input(15)) - + ("00000" & stretched_input(16)) + ("00000" & stretched_input(17)) - + ("00000" & stretched_input(18)) + ("00000" & stretched_input(19)) - + ("00000" & stretched_input(20)) + ("00000" & stretched_input(21)) - + ("00000" & stretched_input(22)) + ("00000" & stretched_input(23)) - + ("00000" & stretched_input(24)) + ("00000" & stretched_input(25)) - + ("00000" & stretched_input(26)) + ("00000" & stretched_input(27)) - + ("00000" & stretched_input(28)) + ("00000" & stretched_input(29)) - + ("00000" & stretched_input(30)) + ("00000" & stretched_input(31)); - - - trigger_direct <= '1' when multiplicity <= std_logic_vector(sum_stretched_input) else - '0'; - + if RESET = '1' then + trigger_direct <= '0'; + else + -- split adder into two stages to relay timing + add_0 <= ( ("00000" & stretched_input_q( 0)) + ("00000" & stretched_input_q( 1)) + + ("00000" & stretched_input_q( 2)) + ("00000" & stretched_input_q( 3))); + + add_1 <= ( ("00000" & stretched_input_q( 4)) + ("00000" & stretched_input_q( 5)) + + ("00000" & stretched_input_q( 6)) + ("00000" & stretched_input_q( 7))); + + add_2 <= ( ("00000" & stretched_input_q( 8)) + ("00000" & stretched_input_q( 9)) + + ("00000" & stretched_input_q(10)) + ("00000" & stretched_input_q(11))); + + add_3 <= ( ("00000" & stretched_input_q(12)) + ("00000" & stretched_input_q(13)) + + ("00000" & stretched_input_q(14)) + ("00000" & stretched_input_q(15))); + + add_4 <= ( ("00000" & stretched_input_q(16)) + ("00000" & stretched_input_q(17)) + + ("00000" & stretched_input_q(18)) + ("00000" & stretched_input_q(19))); + + add_5 <= ( ("00000" & stretched_input_q(20)) + ("00000" & stretched_input_q(21)) + + ("00000" & stretched_input_q(22)) + ("00000" & stretched_input_q(23))); + + add_6 <= ( ("00000" & stretched_input_q(24)) + ("00000" & stretched_input_q(25)) + + ("00000" & stretched_input_q(26)) + ("00000" & stretched_input_q(27))); + + add_7 <= ( ("00000" & stretched_input_q(28)) + ("00000" & stretched_input_q(29)) + + ("00000" & stretched_input_q(30)) + ("00000" & stretched_input_q(31))); + + add_all_0 <= add_0 + add_1 + add_2 + add_3; + add_all_1 <= add_4 + add_5 + add_6 + add_7; + + add_all <= add_0 + add_1; + + if ( multiplicity <= std_logic_vector(add_all) ) then + trigger_direct <= '1'; + else + trigger_direct <= '0'; + end if; + end if; + end process; THE_TRIGGER_SIGNAL_Stretch : entity work.input_signal_stretcher port map ( @@ -72,6 +110,8 @@ begin RESET => RESET, INPUT => trigger_direct, OUTPUT => trigger_stretch, + INVERT => invert_trigOut, + ENABLE => enable_trigOut, STRETCH => stretch_trigSign ); @@ -87,11 +127,19 @@ begin if BUS_RX.write = '1' then BUS_TX.ack <= '1'; - case BUS_RX.addr(0 downto 0) is - when "0" => + case BUS_RX.addr(1 downto 0) is + when "00" => stretch <= BUS_RX.data(3 downto 0); stretch_trigSign <= BUS_RX.data(7 downto 4); multiplicity <= BUS_RX.data(20 downto 16); + enable_trigOut <= BUS_RX.data(21); + invert_trigOut <= BUS_RX.data(22); + + when "01" => + invert <= BUS_RX.data; + + when "10" => + enable <= BUS_RX.data; when others => BUS_TX.ack <= '0'; @@ -99,17 +147,23 @@ begin end case; elsif BUS_RX.read = '1' then BUS_TX.ack <= '1'; - case BUS_RX.addr(0 downto 0) is - when "0" => BUS_TX.data( 3 downto 0) <= stretch; + case BUS_RX.addr(1 downto 0) is + when "00" => BUS_TX.data( 3 downto 0) <= stretch; BUS_TX.data( 7 downto 4) <= stretch_trigSign; BUS_TX.data(15 downto 8) <= (others => '0'); BUS_TX.data(20 downto 16) <= multiplicity; - BUS_TX.data(31 downto 21) <= (others => '0'); - + BUS_TX.data(21) <= enable_trigOut; + BUS_TX.data(22) <= invert_trigOut; + BUS_TX.data(31 downto 23) <= (others => '0'); + + when "01" => BUS_TX.data <= invert; + + when "10" => BUS_TX.data <= enable; + when others => BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; end case; end if; end process; - + end architecture; diff --git a/dirich/dirich.lpf b/dirich/dirich.lpf index f5287ed..6b65df6 100644 --- a/dirich/dirich.lpf +++ b/dirich/dirich.lpf @@ -31,6 +31,14 @@ BLOCK PATH TO PORT "TEST_LINE*"; MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_SCI_READER/PROC_SCI_CTRL.BUS_TX*" 10 ns; MULTICYCLE TO CELL "THE_MEDIA_INTERFACE/THE_MED_CONTROL/THE_TX/STAT_REG_OUT*" 10 ns; +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/THE_TRIGGER_SIGNAL_Stretch/INPUT*" 4 X; +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/THE_TRIGGER_SIGNAL_Stretch/INVERT*" 4 X; +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/THE_TRIGGER_SIGNAL_Stretch/ENABLE*" 4 X; + +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/GEN_STRETCH*/THE_TRIGGER_Stretch/INPUT*" 4 X; +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/GEN_STRETCH*/THE_TRIGGER_Stretch/INVERT*" 4 X; +MULTICYCLE TO CELL "gen_MULT_TRIG/THE_MULT_TRIG/GEN_STRETCH*/THE_TRIGGER_Stretch/ENABLE*" 4 X; + GSR_NET NET "clear_i"; # LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/DCU0_inst" SITE "DCU0" ; diff --git a/dirich/dirich.vhd b/dirich/dirich.vhd index 7ee7221..dc70823 100644 --- a/dirich/dirich.vhd +++ b/dirich/dirich.vhd @@ -268,7 +268,7 @@ THE_CAL_PLL : entity work.pll_in3125_out50 generic map( PORT_NUMBER => 6, PORT_ADDRESSES => (0 => x"d000", 1 => x"b000", 2 => x"d300", 3 => x"a000", 4 => x"c000", 5 => x"e000", others => x"0000"), - PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 1, others => 0), + PORT_ADDR_MASK => (0 => 12, 1 => 9, 2 => 1, 3 => 8, 4 => 12, 5 => 2, others => 0), PORT_MASK_ENABLE => 1 ) port map( @@ -409,7 +409,7 @@ SIG(4) <= signal_trigger_unstretched; TEST_LINE(2) <= hdr_io(9); --Debug_triggerSignalFromInput - --TEST_LINE(3) <= signal_trigger_out; + TEST_LINE(3) <= signal_trigger_out; -- TEST_LINE(8 downto 1) <= hdr_io(7 downto 0); -- TEST_LINE(14 downto 11) <= time_counter(31 downto 28); -- TEST_LINE(14 downto 1) <= med2int(0).stat_op(13) & clear_i & reset_i & debug_clock_reset(10 downto 6) & "00" & link_stat_out & link_stat_in_reg & debug_clock_reset(1 downto 0) ; -- 2.43.0