From 2a2559f0b7ceaa422f5aad3da4192e207a907919 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 24 Jul 2012 17:47:49 +0000 Subject: [PATCH] *** empty log message *** --- trb3_gbe/compile_central_frankfurt.pl | 6 +-- trb3_gbe/trb3_central.p2t | 5 ++- trb3_gbe/trb3_central.prj | 4 +- trb3_gbe/trb3_central.vhd | 61 ++++++++++++++++++++------- trb3_gbe/trb3_central_constraints.lpf | 2 +- 5 files changed, 54 insertions(+), 24 deletions(-) diff --git a/trb3_gbe/compile_central_frankfurt.pl b/trb3_gbe/compile_central_frankfurt.pl index 47f63c0..6b23a7b 100755 --- a/trb3_gbe/compile_central_frankfurt.pl +++ b/trb3_gbe/compile_central_frankfurt.pl @@ -108,11 +108,11 @@ execute($c); my $tpmap = $TOPNAME . "_map" ; -$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +system("mv $TOPNAME.ncd guidefile.ncd"); +# $c=qq|$lattice_path/ispfpga/bin/lin/map -g guidefile.ncd -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; +$c=qq|$lattice_path/ispfpga/bin/lin/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; execute($c); -system("rm $TOPNAME.ncd"); - $c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; execute($c); diff --git a/trb3_gbe/trb3_central.p2t b/trb3_gbe/trb3_central.p2t index c037b03..c54c097 100644 --- a/trb3_gbe/trb3_central.p2t +++ b/trb3_gbe/trb3_central.p2t @@ -4,9 +4,10 @@ -n 1 -y -s 12 --t 12 +-t 13 -c 1 -e 2 +#-g guidefile.ncd -m nodelist.txt # -w # -i 6 @@ -17,4 +18,4 @@ # -c 0 # -e 0 # --exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1: +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1 diff --git a/trb3_gbe/trb3_central.prj b/trb3_gbe/trb3_central.prj index b27e1a0..fd09e78 100644 --- a/trb3_gbe/trb3_central.prj +++ b/trb3_gbe/trb3_central.prj @@ -88,8 +88,8 @@ add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vh add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" -add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd" +add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" +#add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe_nologic.vhd" add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd" diff --git a/trb3_gbe/trb3_central.vhd b/trb3_gbe/trb3_central.vhd index 93b26f3..416cd22 100644 --- a/trb3_gbe/trb3_central.vhd +++ b/trb3_gbe/trb3_central.vhd @@ -257,7 +257,9 @@ signal gsc_busy : std_logic; signal mc_unique_id : std_logic_vector(63 downto 0); signal trb_reset_in : std_logic; signal reset_via_gbe : std_logic; - +signal timer_ticks : std_logic_vector(1 downto 0); +signal reset_via_gbe_delayed : std_logic_vector(2 downto 0); +signal reset_i_temp : std_logic; begin --------------------------------------------------------------------------- @@ -277,15 +279,23 @@ THE_RESET_HANDLER : trb_net_reset_handler SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) - TRB_RESET_IN => trb_reset_in, -- TRBnet reset signal (SYSCLK) + TRB_RESET_IN => '0', -- TRBnet reset signal (SYSCLK) CLEAR_OUT => clear_i, -- async reset out, USE WITH CARE! - RESET_OUT => reset_i, -- synchronous reset out (SYSCLK) + RESET_OUT => reset_i_temp, -- synchronous reset out (SYSCLK) DEBUG_OUT => open ); -trb_reset_in <= med_stat_op(4*16+13) or reset_via_gbe; - +trb_reset_in <= med_stat_op(4*16+13) or reset_via_gbe_delayed(2); +reset_i <= reset_i_temp or trb_reset_in; +process begin + wait until rising_edge(clk_100_i); + if reset_i = '1' then + reset_via_gbe_delayed <= "000"; + elsif timer_ticks(0) = '1' then + reset_via_gbe_delayed <= reset_via_gbe_delayed(1 downto 0) & reset_via_gbe; + end if; + end process; --------------------------------------------------------------------------- -- Clock Handling @@ -437,6 +447,8 @@ gen_normal_hub : if USE_ETHERNET = c_NO generate COMMON_STAT_REGS => common_stat_regs, COMMON_CTRL_REGS => common_ctrl_regs, MY_ADDRESS_OUT => my_address, + TIMER_TICKS_OUT => timer_ticks, + --REGIO INTERFACE REGIO_ADDR_OUT => regio_addr_out, REGIO_READ_ENABLE_OUT => regio_read_enable_out, @@ -459,10 +471,13 @@ gen_normal_hub : if USE_ETHERNET = c_NO generate end generate; gen_ethernet_hub : if USE_ETHERNET = c_YES generate ---If the injected slow control should be visible to the network below this hub only: --- MII_IS_UPLINK => (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0); --- MII_IS_DOWNLINK => (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0); --- MII_IS_UPLINK_ONLY => (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0); +-- Be careful when setting the MII_NUMBER and MII_IS_* generics! +-- for MII_NUMBER=5 (4 downlinks, 1 uplink): +-- port 0,1,2,3: downlinks to other FPGA +-- port 4: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL +-- port 5: SCTRL channel on uplink to CTS +-- port 6: SCTRL channel from GbE interface + THE_HUB: trb_net16_hub_streaming_port_sctrl @@ -471,10 +486,17 @@ gen_ethernet_hub : if USE_ETHERNET = c_YES generate --IBUF_SECURE_MODE => c_YES, INIT_ADDRESS => x"F305", MII_NUMBER => 5, - MII_IS_UPLINK => (4 => 1, 5 => 1, 6 => 1, others => 0), - MII_IS_DOWNLINK => (0 => 1, 1 => 1, 2 => 1, 3 => 1, 4 => 1, others => 0), - MII_IS_UPLINK_ONLY => (5 => 1, 6 => 1, others => 0), - + + --optical link SFP1 is uplink on all channels (e.g. connect a Hub) +-- MII_IS_UPLINK => (0,0,0,0,1,1,1,0,0,0,0,0,0,0,0,0,0), +-- MII_IS_DOWNLINK => (1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0), +-- MII_IS_UPLINK_ONLY => (0,0,0,0,0,1,1,0,0,0,0,0,0,0,0,0,0), + + --optical link SFP1 is uplink on TRG & IPU and downlink on sctrl (e.g. connect a CTS, sctrl via GbE) + MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), + MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), + MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), + USE_ONEWIRE => c_YES, HARDWARE_VERSION => x"90000000", INIT_ENDPOINT_ID => x"0005", @@ -534,9 +556,10 @@ gen_ethernet_hub : if USE_ETHERNET = c_YES generate ONEWIRE => TEMPSENS, ONEWIRE_MONITOR_IN => open, MY_ADDRESS_OUT => my_address, - - UNIQUE_ID_OUT => mc_unique_id, - + TIMER_TICKS_OUT => timer_ticks, + UNIQUE_ID_OUT => mc_unique_id, + EXTERNAL_SEND_RESET => reset_via_gbe, + REGIO_ADDR_OUT => regio_addr_out, REGIO_READ_ENABLE_OUT => regio_read_enable_out, REGIO_WRITE_ENABLE_OUT => regio_write_enable_out, @@ -891,6 +914,12 @@ LED_YELLOW <= link_ok; --debug(3); TEST_LINE(31 downto 10) <= (others => '0'); +-- FPGA1_CONNECTOR(0) <= '0'; + FPGA2_CONNECTOR(0) <= '0'; +-- FPGA3_CONNECTOR(0) <= '0'; +-- FPGA4_CONNECTOR(0) <= '0'; + + --------------------------------------------------------------------------- -- Test Circuits --------------------------------------------------------------------------- diff --git a/trb3_gbe/trb3_central_constraints.lpf b/trb3_gbe/trb3_central_constraints.lpf index 2c820cf..b32142d 100644 --- a/trb3_gbe/trb3_central_constraints.lpf +++ b/trb3_gbe/trb3_central_constraints.lpf @@ -141,7 +141,7 @@ UGROUP "gbe_rx_tx" REGION "GBE_REGION" "R40C2D" 35 40 DEVSIZE; -REGION "MED0" "R75C2D" 30 28 DEVSIZE; +REGION "MED0" "R75C2D" 30 35 DEVSIZE; LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; FREQUENCY NET "gen_ethernet_hub_GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; FREQUENCY NET "gen_ethernet_hub_GBE/serdes_clk_125_c" 125.000000 MHz ; -- 2.43.0