From 2a4643f8e4e37ace9bcc38fba6bd9b0300311aa8 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Thu, 3 Feb 2022 13:07:02 +0100 Subject: [PATCH] for testing: SCI bug workaround added --- media_interfaces/med_ecp3_sfp_sync_all_RS.vhd | 27 ++- media_interfaces/sync/main_rx_reset_RS.vhd | 33 ++-- media_interfaces/sync/med_sync_control_RS.vhd | 2 + media_interfaces/sync/med_sync_define_RS.vhd | 1 + media_interfaces/sync/sci_reader_RS.vhd | 187 +++++++++--------- 5 files changed, 142 insertions(+), 108 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd index 42879e1..f769ac6 100644 --- a/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd +++ b/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd @@ -103,6 +103,11 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal sci_write_i : std_logic; signal wa_position_i : std_logic_vector(15 downto 0) := x"FFFF"; + signal wap_requested_i : std_logic_vector(15 downto 0); + signal wap_req_i : std_logic_vector(3 downto 0); + signal wap_req_all : std_logic; +-- signal wap_req_all_q : std_logic; + signal wap_req_all_q : std_logic_vector(2 downto 0); signal stat_rx_control_i : std_logic_vector(4*32-1 downto 0); signal stat_tx_control_i : std_logic_vector(4*32-1 downto 0); @@ -139,12 +144,9 @@ architecture med_ecp3_sfp_sync_all_RS_arch of med_ecp3_sfp_sync_all_RS is signal word_sync_sel : std_logic; signal link_active_i : std_logic_vector(3 downto 0); - - signal wap_requested_i : std_logic_vector(15 downto 0); signal rx_index_i : std_logic_vector(3 downto 0); signal dlm_result_i : std_logic_vector(4*32-1 downto 0); - signal quad_mode : integer range 0 to 100; @@ -466,6 +468,7 @@ gen_control : for i in 0 to 3 generate TX_PLL_LOL_IN => TX_PLL_LOL_IN, WA_POSITION_IN => wa_position_i(i*4+3 downto i*4), WAP_REQUESTED_IN => wap_requested_i(i*4+3 downto i*4), + WAP_REQ_OUT => wap_req_i(i), -- control signals to SerDes RX_SERDES_RST => rx_serdes_rst(i), RX_PCS_RST => rx_pcs_rst(i), @@ -509,6 +512,7 @@ gen_control : for i in 0 to 3 generate rx_serdes_rst(i) <= '1'; -- keep in reset rx_pcs_rst(i) <= '1'; -- keep in reset rx_index_i(i) <= '0'; + wap_req_i(i) <= '0'; MEDIA_MED2INT(i).dataready <= '0'; MEDIA_MED2INT(i).tx_read <= '1'; MEDIA_MED2INT(i).stat_op <= x"0007"; @@ -537,6 +541,20 @@ end generate; RX_DLM_OUT <= rx_dlm_i; DLM_RESULT_OUT <= dlm_result_i; + wap_req_all <= wap_req_i(0) or wap_req_i(1) or wap_req_i(2) or wap_req_i(3); + +-- SYNC_REQ_0: entity work.signal_sync +-- generic map( WIDTH => 1 ) +-- port map( +-- RESET => RESET, +-- CLK0 => CLK_REF_FULL, +-- CLK1 => SYSCLK, +-- D_IN(0) => wap_req_all, +-- D_OUT(0) => wap_req_all_q +-- ); + + wap_req_all_q(2 downto 0) <= wap_req_all_q(1 downto 0) & wap_req_all when rising_edge(SYSCLK); + THE_SCI_READER : entity work.sci_reader_RS port map( CLK => SYSCLK, @@ -550,6 +568,9 @@ end generate; SCI_WR => sci_write_i, -- WAP WA_POS_OUT => wa_position_i, +-- WA_REQ_IN => wap_req_all_q, + WA_REQ_IN => wap_req_all_q(2), + WA_ACK_OUT => open, --Slowcontrol BUS_RX => BUS_RX, BUS_TX => BUS_TX, diff --git a/media_interfaces/sync/main_rx_reset_RS.vhd b/media_interfaces/sync/main_rx_reset_RS.vhd index f2b2eda..5659379 100644 --- a/media_interfaces/sync/main_rx_reset_RS.vhd +++ b/media_interfaces/sync/main_rx_reset_RS.vhd @@ -13,7 +13,6 @@ entity main_rx_reset_RS is LOS_IN : in std_logic; SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; - WAP_ACK_IN : in std_logic; -- outputs WAP_REQ_OUT : out std_logic; RX_SERDES_RST_OUT : out std_logic; @@ -75,7 +74,6 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; rx_sm <= powerup; STATE_OUT <= x"f"; @@ -95,7 +93,6 @@ begin RX_SERDES_RST_OUT <= '0'; -- needed for RX_LOS to be active RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; -- if( (pll_lol_s = '1') or (los_s = '1') or (sd_los_s = '1') ) then if( (pll_lol_s = '1') or (sd_los_s = '1') ) then cnt <= (others => '0'); @@ -113,7 +110,6 @@ begin RX_SERDES_RST_OUT <= '1'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; if( cnt = Tshort ) then cnt <= (others => '0'); rx_sm <= WAIT_CDR_LOCK; @@ -126,7 +122,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; if( cnt = Tcdr ) then cnt <= (others => '0'); rx_sm <= TEST_CDR; @@ -139,7 +134,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; if( cdr_lol_s = '1' ) then cnt <= (others => '0'); rx_sm <= APPLY_CDR_RST; @@ -157,7 +151,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '1'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; if( cnt = Tshort ) then cnt <= (others => '0'); rx_sm <= WAIT_RXPCS_LOCK; @@ -170,7 +163,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '1'; if( cnt = Tviol ) then cnt <= (others => '0'); rx_sm <= TEST_RXPCS; @@ -183,7 +175,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '1'; if( (lsm_s = '0') or (cv_s = '1') ) then cnt <= (others => '0'); rx_sm <= APPLY_RXPCS_RST; @@ -201,21 +192,30 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; cnt <= (others => '0'); - if( wap_zero_s = '1' ) then - rx_sm <= NORMAL_OP; + if( cnt = Tshort ) then + cnt <= (others => '0'); + if( wap_zero_s = '1' ) then + rx_sm <= NORMAL_OP; + else +-- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK + rx_sm <= APPLY_CDR_RST; + end if; else --- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK - rx_sm <= APPLY_CDR_RST; + cnt <= cnt + 1; end if; +-- if( wap_zero_s = '1' ) then +-- rx_sm <= NORMAL_OP; +-- else +---- rx_sm <= APPLY_RXPCS_RST; -- DOESNT WORK +-- rx_sm <= APPLY_CDR_RST; +-- end if; when NORMAL_OP => STATE_OUT <= x"8"; RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '1'; - WAP_REQ_OUT <= '0'; cnt <= (others => '0'); if( (lsm_s = '0') or (cv_s = '1') ) then -- DANGEROUS rx_sm <= APPLY_RXPCS_RST; @@ -227,7 +227,6 @@ begin RX_SERDES_RST_OUT <= '0'; RX_PCS_RST_OUT <= '0'; LINK_RX_READY_OUT <= '0'; - WAP_REQ_OUT <= '0'; rx_sm <= POWERUP; end case; @@ -243,4 +242,6 @@ begin end if; end process rx_reset_proc; + WAP_REQ_OUT <= '1' when ((rx_sm = WAIT_RXPCS_LOCK) or (rx_sm = TEST_RXPCS)) else '0'; + end architecture; diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index 86f6b66..9ea5a1f 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -32,6 +32,7 @@ entity med_sync_control_RS is TX_PLL_LOL_IN : in std_logic; -- wired'or from all QUADs WA_POSITION_IN : in std_logic_vector(3 downto 0); -- WordAlignment Position WAP_REQUESTED_IN : in std_logic_vector(3 downto 0); -- TESTTESTTEST + WAP_REQ_OUT : out std_logic; -- control signals to SerDes RX_SERDES_RST : out std_logic; -- reset RX (SerDes + CDR) RX_PCS_RST : out std_logic; -- reset RX (PCS) @@ -139,6 +140,7 @@ begin SD_LOS_IN => SFP_LOS_IN, WAP_ZERO_IN => is_wap_zero_i, -- outputs + WAP_REQ_OUT => WAP_REQ_OUT, RX_SERDES_RST_OUT => rx_serdes_rst_i, -- CLK_REF based RX_PCS_RST_OUT => rx_pcs_rst_i, -- CLK_REF based LINK_RX_READY_OUT => link_rx_ready_i, --LINK_RX_READY_OUT, -- CLK_REF based diff --git a/media_interfaces/sync/med_sync_define_RS.vhd b/media_interfaces/sync/med_sync_define_RS.vhd index 0f8570b..d616d68 100644 --- a/media_interfaces/sync/med_sync_define_RS.vhd +++ b/media_interfaces/sync/med_sync_define_RS.vhd @@ -37,6 +37,7 @@ component main_rx_reset_RS is SD_LOS_IN : in std_logic; WAP_ZERO_IN : in std_logic; -- outputs + WAP_REQ_OUT : out std_logic; RX_SERDES_RST_OUT : out std_logic; RX_PCS_RST_OUT : out std_logic; LINK_RX_READY_OUT : out std_logic; diff --git a/media_interfaces/sync/sci_reader_RS.vhd b/media_interfaces/sync/sci_reader_RS.vhd index 0dfe766..2ea0f3f 100644 --- a/media_interfaces/sync/sci_reader_RS.vhd +++ b/media_interfaces/sync/sci_reader_RS.vhd @@ -13,7 +13,6 @@ entity sci_reader_RS is port( CLK : in std_logic; RESET : in std_logic; - --SCI SCI_WRDATA : out std_logic_vector(7 downto 0); SCI_RDDATA : in std_logic_vector(7 downto 0); @@ -21,32 +20,40 @@ entity sci_reader_RS is SCI_SEL : out std_logic_vector(4 downto 0); SCI_RD : out std_logic; SCI_WR : out std_logic; - + -- WAP stuff WA_POS_OUT : out std_logic_vector(15 downto 0); - + WA_REQ_IN : in std_logic; + WA_ACK_OUT : out std_logic; --Slowcontrol BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX; - MEDIA_STATUS_REG_IN : in std_logic_vector(255 downto 0) := (others => '0'); DEBUG_OUT : out std_logic_vector(31 downto 0) - ); + ); end entity; architecture sci_reader_arch of sci_reader_RS is -signal sci_reg_i : std_logic; type sci_ctrl is (IDLE, SCTRL, SCTRL_WAIT, SCTRL_WAIT2, SCTRL_FINISH, GET_WA, GET_WA_WAIT, GET_WA_WAIT2, GET_WA_FINISH); + signal sci_state : sci_ctrl; signal sci_timer : unsigned(12 downto 0) := (others => '0'); + +signal sci_reg_i : std_logic; signal wa_position : std_logic_vector(15 downto 0); signal next_sci_wr : std_logic; +--signal wap_req_q : std_logic_vector(2 downto 0); begin -WA_POS_OUT <= wa_position; +-- THE_SYNC_PROC: process( CLK ) +-- begin +-- if( rising_edge(CLK) ) then +-- wap_req_q(2 downto 0) <= wap_req_q(1 downto 0) & WA_REQ_IN; +-- end if; +-- end process THE_SYNC_PROC; ------------------------------------------------- -- SCI @@ -56,88 +63,90 @@ WA_POS_OUT <= wa_position; BUS_TX.rack <= '0'; BUS_TX.wack <= '0'; -PROC_SCI_CTRL: process - variable cnt : integer range 0 to 4 := 0; -begin - wait until rising_edge(CLK); - BUS_TX.ack <= '0'; - BUS_TX.nack <= '0'; - - SCI_WR <= next_sci_wr; + PROC_SCI_CTRL: process + variable cnt : integer range 0 to 4 := 0; + begin + wait until rising_edge(CLK); + BUS_TX.ack <= '0'; + BUS_TX.nack <= '0'; + + SCI_WR <= next_sci_wr; + + case sci_state is + when IDLE => + SCI_SEL <= (others => '0'); + sci_reg_i <= '0'; + SCI_RD <= '0'; + next_sci_wr <= '0'; + sci_timer <= sci_timer + 1; + if( (BUS_RX.read = '1') or (BUS_RX.write = '1') ) then + SCI_SEL(0) <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8); + SCI_SEL(1) <= BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8); + SCI_SEL(2) <= not BUS_RX.addr(6) and BUS_RX.addr(7) and not BUS_RX.addr(8); + SCI_SEL(3) <= BUS_RX.addr(6) and BUS_RX.addr(7) and not BUS_RX.addr(8); + SCI_SEL(4) <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); + sci_reg_i <= BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); + SCI_ADDR <= BUS_RX.addr(5 downto 0); + SCI_WRDATA <= BUS_RX.data(7 downto 0); + SCI_RD <= BUS_RX.read and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); + next_sci_wr <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); + sci_state <= SCTRL; +-- elsif( (sci_timer(sci_timer'left) = '1') and (wap_req_q(2) = '1') ) then + elsif( (sci_timer(sci_timer'left) = '1') and (WA_REQ_IN = '1') ) then + sci_timer <= (others => '0'); + sci_state <= GET_WA; + end if; + when SCTRL => + if( sci_reg_i = '1' ) then + BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); + BUS_TX.ack <= '1'; + next_sci_wr <= '0'; + SCI_RD <= '0'; + sci_state <= IDLE; + else + sci_state <= SCTRL_WAIT; + end if; + when SCTRL_WAIT => + sci_state <= SCTRL_WAIT2; + when SCTRL_WAIT2 => + sci_state <= SCTRL_FINISH; + when SCTRL_FINISH => + BUS_TX.data(7 downto 0) <= SCI_RDDATA; + BUS_TX.ack <= '1'; + next_sci_wr <= '0'; + SCI_RD <= '0'; + sci_state <= IDLE; + when GET_WA => + if( ((cnt = 4) and (FPGA_TYPE = 3)) or ((cnt = 2) and (FPGA_TYPE = 5)) ) then + cnt := 0; + sci_state <= IDLE; + else + sci_state <= GET_WA_WAIT; + if( FPGA_TYPE = 3 ) then + SCI_ADDR <= "100010";--'0' & x"22"; --for ECP3 + elsif( FPGA_TYPE = 5 ) then + SCI_ADDR <= "110010";--'0' & x"32"; --for ECP5 + end if; + SCI_SEL <= (others => '0'); + SCI_SEL(cnt) <= '1'; + SCI_RD <= '1'; + end if; + when GET_WA_WAIT => + sci_state <= GET_WA_WAIT2; + when GET_WA_WAIT2 => + sci_state <= GET_WA_FINISH; + when GET_WA_FINISH => + wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0); + sci_state <= GET_WA; + cnt := cnt + 1; + end case; - case sci_state is - when IDLE => - SCI_SEL <= (others => '0'); - sci_reg_i <= '0'; - SCI_RD <= '0'; - next_sci_wr <= '0'; - sci_timer <= sci_timer + 1; - if BUS_RX.read = '1' or BUS_RX.write = '1' then - SCI_SEL(0) <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8); - SCI_SEL(1) <= BUS_RX.addr(6) and not BUS_RX.addr(7) and not BUS_RX.addr(8); - SCI_SEL(2) <= not BUS_RX.addr(6) and BUS_RX.addr(7) and not BUS_RX.addr(8); - SCI_SEL(3) <= BUS_RX.addr(6) and BUS_RX.addr(7) and not BUS_RX.addr(8); - SCI_SEL(4) <= not BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); - sci_reg_i <= BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8); - SCI_ADDR <= BUS_RX.addr(5 downto 0); - SCI_WRDATA <= BUS_RX.data(7 downto 0); - SCI_RD <= BUS_RX.read and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); - next_sci_wr <= BUS_RX.write and not (BUS_RX.addr(6) and not BUS_RX.addr(7) and BUS_RX.addr(8)); - sci_state <= SCTRL; --- elsif sci_timer(sci_timer'left) = '1' then --- sci_timer <= (others => '0'); --- sci_state <= GET_WA; - end if; - when SCTRL => - if sci_reg_i = '1' then - BUS_TX.data <= MEDIA_STATUS_REG_IN(32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))+31 downto 32*(to_integer(unsigned(BUS_RX.addr(3 downto 0))))); - BUS_TX.ack <= '1'; - next_sci_wr <= '0'; - SCI_RD <= '0'; - sci_state <= IDLE; - else - sci_state <= SCTRL_WAIT; - end if; - when SCTRL_WAIT => - sci_state <= SCTRL_WAIT2; - when SCTRL_WAIT2 => - sci_state <= SCTRL_FINISH; - when SCTRL_FINISH => - BUS_TX.data(7 downto 0) <= SCI_RDDATA; - BUS_TX.ack <= '1'; - next_sci_wr <= '0'; - SCI_RD <= '0'; - sci_state <= IDLE; - - when GET_WA => - if (cnt = 4 and FPGA_TYPE = 3) or (cnt = 2 and FPGA_TYPE = 5) then - cnt := 0; - sci_state <= IDLE; - else - sci_state <= GET_WA_WAIT; - if FPGA_TYPE = 3 then - SCI_ADDR <= "100010";--'0' & x"22"; --for ECP3 - elsif FPGA_TYPE = 5 then - SCI_ADDR <= "110010";--'0' & x"32"; --for ECP5 - end if; - SCI_SEL <= (others => '0'); - SCI_SEL(cnt) <= '1'; - SCI_RD <= '1'; - end if; - when GET_WA_WAIT => - sci_state <= GET_WA_WAIT2; - when GET_WA_WAIT2 => - sci_state <= GET_WA_FINISH; - when GET_WA_FINISH => - wa_position(cnt*4+3 downto cnt*4) <= SCI_RDDATA(3 downto 0); - sci_state <= GET_WA; - cnt := cnt + 1; - end case; - - if (BUS_RX.read = '1' or BUS_RX.write = '1') and sci_state /= IDLE then - BUS_TX.nack <= '1'; BUS_TX.ack <= '0'; - end if; - -end process; + if( ((BUS_RX.read = '1') or (BUS_RX.write = '1')) and (sci_state /= IDLE) ) then + BUS_TX.nack <= '1'; + BUS_TX.ack <= '0'; + end if; + end process PROC_SCI_CTRL; + + WA_POS_OUT <= wa_position; end architecture; -- 2.43.0