From 2a4ba3340791e42c6200327a0ed192c28c7fe628 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 15 Jun 2009 16:44:35 +0000 Subject: [PATCH] *** empty log message *** --- trb_net_components.vhd | 139 ++++++++++++++++++++++++++++++++++++++++- 1 file changed, 136 insertions(+), 3 deletions(-) diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 729033e..2108f10 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -17,9 +17,6 @@ package trb_net_components is - - - component adc_ltc2308_readout is generic( CLOCK_FREQUENCY : integer := 100 --MHz @@ -279,6 +276,50 @@ package trb_net_components is + component trb_net16_ibuf is + generic ( + DEPTH : integer range 0 to 7 := c_FIFO_BRAM; + USE_VENDOR_CORES : integer range 0 to 1 := c_YES; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION; + SECURE_MODE : integer range 0 to 1 := c_YES; + INIT_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES; + REPLY_CAN_RECEIVE_DATA : integer range 0 to 1 := c_YES + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN : in std_logic; + MED_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT : out std_logic; + MED_ERROR_IN : in std_logic_vector (2 downto 0); + -- Internal direction port + INT_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_INIT_PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_INIT_DATAREADY_OUT : out std_logic; + INT_INIT_READ_IN : in std_logic; + INT_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_REPLY_PACKET_NUM_OUT: out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_REPLY_DATAREADY_OUT : out std_logic; + INT_REPLY_READ_IN : in std_logic; + INT_ERROR_OUT : out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER_COUNTER : out std_logic_vector (31 downto 0); + STAT_BUFFER : out std_logic_vector (31 downto 0) + ); + end component; + + + + + + + component etrax_interface is generic( STATUS_REGISTERS : integer := 4; @@ -759,6 +800,68 @@ package trb_net_components is + + component trb_net16_obuf is + generic ( + DATA_COUNT_WIDTH : integer := 5; + USE_ACKNOWLEDGE : integer range 0 to 1 := std_USE_ACKNOWLEDGE; + USE_CHECKSUM : integer range 0 to 1 := c_YES; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + -- Internal direction port + INT_DATAREADY_IN: in std_logic; + INT_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_IN: in std_logic_vector (c_NUM_WIDTH-1 downto 0); + INT_READ_OUT: out std_logic; + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) + ); + end component; + + + + + + + + + component trb_net16_obuf_nodata is + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_OUT: out std_logic; + MED_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_OUT:out std_logic_vector (c_NUM_WIDTH-1 downto 0); + MED_READ_IN: in std_logic; + --STAT + STAT_BUFFER: out std_logic_vector (31 downto 0); + CTRL_BUFFER: in std_logic_vector (31 downto 0); + STAT_DEBUG : out std_logic_vector (31 downto 0) + ); + end component; + + + + + + + + component pll25 is port( CLK : in std_logic; @@ -1058,6 +1161,36 @@ package trb_net_components is + component trb_net16_term_ibuf is + generic( + SECURE_MODE : integer range 0 to 1 := std_TERM_SECURE_MODE; + SBUF_VERSION : integer range 0 to 1 := std_SBUF_VERSION + ); + port( + -- Misc + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + -- Media direction port + MED_DATAREADY_IN: in std_logic; + MED_DATA_IN: in std_logic_vector (c_DATA_WIDTH-1 downto 0); + MED_PACKET_NUM_IN :in std_logic_vector(c_NUM_WIDTH-1 downto 0); + MED_READ_OUT: out std_logic; + MED_ERROR_IN: in std_logic_vector (2 downto 0); + -- Internal direction port + INT_DATAREADY_OUT: out std_logic; + INT_DATA_OUT: out std_logic_vector (c_DATA_WIDTH-1 downto 0); + INT_PACKET_NUM_OUT:out std_logic_vector(c_NUM_WIDTH-1 downto 0); + INT_READ_IN: in std_logic; + INT_ERROR_OUT: out std_logic_vector (2 downto 0); + -- Status and control port + STAT_BUFFER: out std_logic_vector (31 downto 0) + ); + end component; + + + + component trb_net16_trigger is generic ( USE_TRG_PORT : integer range 0 to 1 := c_YES; -- 2.43.0