From 2a4bb37b6a2a2f13b58cb6e4b5d38439f6a2bcdb Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Wed, 27 May 2015 16:53:49 +0200 Subject: [PATCH] Extending compile_constraints to optionally include TDC --- ADC/compile_constraints.pl | 69 ++++++++++++++++++++++++++--- ADC/compile_periph_gsi.pl | 12 ++--- ADC/config.vhd | 4 +- ADC/source/adc_package.vhd | 18 -------- ADC/trb3_periph_adc.prj | 41 +++++++++++++++++ ADC/trb3_periph_adc_constraints.lpf | 32 ------------- 6 files changed, 110 insertions(+), 66 deletions(-) diff --git a/ADC/compile_constraints.pl b/ADC/compile_constraints.pl index 287f00a..fae4e61 100755 --- a/ADC/compile_constraints.pl +++ b/ADC/compile_constraints.pl @@ -3,13 +3,72 @@ use Data::Dumper; use warnings; use strict; -my $workdir = shift @ARGV || 'workdir'; -unless(-d $workdir) { - print "Creating workdir $workdir\n"; - mkdir $workdir or die "cant create $workdir: $!"; + +use File::Basename; +use Cwd 'realpath'; + +my $TOPNAME = 'trb3_periph_adc'; +my $workdir = './workdir'; + +my $script_dir = dirname(realpath(__FILE__)); +$workdir = $ARGV[0] if (@ARGV); + + +# get activated modules +my %configSettings = (); +open(CONFIG, 'config.vhd'); +my $config = "#!!! This file was compiled using compile_contraints.pl.\n#!!! DO NOT EDIT AS ALL CHANGES WILL BE OVERRIDEN\n\n"; +print "The following module configuration was derived from config.vhd:\n"; +while (my $line = ) { + if ($line =~ /(INCLUDE_\S+).*:=.*c_(yes|no)/i) { + my $mod = uc $1; + my $ena = (lc $2) eq 'yes' ? 1 : 0; + $configSettings{$mod} = $ena; + + my $conf = "set $mod $ena\n"; + print ' ' . $conf; + $config .= $conf; + } } +close(CONFIG); + +open TCLCONF, '>', $TOPNAME . '_prjconfig.tcl'; +print TCLCONF $config; +close TCLCONF; + + +die("workdir has to be relative to compile_constraints.pl") if $workdir =~ m/^\//; +die("workdir must not contain ..") if $workdir =~ m/\.\./; +$workdir =~ s/(\.\/|\/$)//g; # remove ./ and trailing slash +$workdir =~ s/\/{2,}/\//g; # remove multiple // in path -my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity +my $back = "../" x ($workdir =~ tr/\///); +$back = './' unless $back; + +chdir($script_dir); + +unless(-e $workdir) { + print "Creating workdir\n"; + system ("mkdir $workdir"); +} + +chdir($workdir); +system ("$back/../../base/linkdesignfiles.sh '$back'"); +symlink "$back/../tdc_release/Adder_304.ngo", "Adder_304.ngo"; + +chdir($script_dir); system("cp ../base/$TOPNAME.lpf $workdir/$TOPNAME.lpf"); +system("cat tdc_release/tdc_constraints_64.lpf >> $workdir/$TOPNAME.lpf") if $configSettings{'INCLUDE_TDC'}; system("cat ".$TOPNAME."_constraints.lpf >> $workdir/$TOPNAME.lpf"); + +open FILE, "<$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; +my $lpf = join('', ); +close FILE; + +$lpf =~ s#THE_TDC/#GEN_TDC.THE_TDC/#g; +$lpf =~ s#GEN_TDC(.*)The_Buffer#GEN_TDC$1Buffer_64.The_Buffer#g; + +open FILE, ">$workdir/$TOPNAME.lpf" or die "Couldnt open file: $!"; +print FILE $lpf; +close FILE; diff --git a/ADC/compile_periph_gsi.pl b/ADC/compile_periph_gsi.pl index f7aa3fe..e83fe5b 100755 --- a/ADC/compile_periph_gsi.pl +++ b/ADC/compile_periph_gsi.pl @@ -9,9 +9,9 @@ use FileHandle; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_adc"; #Name of top-level entity -my $lattice_path = '/opt/lattice/diamond/2.1_x64'; +my $lattice_path = '/opt/lattice/diamond/3.2_x64'; my $lattice_bin_path = "$lattice_path/bin/lin64"; # note the lin/lin64 at the end, no isfgpa needed -my $synplify_path = '/opt/synplicity/F-2012.03-SP1'; +my $synplify_path = '/opt/synplicity/I-2013.09-SP1'; my $lm_license_file_for_synplify = '27000@lxcad01.gsi.de'; my $lm_license_file_for_par = '1702@hadeb05.gsi.de'; ################################################################################### @@ -41,13 +41,7 @@ my $DEVICENAME="LFE3-150EA"; my $PACKAGE="FPBGA672"; my $SPEEDGRADE="8"; -my $WORKDIR = "workdir"; -unless(-d $WORKDIR) { - mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; - system ("cd workdir; ../../base/linkdesignfiles.sh; cd ..;"); -} - - +# also links the design files and creates the workdir if necessary system ("./compile_constraints.pl"); system ("../base/make_version_vhd.pl"); diff --git a/ADC/config.vhd b/ADC/config.vhd index ec3a476..96173e2 100644 --- a/ADC/config.vhd +++ b/ADC/config.vhd @@ -38,8 +38,8 @@ package config is constant ADC_TRIGGER_LOGIC : integer := c_YES; constant ADC_CHANNELS : integer := 48; ---Include the TDC if READOUT_MODE is CFD - constant INCLUDE_TDC : integer := sel(READOUT_MODE = READOUT_MODE_CFD, c_YES, c_NO); +--Include the TDC (only usefule for CFD readout mode) + constant INCLUDE_TDC : integer := c_YES; ------------------------------------------------------------------------------ --End of design configuration diff --git a/ADC/source/adc_package.vhd b/ADC/source/adc_package.vhd index a719770..218e272 100644 --- a/ADC/source/adc_package.vhd +++ b/ADC/source/adc_package.vhd @@ -88,28 +88,10 @@ package adc_package is Trigger : std_logic; end record; - function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer; - end package; package body adc_package is ----*** START CODE ***--- - ---------------------------------------------------------------- - -- Functions to select one or the other based on a boolean (or - -- std_ulogic or std_logic) input. - -- Analogous to the C statement x = Cond ? a : b - ---------------------------------------------------------------- - function sel(Cond: BOOLEAN; If_True, If_False: integer) return integer is - begin - if (Cond = TRUE) then - return(If_True); - else - return(If_False); - end if; - end function sel; ----*** END CODE ***--- - end package body; diff --git a/ADC/trb3_periph_adc.prj b/ADC/trb3_periph_adc.prj index 3c98e45..b90c68d 100644 --- a/ADC/trb3_periph_adc.prj +++ b/ADC/trb3_periph_adc.prj @@ -1,3 +1,5 @@ +# load configuration derived from config.vhd by compile_constraints.pl +source trb3_periph_adc_prjconfig.tcl # implementation: "workdir" impl -add workdir -type fpga @@ -167,3 +169,42 @@ add_file -vhdl -lib "work" "source/adc_slowcontrol_data_buffer.vhd" add_file -vhdl -lib "work" "trb3_periph_adc.vhd" add_file -constraint "trb3_periph_adc.sdc" + +# TDC stuff + +add_file -vhdl -lib "work" "tdc_release/tdc_version.vhd" +add_file -vhdl -lib "work" "tdc_release/tdc_components.vhd" +if {$INCLUDE_TDC == 1} { + ############### + #Change path to tdc release also in compile script! + ############### + # don't use vhd but link Adder_304.ngo to workdir! + + + add_file -vhdl -lib "work" "tdc_release/bit_sync.vhd" + add_file -vhdl -lib "work" "tdc_release/BusHandler.vhd" + add_file -vhdl -lib "work" "tdc_release/Channel_200.vhd" + add_file -vhdl -lib "work" "tdc_release/Channel.vhd" + add_file -vhdl -lib "work" "tdc_release/Encoder_304_Bit.vhd" + add_file -vhdl -lib "work" "tdc_release/fallingEdgeDetect.vhd" + add_file -vhdl -lib "work" "tdc_release/hit_mux.vhd" + add_file -vhdl -lib "work" "tdc_release/LogicAnalyser.vhd" + add_file -vhdl -lib "work" "tdc_release/Readout.vhd" + add_file -vhdl -lib "work" "tdc_release/risingEdgeDetect.vhd" + add_file -vhdl -lib "work" "tdc_release/ROM_encoder_ecp3.vhd" + add_file -vhdl -lib "work" "tdc_release/ShiftRegisterSISO.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher_A.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher_B.vhd" + add_file -vhdl -lib "work" "tdc_release/Stretcher.vhd" + add_file -vhdl -lib "work" "tdc_release/TDC.vhd" + add_file -vhdl -lib "work" "tdc_release/TriggerHandler.vhd" + add_file -vhdl -lib "work" "tdc_release/up_counter.vhd" + + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_DynThr_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x128_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x64_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_DC_36x32_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x128_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x64_OutReg.vhd" + add_file -vhdl -lib "work" "../../tdc/base/cores/ecp3/FIFO/FIFO_36x32_OutReg.vhd" +} \ No newline at end of file diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 72364c9..566542d 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -95,92 +95,60 @@ MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_A MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_q_*" TO CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_qq_*" 2 X; -# we define everything doubled to make it work with all lattice/synplify versions -# due to _ vs . notation of generate statements args... - # left are ADCs 0-5 and 7 (counted from 0) UGROUP "THE_ADC_LEFT_group" BLKNAME gen_reallogic.THE_ADC/THE_ADC_LEFT; -UGROUP "THE_ADC_LEFT_group_2" BLKNAME gen_reallogic_THE_ADC/THE_ADC_LEFT; REGION "THE_ADC_LEFT_region" "R57C2D" 9 55; LOCATE UGROUP "THE_ADC_LEFT_group" REGION "THE_ADC_LEFT_region"; -LOCATE UGROUP "THE_ADC_LEFT_group_2" REGION "THE_ADC_LEFT_region"; UGROUP "THE_ADC_PROC_cfd_0_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.0.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_0_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_0_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_0_region" "R7C2D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_0_group" REGION "THE_ADC_PROC_cfd_0_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_0_group_2" REGION "THE_ADC_PROC_cfd_0_region"; UGROUP "THE_ADC_PROC_cfd_1_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.1.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_1_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_1_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_1_region" "R7C29D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_1_group" REGION "THE_ADC_PROC_cfd_1_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_1_group_2" REGION "THE_ADC_PROC_cfd_1_region"; UGROUP "THE_ADC_PROC_cfd_2_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.2.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_2_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_2_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_2_region" "R7C56D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_2_group" REGION "THE_ADC_PROC_cfd_2_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_2_group_2" REGION "THE_ADC_PROC_cfd_2_region"; UGROUP "THE_ADC_PROC_cfd_3_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.3.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_3_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_3_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_3_region" "R7C83D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_3_group" REGION "THE_ADC_PROC_cfd_3_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_3_group_2" REGION "THE_ADC_PROC_cfd_3_region"; UGROUP "THE_ADC_PROC_cfd_4_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.4.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_4_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_4_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_4_region" "R66C2D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_4_group" REGION "THE_ADC_PROC_cfd_4_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_4_group_2" REGION "THE_ADC_PROC_cfd_4_region"; UGROUP "THE_ADC_PROC_cfd_5_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.5.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_5_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_5_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_5_region" "R66C29D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_5_group" REGION "THE_ADC_PROC_cfd_5_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_5_group_2" REGION "THE_ADC_PROC_cfd_5_region"; UGROUP "THE_ADC_PROC_cfd_7_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.7.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_7_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_7_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_7_region" "R66C56D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_7_group" REGION "THE_ADC_PROC_cfd_7_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_7_group_2" REGION "THE_ADC_PROC_cfd_7_region"; # right are ADCs 6 and 8-11 (counted from 0) UGROUP "THE_ADC_RIGHT_group" BLKNAME gen_reallogic.THE_ADC/THE_ADC_RIGHT; -UGROUP "THE_ADC_RIGHT_group_2" BLKNAME gen_reallogic_THE_ADC/THE_ADC_RIGHT; REGION "THE_ADC_RIGHT_region" "R57C137D" 9 45; LOCATE UGROUP "THE_ADC_RIGHT_group" REGION "THE_ADC_RIGHT_region"; -LOCATE UGROUP "THE_ADC_RIGHT_group_2" REGION "THE_ADC_RIGHT_region"; UGROUP "THE_ADC_PROC_cfd_6_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.6.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_6_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_6_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_6_region" "R66C101D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_6_group" REGION "THE_ADC_PROC_cfd_6_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_6_group_2" REGION "THE_ADC_PROC_cfd_6_region"; UGROUP "THE_ADC_PROC_cfd_8_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.8.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_8_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_8_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_8_region" "R66C128D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_8_group" REGION "THE_ADC_PROC_cfd_8_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_8_group_2" REGION "THE_ADC_PROC_cfd_8_region"; UGROUP "THE_ADC_PROC_cfd_9_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.9.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_9_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_9_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_9_region" "R66C155D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_9_group" REGION "THE_ADC_PROC_cfd_9_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_9_group_2" REGION "THE_ADC_PROC_cfd_9_region"; UGROUP "THE_ADC_PROC_cfd_10_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.10.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_10_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_10_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_10_region" "R7C128D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_10_group" REGION "THE_ADC_PROC_cfd_10_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_10_group_2" REGION "THE_ADC_PROC_cfd_10_region"; UGROUP "THE_ADC_PROC_cfd_11_group" BLKNAME gen_reallogic.THE_ADC/gen_readout_cfd.gen_processors.11.THE_ADC_PROC; -UGROUP "THE_ADC_PROC_cfd_11_group_2" BLKNAME gen_reallogic_THE_ADC/gen_readout_cfd_gen_processors_11_THE_ADC_PROC; REGION "THE_ADC_PROC_cfd_11_region" "R7C155D" 49 27; LOCATE UGROUP "THE_ADC_PROC_cfd_11_group" REGION "THE_ADC_PROC_cfd_11_region"; -LOCATE UGROUP "THE_ADC_PROC_cfd_11_group_2" REGION "THE_ADC_PROC_cfd_11_region"; - -- 2.43.0