From 2b37090c9d5dbbcd9f65cb726db1681bb972d517 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 25 Jul 2016 17:35:24 +0200 Subject: [PATCH] Include M26 trigger module to CTS. Include MBS master output sender to CTS --- base/trb3_central_cts.lpf | 6 +- cts/compile_central_frankfurt.pl | 12 +- cts/config_mvd.vhd | 160 ++++++++++++++++ cts/source/cts.vhd | 13 +- cts/source/cts_pkg.vhd | 1 + cts/source/m26_sensor_etm.vhd | 179 ++++++++++++++++++ cts/source/mbs_master.vhd | 124 +++++++++++++ cts/trb3_central.prj | 85 +-------- cts/trb3_central.vhd | 284 ++++++++++++++++++----------- cts/trb3_central_constraints_3.lpf | 205 ++++++++++----------- 10 files changed, 765 insertions(+), 304 deletions(-) create mode 100644 cts/config_mvd.vhd create mode 100644 cts/source/m26_sensor_etm.vhd create mode 100644 cts/source/mbs_master.vhd diff --git a/base/trb3_central_cts.lpf b/base/trb3_central_cts.lpf index 72f976c..d27ce22 100644 --- a/base/trb3_central_cts.lpf +++ b/base/trb3_central_cts.lpf @@ -61,10 +61,10 @@ LOCATE COMP "TRIGGER_EXT_3" SITE "W4"; #was EXT_TRIG_2 DEFINE PORT GROUP "TRIGGER_EXT_group" "TRIGGER_EXT*" ; IOBUF GROUP "TRIGGER_EXT_group" IO_TYPE=LVDS25; -LOCATE COMP "CLK_TEST_OUT_2" SITE "Y34"; -IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; -LOCATE COMP "CLK_TEST_OUT_1" SITE "W4"; +LOCATE COMP "CLK_TEST_OUT_1" SITE "Y34"; IOBUF PORT "CLK_TEST_OUT_1" IO_TYPE=LVDS25 ; +LOCATE COMP "CLK_TEST_OUT_2" SITE "W4"; +IOBUF PORT "CLK_TEST_OUT_2" IO_TYPE=LVDS25 ; LOCATE COMP "CLK_TEST_OUT_0" SITE "U9"; IOBUF PORT "CLK_TEST_OUT_0" IO_TYPE=LVDS25 ; diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index ada63bb..cdbb331 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -13,11 +13,11 @@ use Cwd 'abs_path'; my $TOPNAME = "trb3_central"; #Name of top-level entity my $BasePath = "../base/"; #path to "base" directory my $CbmNetPath = "../../cbmnet"; -my $lm_license_file_for_synplify = "1702\@hadeb05.gsi.de"; #"27000\@lxcad01.gsi.de"; +my $lm_license_file_for_synplify = "27020\@jspc29"; #"27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -my $lattice_path = '/d/jspc29/lattice/diamond/3.6_x64'; -my $synplify_path = '/d/jspc29/lattice/synplify/J-2015.03-SP1/'; +my $lattice_path = '/d/jspc29/lattice/diamond/3.7_x64'; +my $synplify_path = '/d/jspc29/lattice/synplify/K-2015.09/'; ################################################################################### @@ -69,7 +69,11 @@ system("env| grep LM_"); my $r = ""; # my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -my $c="$lattice_path/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj"; +# my $c="$lattice_path/bin/lin64/synpwrap -fg -options -batch $TOPNAME.prj"; +print "Starting synthesis process...\n\n"; +my $synplify_command = "$synplify_path/bin/synplify_premier_dp"; +my $c="$synplify_command -batch $TOPNAME.prj"; + $r=execute($c, "do_not_exit" ); chdir "workdir"; diff --git a/cts/config_mvd.vhd b/cts/config_mvd.vhd new file mode 100644 index 0000000..10fd989 --- /dev/null +++ b/cts/config_mvd.vhd @@ -0,0 +1,160 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is +------------------------------------------------------------------------------ +--Begin of configuration +------------------------------------------------------------------------------ + + constant INCLUDE_CTS : integer range c_NO to c_YES := c_YES; + constant INCLUDE_CBMNET : integer range c_NO to c_YES := c_NO; + constant INCLUDE_MBS_MASTER : integer range c_NO to c_YES := c_YES; + +--include TDC for all four trigger input lines + + constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO; + constant TDC_CHANNEL_NUMBER : integer := 5; + constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 0; --double edge type: 0, 1, 2, 3 + -- 0: single edge only, + -- 1: same channel, + -- 2: alternating channels, + -- 3: same channel with stretcher + constant RING_BUFFER_SIZE : integer range 0 to 7 := 7; --ring buffer size: 0, 1, 2, 3, 7 + --ring buffer size: 32,64,96,128,dyn +-- Include SFP power readout + constant INCLUDE_SFP_DDM : integer range c_NO to c_YES := c_NO; + +--use all four SFP (1-4) as downlink to other boards (only w/o CBMNET) + constant USE_4_SFP : integer range c_NO to c_YES := c_NO; + + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer range c_NO to c_YES := c_NO; + +--Run external 200 MHz clock source + constant USE_EXTERNAL_CLOCK : integer range c_NO to c_YES := c_NO; + +--Which external trigger module (ETM) to use? + constant INCLUDE_ETM : integer range c_NO to c_YES := c_YES; + type ETM_CHOICE_type is (ETM_CHOICE_MBS_VULOM, ETM_CHOICE_MAINZ_A2, ETM_CHOICE_CBMNET, ETM_CHOICE_M26); + constant ETM_CHOICE : ETM_CHOICE_type := ETM_CHOICE_M26; + + constant ETM_ID : std_logic_vector(7 downto 0); + +--output busy signal on pair 4 of Trigger RJ45? + constant GEN_BUSY_OUTPUT : integer := c_NO; + + constant TRIGGER_COIN_COUNT : integer := 1; + constant TRIGGER_PULSER_COUNT : integer := 2; + constant TRIGGER_RAND_PULSER : integer := 1; + constant TRIGGER_ADDON_COUNT : integer := 1; + constant PERIPH_TRIGGER_COUNT : integer := 1; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F3CE"; + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"60"; + +------------------------------------------------------------------------------ +--End of configuration +------------------------------------------------------------------------------ + +--Ports: +-- LVL1/IPU SCtrl +-- 0 FPGA 1 FPGA 1 +-- 1 FPGA 2 FPGA 2 +-- 2 FPGA 3 FPGA 3 +-- 3 FPGA 4 FPGA 4 +-- 4 opt. link opt. link +-- 5-7 SFP 2-4 +-- 5(8) CTS read-out internal 0 1 - X X O --downlink only +-- 6(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only + +------------------------------------------------------------------------------ +--Hub configuration +------------------------------------------------------------------------------ + type hub_mii_t is array(0 to 1) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 1) of hub_ct; + type hw_info_t is array(0 to 1) of std_logic_vector(31 downto 0); + + --this is used to select the proper configuration in the main code + constant CFG_MODE : integer; + + + --first entry is normal CTS with one optical output, second one is with four optical outputs + --slow-control is accepted on SFP1 only, triggers are sent to all used SFP + constant INTERNAL_NUM_ARR : hub_mii_t := (5,5); + constant INTERFACE_NUM_ARR : hub_mii_t := (5,8); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,1,0,0,0,0,1,0,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)); + constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0",x"9000CEE2"); + + constant CLOCK_FREQUENCY : integer := 100; + constant INTERNAL_NUM : integer; + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + + -- MII_NUMBER => 5, --(8) + -- INT_NUMBER => 5, + -- INT_CHANNELS => (0,1,0,1,3), + + -- No trigger / sctrl sent to optical link, slow control receiving possible + -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + + -- Trigger / sctrl sent to optical link, slow control receiving possible + -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0); + -- & disable port 4 in c0 and c1 -- no triggers from/to optical link + + -- Trigger / sctrl sent to 4 optical links + -- MII_IS_UPLINK => (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0); + -- & disable port 4 in c0 and c1 -- no triggers from/to optical link + +------------------------------------------------------------------------------ +--CTS configuration +------------------------------------------------------------------------------ + constant cts_rdo_additional_ports : integer; + +end; + +package body config is +--compute correct configuration mode + constant CFG_MODE : integer := USE_4_SFP; + constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC + INCLUDE_CBMNET + INCLUDE_MBS_MASTER; + + constant HARDWARE_INFO : std_logic_vector (31 downto 0) := HARDWARE_INFO_ARR(INCLUDE_TDC); + constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE); + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + + function etm_id_func return std_logic_vector is + variable res : unsigned(7 downto 0); + begin + res := x"00"; + if INCLUDE_ETM=c_YES then + res := x"60"; + res := res + TO_UNSIGNED(ETM_CHOICE_type'pos(ETM_CHOICE), 4); + end if; + return std_logic_vector(res); + end function; + + constant ETM_ID : std_logic_vector(7 downto 0) := etm_id_func; + +end package body; diff --git a/cts/source/cts.vhd b/cts/source/cts.vhd index 2e0dac1..4b633dd 100755 --- a/cts/source/cts.vhd +++ b/cts/source/cts.vhd @@ -6,7 +6,7 @@ library work; use work.trb_net_components.all; use work.trb_net_std.all; use work.CTS_PKG.ALL; - + use work.config.all; -- Debug and status registers -- Address Description -- @@ -144,6 +144,7 @@ entity CTS is EXT_STATUS_IN : in std_logic_vector(31 downto 0) := X"00000000"; EXT_CONTROL_OUT : out std_logic_vector(31 downto 0); EXT_HEADER_BITS_IN : in std_logic_vector( 1 downto 0) := "00"; + EXT_FORCE_TRIGGER_INFO_IN : in std_logic_vector(23 downto 0) := (others => '0'); -- CTS Endpoint ----------------------------------------------------------- --LVL1 trigger @@ -429,7 +430,11 @@ begin -- cts CTS_TRG_NUMBER_OUT <= td_trigger_id_i; - CTS_TRG_INFORMATION_OUT <= trg_information_reg; +-- if EXTERNAL_TRIGGER_ID = x"63" then + CTS_TRG_INFORMATION_OUT <= trg_information_reg or EXT_FORCE_TRIGGER_INFO_IN; +-- else +-- CTS_TRG_INFORMATION_OUT <= trg_information_reg; +-- end if; CTS_TRG_INFORMATION_OUT(7) <= trigger_type_buf_i(3); CTS_TRG_RND_CODE_OUT <= td_random_number_i; CTS_TRG_SEND_OUT <= '1'; @@ -687,8 +692,8 @@ begin begin if rising_edge(CLK) then -- sequence (without external entropy) repeats every 256 iterations - td_random_number_i <= STD_LOGIC_VECTOR(UNSIGNED(td_random_number_i) + TO_UNSIGNED(113, 8) + UNSIGNED(CTS_REGIO_ADDR_IN(7 downto 0))) - xor ("0" & LVL1_TRG_DATA_VALID_IN & "0" &LVL1_VALID_TIMING_TRG_IN & "0000"); + td_random_number_i <= STD_LOGIC_VECTOR(UNSIGNED(td_random_number_i) + TO_UNSIGNED(113, 8));-- + UNSIGNED(CTS_REGIO_ADDR_IN(7 downto 0))) + --xor ("0" & LVL1_TRG_DATA_VALID_IN & "0" &LVL1_VALID_TIMING_TRG_IN & "0000"); end if; end process; diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd index 355b2fe..06cb7ab 100755 --- a/cts/source/cts_pkg.vhd +++ b/cts/source/cts_pkg.vhd @@ -53,6 +53,7 @@ package cts_pkg is EXT_STATUS_IN : in std_logic_vector(31 downto 0) := X"00000000"; EXT_CONTROL_OUT : out std_logic_vector(31 downto 0); EXT_HEADER_BITS_IN : in std_logic_vector( 1 downto 0) := "00"; + EXT_FORCE_TRIGGER_INFO_IN : in std_logic_vector(23 downto 0) := (others => '0'); -- CTS Endpoint ----------------------------------------------------------- diff --git a/cts/source/m26_sensor_etm.vhd b/cts/source/m26_sensor_etm.vhd new file mode 100644 index 0000000..128a74f --- /dev/null +++ b/cts/source/m26_sensor_etm.vhd @@ -0,0 +1,179 @@ + +--m26_sensor_etm +--To check the busy status of the CTS +--Qiyan 06072016 + + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.All; + +library work; +--use work.trb_net_std.all; +--use work.trb3_components.all; + + +entity m26_sensor_etm is + port( + CLK : in std_logic; -- system clk 100 MHz! + RESET_IN : in std_logic; -- system reset + + Busy_IN : in std_logic; -- status of trb data transfer. + BUFFER_WARNING_IN : in std_logic; + + Trigger_OUT : out std_logic; -- trigger for TRB depends on the Busy_in; + DISCARD_OUT : out std_logic; + + --data output for read-out + TRIGGER_IN : in std_logic; + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_OUT : out std_logic; + STATUSBIT_OUT : out std_logic_vector(31 downto 0); + FINISHED_OUT : out std_logic; + + --Registers / Debug + CONTROL_REG_IN : in std_logic_vector(31 downto 0); + STATUS_REG_OUT : out std_logic_vector(31 downto 0) := (others => '0'); + DEBUG : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch1 of m26_sensor_etm is + + type state_trigger is (IDLE, WAIT_PULSE,CHECK_BUSY,WAIT_BUSY,SEND_TRIGGER); + signal state : state_trigger := IDLE; + + type state_readout is (RDO_IDLE, RDO_WRITE1, RDO_WRITE2, RDO_WRITE3, RDO_WRITE4, RDO_FINISH); + signal rdostate : state_readout := RDO_IDLE; + + signal pulserCNT: integer range 0 to 65535; + signal waitBusyCNT: integer range 0 to 65535; + signal bufWaringCNT: integer range 0 to 1023; + signal config_checkbusy_disable_IN: std_logic; + signal config_discard_disable_IN:std_logic; + signal config_rdo_disable_IN:std_logic; + signal busy_delayCLK: integer range 0 to 1023; + signal bufferWarning_NUM:integer range 0 to 1023; + +begin + + + PROC_FSM : process + begin + wait until rising_edge(CLK); + if RESET_IN = '1' then + state <= IDLE; + waitBusyCNT <= 0; + pulserCNT <= 0; + bufWaringCNT <= 0; + Trigger_OUT <= '0'; + DISCARD_OUT <= '0'; + else + Trigger_OUT <= '0'; + DISCARD_OUT <= '0'; + pulserCNT <= pulserCNT + 1; + if(pulserCNT = 11520)then + pulserCNT <= 0; + end if; + case state is + when IDLE => + waitBusyCNT <= 0; + DISCARD_OUT <= '0'; + bufWaringCNT <= 0; + if(config_checkbusy_disable_IN = '0') then + state <= WAIT_PULSE; + else + if(pulserCNT = 11520)then + Trigger_OUT <= '1'; + end if; + end if; + when WAIT_PULSE => + if(pulserCNT = 11519) then + state <= CHECK_BUSY; + end if; + when CHECK_BUSY => + if(Busy_IN = '0')then + if(BUFFER_WARNING_IN = '1')then + bufWaringCNT <= bufWaringCNT + 1; + else + bufWaringCNT <= 0; + end if; + state <= SEND_TRIGGER; + else + state <= WAIT_BUSY; + end if; + when WAIT_BUSY => + waitBusyCNT <= waitBusyCNT + 1;--how many clk should it wait? + if(Busy_IN = '0')then + state <= SEND_TRIGGER; + if(BUFFER_WARNING_IN = '1')then + bufWaringCNT <= bufWaringCNT + 1; + else + bufWaringCNT <= 0; + end if; + end if; + when SEND_TRIGGER => + Trigger_OUT <= '1'; + if(waitBusyCNT > busy_delayCLK or bufWaringCNT > bufferWarning_NUM)then + if(config_discard_disable_IN = '0')then + DISCARD_OUT <= '1'; + end if; + end if; + waitBusyCNT <= 0; + bufWaringCNT <= 0; + state <= WAIT_PULSE; + end case; + end if; + end process; + + + + + + PROC_RDO : process + begin + wait until rising_edge(CLK); + WRITE_OUT <= '0'; + FINISHED_OUT <= config_rdo_disable_IN; + STATUSBIT_OUT <= (others => '0');--(23 => data_status_reg(0), others => '0'); + DATA_OUT <= x"00000000"; + case rdostate is + when RDO_IDLE => + DATA_OUT <= x"00000000"; + if TRIGGER_IN = '1' and config_rdo_disable_IN = '0' then + rdostate <= RDO_WRITE1; + end if; + when RDO_WRITE1 => + rdostate <= RDO_WRITE2; + DATA_OUT <= x"55555555"; + WRITE_OUT <= '1'; + when RDO_WRITE2 => + rdostate <= RDO_WRITE3; + DATA_OUT <= x"AAAAAAAA"; + WRITE_OUT <= '1'; + when RDO_WRITE3 => + rdostate <= RDO_WRITE4; + DATA_OUT <= x"deadbeef"; + WRITE_OUT <= '1'; + when RDO_WRITE4 => + rdostate <= RDO_FINISH; + DATA_OUT <= x"deadbeef"; + WRITE_OUT <= '1'; + when RDO_FINISH => + FINISHED_OUT <= '1'; + rdostate <= RDO_IDLE; + end case; + end process; + + config_rdo_disable_IN <= CONTROL_REG_IN(0); + config_discard_disable_IN <= CONTROL_REG_IN(1); + config_checkbusy_disable_IN <= CONTROL_REG_IN(2); + busy_delayCLK <= to_integer(unsigned(CONTROL_REG_IN(14 downto 5))); + bufferWarning_NUM <= to_integer(unsigned(CONTROL_REG_IN(24 downto 15))); + + STATUS_REG_OUT <= std_logic_vector(to_unsigned(pulserCNT,16)) & std_logic_vector(to_unsigned(waitBusyCNT,16)); + DEBUG <= x"00000000"; + +end architecture; diff --git a/cts/source/mbs_master.vhd b/cts/source/mbs_master.vhd new file mode 100644 index 0000000..7f4a614 --- /dev/null +++ b/cts/source/mbs_master.vhd @@ -0,0 +1,124 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.numeric_std.All; + +library work; +use work.trb_net_std.all; + + +entity mbs_master is + port( + CLK : in std_logic; -- system clk 100 MHz! + RESET_IN : in std_logic; -- system reset + + MBS_CLOCK_OUT : out std_logic; + MBS_DATA_OUT : out std_logic; + + --data output for read-out + TRIGGER_IN : in std_logic; + TRIGGER_NUMBER_IN : in std_logic_vector(15 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_OUT : out std_logic; + FINISHED_OUT : out std_logic; + STATUSBIT_OUT : out std_logic_vector(31 downto 0) + ); +end entity; + + + +architecture arch1 of mbs_master is + + type state_trigger is (IDLE, MAKEWORD, SETUP, CLOCKWAIT, MBS_FINISHED); + signal state : state_trigger := IDLE; + + type state_readout is (RDO_IDLE, RDO_WRITE1, RDO_FINISH); + signal rdostate : state_readout := RDO_IDLE; + + signal mbs_trigger_counter : std_logic_vector(23 downto 0); + signal mbs_word : std_logic_vector(36 downto 0); + signal mbs_clock_i : std_logic; + signal mbs_data_i : std_logic; + signal bitcounter : unsigned(6 downto 0); + signal last_TRIGGER_IN : std_logic; + +begin +MBS_CLOCK_OUT <= mbs_clock_i; +MBS_DATA_OUT <= mbs_data_i; + +last_TRIGGER_IN <= TRIGGER_IN when rising_edge(CLK); + + PROC_FSM : process + begin + wait until rising_edge(CLK); + if RESET_IN = '1' then + state <= IDLE; + mbs_trigger_counter <= 0; + else + case state is + when IDLE => + mbs_clock_i <= '0'; + mbs_data_i <= '1'; + if TRIGGER_IN = '1' and last_TRIGGER_IN = '0' then + mbs_trigger_counter(15 downto 0) <= TRIGGER_NUMBER_IN; + if mbs_trigger_counter(15 downto 0) = x"ffff" then + mbs_trigger_counter(23 downto 16) <= std_logic_vector(unsigned(mbs_trigger_counter(23 downto 16)) + 1); + end if; + state <= MAKEWORD; + end if; + when MAKEWORD => + mbs_word(36 downto 32) <= "01010"; + mbs_word(31 downto 8) <= std_logic_vector(mbs_trigger_counter); + mbs_word(7 downto 6) <= "00"; + mbs_word(5) <= xor_all(std_logic_vector(mbs_trigger_counter)); + mbs_word(4 downto 0) <= "10101"; + bitcounter <= 10#36#; + state <= SETUP; + when SETUP => + mbs_clock_i <= '1'; + mbs_data_i <= mbs_word(36); + mbs_word <= mbs_word(35 downto 0) & '1'; + bitcounter <= bitcounter - 1; + state <= CLOCKWAIT; + when CLOCKWAIT => + mbs_clock_i <= '0'; + if bitcounter = 0 then + state <= MBS_FINISHED; + else + state <= SETUP; + end if; + when MBS_FINISHED => + state <= IDLE; + end case; + end if; + end process; + + + + PROC_RDO : process + begin + wait until rising_edge(CLK); + WRITE_OUT <= '0'; + FINISHED_OUT <= '0'; + STATUSBIT_OUT <= (others => '0'); + DATA_OUT <= x"00000000"; + case rdostate is + when RDO_IDLE => + if TRIGGER_IN = '1' and last_TRIGGER_IN = '0' then + rdostate <= RDO_WRITE1; + end if; + when RDO_WRITE1 => + if state = MBS_FINISHED then + rdostate <= RDO_FINISH; + DATA_OUT <= x"b5" & std_logic_vector(mbs_trigger_counter); + WRITE_OUT <= '1'; + end if; + when RDO_FINISH => + FINISHED_OUT <= '1'; + rdostate <= RDO_IDLE; + end case; + if RESET_IN = '1' then + rdostate <= RDO_IDLE; + end if; + end process; + +end architecture; diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 3a05cc6..d215547 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -145,87 +145,7 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" -#gbe files -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_protocols.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net_gbe_components.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_ch4.vhd" -# -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_receive_control.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_main_control.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_mac_control.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_prioritizer.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_protocol_selector.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Forward.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Test1.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Trash.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_type_validator.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_lsm_sfp_gbe.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_med_ecp_sfp_gbe_8b.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_trans.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_frame_constr.vhd" -# #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_nologic.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr.vhd" -# #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_packet_constr_simple_sender.vhd" -# -# -# #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu2gbe_simple_sender.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_ipu2gbe.vhd" -# -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ip_configurator.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_buf.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_setup.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/mb_mac_sim.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_mac_memory.vhd" -# #add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/slv_register.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/ip_mem.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/serdes_gbe_0ch/serdes_gbe_0ch.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/mac_init_mem.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x9.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4096x32.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_16kx8.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx8.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x72.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_2048x8x16.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_65536x18x9.vhd" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/debug_fifo_2kx16.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx16x8_mb2.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_64kx9.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/statts_mem.vhd" -# -# add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/sgmii_channel_smi.v" -# add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_pcs.v" -# add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/reset_controller_cdr.v" -# add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/register_interface_hb.v" -# add_file -verilog -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/sgmii33/rate_resolution.v" -# -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_transmit_control2.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_response_constructor_TrbNetData.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx18x9.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_4kx8_ecp3.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_512x32x8.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/ipcores_ecp3/fifo_32kx9_flags.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_ipu_interface.vhd" -# add_file -vhdl -lib work "../../trbnet/gbe2_ecp3/trb_net16_gbe_event_constr.vhd" + #trbnet and base files @@ -326,6 +246,9 @@ add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" add_file -vhdl -lib work "source/cts_pkg.vhd" add_file -vhdl -lib work "source/cbmnet_dlm_etm.vhd" +add_file -vhdl -lib work "source/m26_sensor_etm.vhd" +add_file -vhdl -lib work "source/mbs_master.vhd" + if {$INCLUDE_CTS == 1} { add_file -vhdl -lib work "source/cts_fifo.vhd" add_file -vhdl -lib work "source/cts_trg_input.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 8bd5827..8fca209 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -54,7 +54,8 @@ entity trb3_central is -- TRIGGER_EXT : inout std_logic_vector(4 downto 2); --additional trigger from RJ45 TRIGGER_OUT : out std_logic; --trigger to second input of fan-out TRIGGER_OUT2 : out std_logic; - + CLK_TEST_OUT : out std_logic_vector(1 downto 0); --CLK_EXT_3/4 as output + --Serdes CLK_SERDES_INT_LEFT : in std_logic; --Clock Manager 2/0, 200 MHz, only in case of problems CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible @@ -564,6 +565,13 @@ architecture trb3_central_arch of trb3_central is signal do_reboot_i : std_logic; signal killswitch_reboot_i : std_logic; + signal cts_ext_bufferwarning : std_logic := '0'; + signal cts_ext_discard : std_logic := '0'; + signal cts_ext_force_trigger_info : std_logic_vector(23 downto 0) := (others => '0'); + signal last_cts_trg_busy : std_logic; + + signal mbs_clock_i, mbs_data_i : std_logic; + -- cbmnet signal cbm_clk_i : std_logic; signal cbm_reset_i : std_logic; @@ -590,6 +598,7 @@ architecture trb3_central_arch of trb3_central is begin assert not(USE_4_SFP = c_YES and INCLUDE_CBMNET = c_YES) report "CBMNET uses SFPs 1-4 and hence does not support USE_4_SFP" severity failure; assert not(INCLUDE_CBMNET = c_YES and INCLUDE_CTS = c_NO) report "CBMNET is supported only with CTS included" severity failure; + assert not(INCLUDE_TDC = c_YES and INCLUDE_MBS_MASTER = c_NO) report "TDC and MBS Master can not be implemented" severity failure; -- MBS Module gen_mbs_vulom_as_etm : if ETM_CHOICE = ETM_CHOICE_MBS_VULOM and INCLUDE_CTS = c_YES and INCLUDE_ETM = c_YES generate @@ -647,6 +656,37 @@ begin ); end generate; +-- Mimosa26 MVD ETM + gen_m26_etm : if ETM_CHOICE = ETM_CHOICE_M26 and INCLUDE_CTS = c_YES and INCLUDE_ETM = c_YES generate + m26_etm : entity work.m26_sensor_etm + port map ( + CLK => clk_100_i, + RESET_IN => reset_i, + + BUSY_IN => trigger_busy_i, + BUFFER_WARNING_IN => cts_ext_bufferwarning, + TRIGGER_OUT => cts_ext_trigger, + DISCARD_OUT => cts_ext_discard, + + TRIGGER_IN => cts_rdo_trg_data_valid, + DATA_OUT => cts_rdo_additional(0).data, + WRITE_OUT => cts_rdo_additional(0).data_write, + FINISHED_OUT => cts_rdo_additional(0).data_finished, + STATUSBIT_OUT => cts_rdo_additional(0).statusbits, + + --Registers / Debug + CONTROL_REG_IN => cts_ext_control, + STATUS_REG_OUT => cts_ext_status, + DEBUG => cts_ext_debug + ); + cts_ext_header <= "10"; + cts_ext_force_trigger_info(0) <= cts_ext_discard; + cts_ext_force_trigger_info(23 downto 1) <= (others => '0'); + last_cts_trg_busy <= cts_trg_busy when rising_edge(clk_100_i); + cts_ext_bufferwarning <= cts_trg_status_bits(20) when cts_trg_busy = '0' and last_cts_trg_busy = '1'; + end generate; + + -- CBMNet ETM gen_cbmnet_etm : if (ETM_CHOICE = ETM_CHOICE_CBMNET and INCLUDE_CTS = c_YES) or INCLUDE_ETM = c_NO generate cts_ext_trigger <= cbm_etm_trigger_i; @@ -691,6 +731,7 @@ begin EXT_STATUS_IN => cts_ext_status, EXT_CONTROL_OUT => cts_ext_control, EXT_HEADER_BITS_IN => cts_ext_header, + EXT_FORCE_TRIGGER_INFO_IN => cts_ext_force_trigger_info, PERIPH_TRIGGER_IN => cts_periph_trigger_i, @@ -732,7 +773,9 @@ begin FEE_DATA_FINISHED_OUT => cts_rdo_finished ); +gen_trigger_in_nombsmaster : if INCLUDE_MBS_MASTER = c_NO generate cts_addon_triggers_in(1 downto 0) <= CLK_EXT; -- former trigger inputs +end generate; cts_addon_triggers_in(3 downto 2) <= TRIGGER_EXT_3 & TRIGGER_EXT_2; -- former trigger inputs cts_addon_triggers_in(7 downto 4) <= ECL_IN; @@ -782,115 +825,115 @@ begin cts_trigger_out <= '0'; end generate; ---------------------------------------------------------------------------- --- CBMNET stack ---------------------------------------------------------------------------- - GEN_CBMNET : if INCLUDE_CBMNET = c_YES generate - THE_CBM_BRIDGE : cbmnet_bridge - port map ( - -- clock and reset - CLK125_IN => clk_125_i, -- in std_logic; - ASYNC_RESET_IN => clear_i, - TRB_CLK_IN => clk_100_i, -- in std_logic; - TRB_RESET_IN => reset_i, -- in std_logic; - - CBM_CLK_OUT => cbm_clk_i, -- out std_logic; - CBM_RESET_OUT => cbm_reset_i, -- out std_logic; - - -- Media Interface - SD_RXD_P_IN => SFP_RX_P(5), - SD_RXD_N_IN => SFP_RX_N(5), - SD_TXD_P_OUT => SFP_TX_P(5), - SD_TXD_N_OUT => SFP_TX_N(5), - - SD_PRSNT_N_IN => SFP_MOD0(1), - SD_LOS_IN => SFP_LOS(1), - SD_TXDIS_OUT => SFP_TXDIS(1), - - LED_RX_OUT => cbm_phy_led_rx_i, - LED_TX_OUT => cbm_phy_led_tx_i, - LED_OK_OUT => cbm_phy_led_ok_i, - - -- Status and strobes - CBM_LINK_ACTIVE_OUT => cbm_link_active_i, - CBM_DLM_OUT => cbm_sync_dlm_sensed_i, -- out std_logic; - CBM_TIMING_TRIGGER_OUT => cbm_sync_timing_trigger_i, -- out std_logic; - CBM_SYNC_PULSER_OUT => cbm_sync_pulser_i, -- out std_logic; - - -- TRBNet Terminal - TRB_TRIGGER_IN => cts_trigger_out, - TRB_RDO_VALID_DATA_TRG_IN => cts_rdo_trg_data_valid, -- in std_logic; - TRB_RDO_VALID_NO_TIMING_IN => cts_rdo_valid_notiming_trg, -- in std_logic; - TRB_RDO_DATA_OUT => cts_rdo_additional(1).data, -- out std_logic_vector(31 downto 0); - TRB_RDO_WRITE_OUT => cts_rdo_additional(1).data_write, -- out std_logic; - TRB_RDO_FINISHED_OUT => cts_rdo_additional(1).data_finished, -- out std_logic; - - TRB_TRIGGER_OUT => cbm_etm_trigger_i, - - -- connect to hub - HUB_CTS_NUMBER_IN => hub_cts_number, -- in std_logic_vector (15 downto 0); - HUB_CTS_CODE_IN => hub_cts_code, -- in std_logic_vector (7 downto 0); - HUB_CTS_INFORMATION_IN => hub_cts_information, -- in std_logic_vector (7 downto 0); - HUB_CTS_READOUT_TYPE_IN => hub_cts_readout_type, -- in std_logic_vector (3 downto 0); - HUB_CTS_START_READOUT_IN => hub_cts_start_readout, -- in std_logic; - HUB_CTS_READOUT_FINISHED_OUT => hub_cts_readout_finished, -- out std_logic; --no more data, end transfer, send TRM - HUB_CTS_STATUS_BITS_OUT => hub_cts_status_bits, -- out std_logic_vector (31 downto 0); - HUB_FEE_DATA_IN => hub_fee_data, -- in std_logic_vector (15 downto 0); - HUB_FEE_DATAREADY_IN => hub_fee_dataready, -- in std_logic; - HUB_FEE_READ_OUT => hub_fee_read, -- out std_logic; --must be high when idle, otherwise you will never get a dataready - HUB_FEE_STATUS_BITS_IN => hub_fee_status_bits, -- in std_logic_vector (31 downto 0); - HUB_FEE_BUSY_IN => hub_fee_busy, -- in std_logic; - - -- connect to GbE - GBE_CTS_NUMBER_OUT => gbe_cts_number, -- out std_logic_vector (15 downto 0); - GBE_CTS_CODE_OUT => gbe_cts_code, -- out std_logic_vector (7 downto 0); - GBE_CTS_INFORMATION_OUT => gbe_cts_information, -- out std_logic_vector (7 downto 0); - GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, -- out std_logic_vector (3 downto 0); - GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, -- out std_logic; - GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, -- in std_logic; --no more data, end transfer, send TRM - GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, -- in std_logic_vector (31 downto 0); - GBE_FEE_DATA_OUT => gbe_fee_data, -- out std_logic_vector (15 downto 0); - GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, -- out std_logic; - GBE_FEE_READ_IN => gbe_fee_read, -- in std_logic; --must be high when idle, otherwise you will never get a dataready - GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, -- out std_logic_vector (31 downto 0); - GBE_FEE_BUSY_OUT => gbe_fee_busy, -- out std_logic; - - -- reg io - --REGIO_IN => cbm_regio_rx, - --REGIO_OUT => cbm_regio_tx - REGIO_ADDR_IN => cbm_regio_rx.addr, - REGIO_DATA_IN => cbm_regio_rx.data, - REGIO_TIMEOUT_IN => cbm_regio_rx.timeout, - REGIO_READ_ENABLE_IN => cbm_regio_rx.read, - REGIO_WRITE_ENABLE_IN => cbm_regio_rx.write, - - REGIO_DATA_OUT => cbm_regio_tx.data, - REGIO_DATAREADY_OUT => cbm_regio_tx.rack, - REGIO_WRITE_ACK_OUT => cbm_regio_tx.wack, - REGIO_NO_MORE_DATA_OUT => cbm_regio_tx.nack, - REGIO_UNKNOWN_ADDR_OUT => cbm_regio_tx.unknown - ); - - cbm_regio_tx.ack <= cbm_regio_tx.rack or cbm_regio_tx.wack; - - SFP_RATE_SEL(1) <= '1'; -- not supported by SFP, but in general, this should be the correct setting - LED_TRIGGER_GREEN <= not cbm_link_active_i; - LED_TRIGGER_RED <= '0'; - - --Internal Connection - med_read_in(4) <= '0'; - med_data_in(79 downto 64) <= (others => '0'); - med_packet_num_in(14 downto 12) <= (others => '0'); - med_dataready_in(4) <= '0'; - med_stat_op(79 downto 64) <= ( - 64+2 downto 64 => '1', -- ERROR_NC - 64 + 14 => '1', -- indicate "no signal" - others => '0'); - med_stat_debug(4*64+63 downto 4*64) <= (others => '0'); - - SFP_TXDIS(4 downto 2) <= (others => '1'); - - end generate; +-- --------------------------------------------------------------------------- +-- -- CBMNET stack +-- --------------------------------------------------------------------------- +-- GEN_CBMNET : if INCLUDE_CBMNET = c_YES generate +-- THE_CBM_BRIDGE : cbmnet_bridge +-- port map ( +-- -- clock and reset +-- CLK125_IN => clk_125_i, -- in std_logic; +-- ASYNC_RESET_IN => clear_i, +-- TRB_CLK_IN => clk_100_i, -- in std_logic; +-- TRB_RESET_IN => reset_i, -- in std_logic; +-- +-- CBM_CLK_OUT => cbm_clk_i, -- out std_logic; +-- CBM_RESET_OUT => cbm_reset_i, -- out std_logic; +-- +-- -- Media Interface +-- SD_RXD_P_IN => SFP_RX_P(5), +-- SD_RXD_N_IN => SFP_RX_N(5), +-- SD_TXD_P_OUT => SFP_TX_P(5), +-- SD_TXD_N_OUT => SFP_TX_N(5), +-- +-- SD_PRSNT_N_IN => SFP_MOD0(1), +-- SD_LOS_IN => SFP_LOS(1), +-- SD_TXDIS_OUT => SFP_TXDIS(1), +-- +-- LED_RX_OUT => cbm_phy_led_rx_i, +-- LED_TX_OUT => cbm_phy_led_tx_i, +-- LED_OK_OUT => cbm_phy_led_ok_i, +-- +-- -- Status and strobes +-- CBM_LINK_ACTIVE_OUT => cbm_link_active_i, +-- CBM_DLM_OUT => cbm_sync_dlm_sensed_i, -- out std_logic; +-- CBM_TIMING_TRIGGER_OUT => cbm_sync_timing_trigger_i, -- out std_logic; +-- CBM_SYNC_PULSER_OUT => cbm_sync_pulser_i, -- out std_logic; +-- +-- -- TRBNet Terminal +-- TRB_TRIGGER_IN => cts_trigger_out, +-- TRB_RDO_VALID_DATA_TRG_IN => cts_rdo_trg_data_valid, -- in std_logic; +-- TRB_RDO_VALID_NO_TIMING_IN => cts_rdo_valid_notiming_trg, -- in std_logic; +-- TRB_RDO_DATA_OUT => cts_rdo_additional(1).data, -- out std_logic_vector(31 downto 0); +-- TRB_RDO_WRITE_OUT => cts_rdo_additional(1).data_write, -- out std_logic; +-- TRB_RDO_FINISHED_OUT => cts_rdo_additional(1).data_finished, -- out std_logic; +-- +-- TRB_TRIGGER_OUT => cbm_etm_trigger_i, +-- +-- -- connect to hub +-- HUB_CTS_NUMBER_IN => hub_cts_number, -- in std_logic_vector (15 downto 0); +-- HUB_CTS_CODE_IN => hub_cts_code, -- in std_logic_vector (7 downto 0); +-- HUB_CTS_INFORMATION_IN => hub_cts_information, -- in std_logic_vector (7 downto 0); +-- HUB_CTS_READOUT_TYPE_IN => hub_cts_readout_type, -- in std_logic_vector (3 downto 0); +-- HUB_CTS_START_READOUT_IN => hub_cts_start_readout, -- in std_logic; +-- HUB_CTS_READOUT_FINISHED_OUT => hub_cts_readout_finished, -- out std_logic; --no more data, end transfer, send TRM +-- HUB_CTS_STATUS_BITS_OUT => hub_cts_status_bits, -- out std_logic_vector (31 downto 0); +-- HUB_FEE_DATA_IN => hub_fee_data, -- in std_logic_vector (15 downto 0); +-- HUB_FEE_DATAREADY_IN => hub_fee_dataready, -- in std_logic; +-- HUB_FEE_READ_OUT => hub_fee_read, -- out std_logic; --must be high when idle, otherwise you will never get a dataready +-- HUB_FEE_STATUS_BITS_IN => hub_fee_status_bits, -- in std_logic_vector (31 downto 0); +-- HUB_FEE_BUSY_IN => hub_fee_busy, -- in std_logic; +-- +-- -- connect to GbE +-- GBE_CTS_NUMBER_OUT => gbe_cts_number, -- out std_logic_vector (15 downto 0); +-- GBE_CTS_CODE_OUT => gbe_cts_code, -- out std_logic_vector (7 downto 0); +-- GBE_CTS_INFORMATION_OUT => gbe_cts_information, -- out std_logic_vector (7 downto 0); +-- GBE_CTS_READOUT_TYPE_OUT => gbe_cts_readout_type, -- out std_logic_vector (3 downto 0); +-- GBE_CTS_START_READOUT_OUT => gbe_cts_start_readout, -- out std_logic; +-- GBE_CTS_READOUT_FINISHED_IN => gbe_cts_readout_finished, -- in std_logic; --no more data, end transfer, send TRM +-- GBE_CTS_STATUS_BITS_IN => gbe_cts_status_bits, -- in std_logic_vector (31 downto 0); +-- GBE_FEE_DATA_OUT => gbe_fee_data, -- out std_logic_vector (15 downto 0); +-- GBE_FEE_DATAREADY_OUT => gbe_fee_dataready, -- out std_logic; +-- GBE_FEE_READ_IN => gbe_fee_read, -- in std_logic; --must be high when idle, otherwise you will never get a dataready +-- GBE_FEE_STATUS_BITS_OUT => gbe_fee_status_bits, -- out std_logic_vector (31 downto 0); +-- GBE_FEE_BUSY_OUT => gbe_fee_busy, -- out std_logic; +-- +-- -- reg io +-- --REGIO_IN => cbm_regio_rx, +-- --REGIO_OUT => cbm_regio_tx +-- REGIO_ADDR_IN => cbm_regio_rx.addr, +-- REGIO_DATA_IN => cbm_regio_rx.data, +-- REGIO_TIMEOUT_IN => cbm_regio_rx.timeout, +-- REGIO_READ_ENABLE_IN => cbm_regio_rx.read, +-- REGIO_WRITE_ENABLE_IN => cbm_regio_rx.write, +-- +-- REGIO_DATA_OUT => cbm_regio_tx.data, +-- REGIO_DATAREADY_OUT => cbm_regio_tx.rack, +-- REGIO_WRITE_ACK_OUT => cbm_regio_tx.wack, +-- REGIO_NO_MORE_DATA_OUT => cbm_regio_tx.nack, +-- REGIO_UNKNOWN_ADDR_OUT => cbm_regio_tx.unknown +-- ); +-- +-- cbm_regio_tx.ack <= cbm_regio_tx.rack or cbm_regio_tx.wack; +-- +-- SFP_RATE_SEL(1) <= '1'; -- not supported by SFP, but in general, this should be the correct setting +-- LED_TRIGGER_GREEN <= not cbm_link_active_i; +-- LED_TRIGGER_RED <= '0'; +-- +-- --Internal Connection +-- med_read_in(4) <= '0'; +-- med_data_in(79 downto 64) <= (others => '0'); +-- med_packet_num_in(14 downto 12) <= (others => '0'); +-- med_dataready_in(4) <= '0'; +-- med_stat_op(79 downto 64) <= ( +-- 64+2 downto 64 => '1', -- ERROR_NC +-- 64 + 14 => '1', -- indicate "no signal" +-- others => '0'); +-- med_stat_debug(4*64+63 downto 4*64) <= (others => '0'); +-- +-- SFP_TXDIS(4 downto 2) <= (others => '1'); +-- +-- end generate; GEN_NO_CBMNET : if INCLUDE_CBMNET = c_NO generate gbe_cts_number <= hub_cts_number; @@ -1840,6 +1883,27 @@ begin end generate; + GEN_MBS_MASTER : if INCLUDE_MBS_MASTER = c_YES generate + THE_MBS_MASTER : entity work.mbs_master + port map( + CLK => clk_100_i, + RESET_IN => reset_i, + + MBS_CLOCK_OUT => mbs_clock_i, + MBS_DATA_OUT => mbs_data_i, + + TRIGGER_IN => cts_rdo_trg_data_valid, + TRIGGER_NUMBER_IN => cts_rdo_trg_number, + DATA_OUT => cts_rdo_additional(1).data, + WRITE_OUT => cts_rdo_additional(1).data_write, + FINISHED_OUT => cts_rdo_additional(1).data_finished, + STATUSBIT_OUT => cts_rdo_additional(1).statusbits + ); + CLK_TEST_OUT(0) <= mbs_data_i; + CLK_TEST_OUT(1) <= mbs_clock_i; + end generate; + + ------------------------------------------------------------------------------- -- SFP POWER Entity ------------------------------------------------------------------------------- diff --git a/cts/trb3_central_constraints_3.lpf b/cts/trb3_central_constraints_3.lpf index 8a552fa..8a0dee3 100644 --- a/cts/trb3_central_constraints_3.lpf +++ b/cts/trb3_central_constraints_3.lpf @@ -29,6 +29,7 @@ FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch2" 10 FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_rx_ch3" 100.0 MHz; FREQUENCY NET "THE_MEDIA_ONBOARD/gen_serdes_200.THE_SERDES/refclkdiv2_tx_ch" 100.0 MHz; FREQUENCY NET "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "GBE/clk_125_rx_from_pcs[3]" 125 MHz; FREQUENCY NET "osc_int" 200.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.1.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; FREQUENCY NET "GEN_TDC.THE_TDC/GEN_Channels.2.Channels/Channel200/FSM_RD_STATE[2]" 100.0 MHz; @@ -44,7 +45,7 @@ GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# -LOCATE COMP "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSD_INST" SITE "PCSB" ; +# LOCATE COMP "GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/PCSD_INST" SITE "PCSB" ; LOCATE COMP "GBE/physical_impl_gen.physical/impl_gen.gbe_serdes/PCSD_INST" SITE "PCSB"; @@ -135,21 +136,21 @@ LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.3.gen_iobufs.1.gen_iobuf.IOBUF/GEN_IBUF. LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs.2.gen_iobufs.0.gen_iobuf.IOBUF/GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF" ; # #GbE Part -UGROUP "tsmac" - BLKNAME GBE/imp_gen.MAC - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS - BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER - BLKNAME GBE/FRAME_TRANSMITTER; -UGROUP "controllers" - BLKNAME GBE/main_gen.MAIN_CONTROL - BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER - BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER; -UGROUP "gbe_rx_tx" - BLKNAME GBE/FRAME_CONSTRUCTOR - BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG - BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR - BLKNAME GBE/setup_imp_gen.SETUP; +# UGROUP "tsmac" +# BLKNAME GBE/imp_gen.MAC +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SGMII_GBE_PCS +# BLKNAME GBE/rx_enable_gen.FRAME_RECEIVER +# BLKNAME GBE/FRAME_TRANSMITTER; +# UGROUP "controllers" +# BLKNAME GBE/main_gen.MAIN_CONTROL +# BLKNAME GBE/rx_enable_gen.RECEIVE_CONTROLLER +# BLKNAME GBE/transmit_gen.TRANSMIT_CONTROLLER; +# UGROUP "gbe_rx_tx" +# BLKNAME GBE/FRAME_CONSTRUCTOR +# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/MB_IP_CONFIG +# BLKNAME GBE/main_gen.MAIN_CONTROL/protocol_selector/TrbNetData/THE_IP_CONFIGURATOR +# BLKNAME GBE/setup_imp_gen.SETUP; #REGION "GBE_REGION" "R20C65D" 36 42 DEVSIZE; #REGION "MED0" "R81C30D" 34 40 DEVSIZE; @@ -158,96 +159,96 @@ UGROUP "gbe_rx_tx" #LOCATE UGROUP "controllers" REGION "GBE_MAIN_REGION" ; #LOCATE UGROUP "gbe_rx_tx" REGION "GBE_MAIN_REGION" ; -UGROUP "sd_tx_to_pcs" - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; -UGROUP "sd_rx_to_pcs" - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7] - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; -UGROUP "pcs_tx_to_mac" - BLKNAME GBE/pcs_tx_en_q - BLKNAME GBE/pcs_tx_en_qq - BLKNAME GBE/pcs_tx_er_q - BLKNAME GBE/pcs_tx_er_qq - BLKNAME GBE/pcs_txd_q[0] - BLKNAME GBE/pcs_txd_q[1] - BLKNAME GBE/pcs_txd_q[2] - BLKNAME GBE/pcs_txd_q[3] - BLKNAME GBE/pcs_txd_q[4] - BLKNAME GBE/pcs_txd_q[5] - BLKNAME GBE/pcs_txd_q[6] - BLKNAME GBE/pcs_txd_q[7] - BLKNAME GBE/pcs_txd_qq[0] - BLKNAME GBE/pcs_txd_qq[1] - BLKNAME GBE/pcs_txd_qq[2] - BLKNAME GBE/pcs_txd_qq[3] - BLKNAME GBE/pcs_txd_qq[4] - BLKNAME GBE/pcs_txd_qq[5] - BLKNAME GBE/pcs_txd_qq[6] - BLKNAME GBE/pcs_txd_qq[7]; -UGROUP "pcs_rx_to_mac" - BLKNAME GBE/pcs_rx_en_q - BLKNAME GBE/pcs_rx_en_qq - BLKNAME GBE/pcs_rx_er_q - BLKNAME GBE/pcs_rx_er_qq - BLKNAME GBE/pcs_rxd_q[0] - BLKNAME GBE/pcs_rxd_q[1] - BLKNAME GBE/pcs_rxd_q[2] - BLKNAME GBE/pcs_rxd_q[3] - BLKNAME GBE/pcs_rxd_q[4] - BLKNAME GBE/pcs_rxd_q[5] - BLKNAME GBE/pcs_rxd_q[6] - BLKNAME GBE/pcs_rxd_q[7] - BLKNAME GBE/pcs_rxd_qq[0] - BLKNAME GBE/pcs_rxd_qq[1] - BLKNAME GBE/pcs_rxd_qq[2] - BLKNAME GBE/pcs_rxd_qq[3] - BLKNAME GBE/pcs_rxd_qq[4] - BLKNAME GBE/pcs_rxd_qq[5] - BLKNAME GBE/pcs_rxd_qq[6] - BLKNAME GBE/pcs_rxd_qq[7]; +# UGROUP "sd_tx_to_pcs" +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_correct_disp_q +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[0] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[1] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[2] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[3] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[4] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[5] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[6] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_data_q[7] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_TX_PROC_sd_tx_kcntl_q; +# UGROUP "sd_rx_to_pcs" +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_cv_error_q +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[0] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[1] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[2] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[3] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[4] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[5] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[6] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_data_q[7] +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_disp_error_q +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/SYNC_RX_PROC_sd_rx_kcntl_q; +# UGROUP "pcs_tx_to_mac" +# BLKNAME GBE/pcs_tx_en_q +# BLKNAME GBE/pcs_tx_en_qq +# BLKNAME GBE/pcs_tx_er_q +# BLKNAME GBE/pcs_tx_er_qq +# BLKNAME GBE/pcs_txd_q[0] +# BLKNAME GBE/pcs_txd_q[1] +# BLKNAME GBE/pcs_txd_q[2] +# BLKNAME GBE/pcs_txd_q[3] +# BLKNAME GBE/pcs_txd_q[4] +# BLKNAME GBE/pcs_txd_q[5] +# BLKNAME GBE/pcs_txd_q[6] +# BLKNAME GBE/pcs_txd_q[7] +# BLKNAME GBE/pcs_txd_qq[0] +# BLKNAME GBE/pcs_txd_qq[1] +# BLKNAME GBE/pcs_txd_qq[2] +# BLKNAME GBE/pcs_txd_qq[3] +# BLKNAME GBE/pcs_txd_qq[4] +# BLKNAME GBE/pcs_txd_qq[5] +# BLKNAME GBE/pcs_txd_qq[6] +# BLKNAME GBE/pcs_txd_qq[7]; +# UGROUP "pcs_rx_to_mac" +# BLKNAME GBE/pcs_rx_en_q +# BLKNAME GBE/pcs_rx_en_qq +# BLKNAME GBE/pcs_rx_er_q +# BLKNAME GBE/pcs_rx_er_qq +# BLKNAME GBE/pcs_rxd_q[0] +# BLKNAME GBE/pcs_rxd_q[1] +# BLKNAME GBE/pcs_rxd_q[2] +# BLKNAME GBE/pcs_rxd_q[3] +# BLKNAME GBE/pcs_rxd_q[4] +# BLKNAME GBE/pcs_rxd_q[5] +# BLKNAME GBE/pcs_rxd_q[6] +# BLKNAME GBE/pcs_rxd_q[7] +# BLKNAME GBE/pcs_rxd_qq[0] +# BLKNAME GBE/pcs_rxd_qq[1] +# BLKNAME GBE/pcs_rxd_qq[2] +# BLKNAME GBE/pcs_rxd_qq[3] +# BLKNAME GBE/pcs_rxd_qq[4] +# BLKNAME GBE/pcs_rxd_qq[5] +# BLKNAME GBE/pcs_rxd_qq[6] +# BLKNAME GBE/pcs_rxd_qq[7]; -UGROUP "GBE_SERDES_group" BBOX 10 67 - BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES; -LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ; +# UGROUP "GBE_SERDES_group" BBOX 10 67 +# BLKNAME GBE/imp_gen.serdes_intclk_gen.PCS_SERDES; +# LOCATE UGROUP "GBE_SERDES_group" SITE "R105C17D" ; -MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ; -MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ; +# MAXDELAY NET "GBE/pcs_rx_e?_q" 1.500000 nS ; +# MAXDELAY NET "GBE/pcs_rxd_q[?]" 1.500000 nS ; -DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q" - "GBE/pcs_rx_er_q" - "GBE/pcs_rxd_q*"; -INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ; +# DEFINE PORT GROUP "RX_GRP" "GBE/pcs_rx_en_q" +# "GBE/pcs_rx_er_q" +# "GBE/pcs_rxd_q*"; +# INPUT_SETUP GROUP "RX_GRP" 3.500000 ns HOLD 0.000000 ns CLKPORT "GBE/serdes_rx_clk_c" ; -PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ; -PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; -PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; -PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; +# PRIORITIZE NET "GBE/pcs_rx_en_q" 100 ; +# PRIORITIZE NET "GBE/pcs_rx_er_q" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[1]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[2]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[3]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[4]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[5]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[6]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[7]" 100 ; +# PRIORITIZE NET "GBE/pcs_rxd_q[0]" 100 ; +# PRIORITIZE NET "GBE/serdes_rx_clk_c" 80 ; LOCATE UGROUP "CBMNET_PHY_GROUP" SITE "R100C118D"; -- 2.43.0