From 2bd4e91797e627a3507ae82c9b64f13bd2265406 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Mon, 24 Jan 2022 08:27:46 +0100 Subject: [PATCH] first SerDes based delay measurement test --- cts/trb3sc_cts.prj | 2 ++ cts/trb3sc_cts.vhd | 40 ++++++++++++++++++++++++++++++++++------ 2 files changed, 36 insertions(+), 6 deletions(-) diff --git a/cts/trb3sc_cts.prj b/cts/trb3sc_cts.prj index e271d83..8c31ac5 100644 --- a/cts/trb3sc_cts.prj +++ b/cts/trb3sc_cts.prj @@ -139,6 +139,8 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" +add_file -vhdl -lib work "../../trbnet/special/phaser.vhd" + #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" diff --git a/cts/trb3sc_cts.vhd b/cts/trb3sc_cts.vhd index 96f0125..745ecad 100644 --- a/cts/trb3sc_cts.vhd +++ b/cts/trb3sc_cts.vhd @@ -253,7 +253,12 @@ architecture trb3sc_arch of trb3sc_cts is signal rst_ctrs_sc : std_logic; signal tx_rst_i : std_logic; signal tx_rst_x : std_logic; - + + signal wap_requested_i : std_logic_vector(3 downto 0); + signal rx_index_i : std_logic_vector(3 downto 0); + signal phaser_data : std_logic_vector(31 downto 0); + signal phaser_update : std_logic; + -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; -- attribute syn_keep of tx_dlm_i : signal is true; @@ -381,6 +386,8 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate DESTROY_LINK_IN(1) => '0', DESTROY_LINK_IN(2) => '0', DESTROY_LINK_IN(3) => destroy_link_i, + WAP_REQUESTED_IN => wap_requested_i, + RX_INDEX_OUT => rx_index_i, --SFP Connection SD_PRSNT_N_IN(0) => '1', SD_LOS_IN(0) => '1', @@ -420,6 +427,21 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate LINK_TX_READY_OUT => link_tx_ready_i, STATE_OUT => tx_reset_state ); + + -------------------------------------------------------------------- + -------------------------------------------------------------------- + THE_PHASER: entity phaser + port map( + SAMPLE_CLK => CLK_SUPPL_PCLK, + RESET => reset_i, + SIGNAL_A_IN => word_sync_i, + SIGNAL_B_IN => rx_index_i(3), + LOW_CNT_OUT => phaser_data(15 downto 0), + HI_CNT_OUT => phaser_data(31 downto 16), + UPDATE_OUT => phaser_update + ); + -------------------------------------------------------------------- + -------------------------------------------------------------------- PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 @@ -428,8 +450,9 @@ gen_PCSB : if USE_BACKPLANE = c_NO and USE_ADDON = c_NO generate send_rst_i <= test_reg(30); destroy_link_i <= test_reg(24); send_dlm_word_i <= std_logic_vector(dlm_tag_ctr); --test_reg(15 downto 8); - send_rst_word_i <= test_reg(7 downto 0); - + send_rst_word_i <= test_reg(15 downto 8); + wap_requested_i <= test_reg(3 downto 0); + tx_dlm_i <= dlm_send_qq; -- LED feedback @@ -503,10 +526,15 @@ end generate; --------------------------------------------------------------------------- -- PCSC: not used --------------------------------------------------------------------------- - bussci3_tx.data <= (others => '0'); - bussci3_tx.ack <= '0'; + bussci3_tx.data <= phaser_data; + bussci3_tx.ack <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); bussci3_tx.nack <= '0'; - bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); + bussci3_tx.unknown <= '0'; + +-- bussci3_tx.data <= (others => '0'); +-- bussci3_tx.ack <= '0'; +-- bussci3_tx.nack <= '0'; +-- bussci3_tx.unknown <= bussci3_rx.read or bussci3_rx.write when rising_edge(clk_sys); --------------------------------------------------------------------------- -- PCSD: GbE -- 2.43.0