From 2d3d15f482fdc04486689d985cd474139726587b Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 10 Mar 2010 18:24:48 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/pll_in100_out25.lpc | 56 +++++ lattice/ecp2m/pll_in100_out25.vhd | 120 +++++++++ pinout/mdchub_fpga1234.lpf | 254 +++++++++++++++++++ pinout/mdchub_fpga5.lpf | 389 ++++++++++++++++++++++++++++++ special/spi_databus_memory.vhd | 5 +- 5 files changed, 823 insertions(+), 1 deletion(-) create mode 100644 lattice/ecp2m/pll_in100_out25.lpc create mode 100644 lattice/ecp2m/pll_in100_out25.vhd create mode 100644 pinout/mdchub_fpga1234.lpf create mode 100644 pinout/mdchub_fpga5.lpf diff --git a/lattice/ecp2m/pll_in100_out25.lpc b/lattice/ecp2m/pll_in100_out25.lpc new file mode 100644 index 0000000..5c5a0c8 --- /dev/null +++ b/lattice/ecp2m/pll_in100_out25.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.1 +ModuleName=pll_in100_out25 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=03/10/2010 +Time=19:09:50 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=100 +OFrq=25.000000 +KFrq= +U_OFrq=25 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=4 +Mult=1 +Post=48 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=AUTO_NO_DELAY +External=AUTO +PCDR=0 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/lattice/ecp2m/pll_in100_out25.vhd b/lattice/ecp2m/pll_in100_out25.vhd new file mode 100644 index 0000000..a1a7468 --- /dev/null +++ b/lattice/ecp2m/pll_in100_out25.vhd @@ -0,0 +1,120 @@ +-- VHDL netlist generated by SCUBA ispLever_v8.0_PROD_Build (41) +-- Module Version: 5.1 +--/opt/lattice/ispLEVER8.0/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out25 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 25 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap AUTO -noclkos -noclkok -norst -e + +-- Wed Mar 10 19:09:50 2010 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_in100_out25 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : boolean; + attribute dont_touch of pll_in100_out25 : entity is true; +end pll_in100_out25; + +architecture Structure of pll_in100_out25 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "AUTO"; + attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "25.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "48"; + attribute CLKFB_DIV of PLLDInst_0 : label is "1"; + attribute CLKI_DIV of PLLDInst_0 : label is "4"; + attribute FIN of PLLDInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "AUTO", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 48, + CLKFB_DIV=> 1, CLKI_DIV=> 4) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_in100_out25 is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/pinout/mdchub_fpga1234.lpf b/pinout/mdchub_fpga1234.lpf new file mode 100644 index 0000000..1c53675 --- /dev/null +++ b/pinout/mdchub_fpga1234.lpf @@ -0,0 +1,254 @@ +##################################################################### +# Default +##################################################################### + IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + COMMERCIAL ; + BLOCK RESETPATHS ; + BLOCK ASYNCPATHS ; + +##################################################################### +# Clocks & Resets +##################################################################### + + LOCATE COMP "RESET_IN" SITE "AD1"; + IOBUF PORT "RESET_IN" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "CLK_100_IN" SITE "M29"; + IOBUF PORT "CLK_100_IN" IO_TYPE=LVDS25 PULLMODE=NONE ; + + LOCATE COMP "CLK_125_IN" SITE "P28"; + IOBUF PORT "CLK_125_IN" IO_TYPE=LVDS25 PULLMODE=NONE ; + +##################################################################### +# Test connector +##################################################################### + LOCATE COMP "TEST_LINE_0" SITE "F7"; + LOCATE COMP "TEST_LINE_1" SITE "D8"; + LOCATE COMP "TEST_LINE_2" SITE "J13"; + LOCATE COMP "TEST_LINE_3" SITE "G11"; + LOCATE COMP "TEST_LINE_4" SITE "H13"; + LOCATE COMP "TEST_LINE_5" SITE "H12"; + LOCATE COMP "TEST_LINE_6" SITE "E8"; + LOCATE COMP "TEST_LINE_7" SITE "D9"; + LOCATE COMP "TEST_LINE_8" SITE "D12"; + LOCATE COMP "TEST_LINE_9" SITE "E13"; + LOCATE COMP "TEST_LINE_10" SITE "J12"; + LOCATE COMP "TEST_LINE_11" SITE "H10"; + LOCATE COMP "TEST_LINE_12" SITE "E12"; + LOCATE COMP "TEST_LINE_13" SITE "D11"; + LOCATE COMP "TEST_LINE_14" SITE "H11"; + LOCATE COMP "TEST_LINE_15" SITE "F11"; + + DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; + IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +##################################################################### +# Flash & Reboot Control +##################################################################### + + LOCATE COMP "PROGRAMB_OUT" SITE "AD3"; + IOBUF PORT "PROGRAMB_OUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "SPI_CLK_OUT" SITE "T8"; # LOGIC_SPI_CLK_FPGA + LOCATE COMP "SPI_CS_OUT" SITE "U7"; # LOGIC_SPI_CS_FPGA + LOCATE COMP "SPI_SI_OUT" SITE "R3"; # LOGIC_SPI_INP_FPGA + LOCATE COMP "SPI_SO_IN" SITE "R2"; # LOGIC_SPI_OUT_FPGA + DEFINE PORT GROUP "SPI_group" "SPI*" ; + IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + LOCATE COMP "FPGA_NUMBER_IN_0" SITE "J18"; + LOCATE COMP "FPGA_NUMBER_IN_1" SITE "J19"; + DEFINE PORT GROUP "FPGA_group" "FPGA_NUMBER*" ; + IOBUF GROUP "FPGA_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + +##################################################################### +# FOT Control +##################################################################### + LOCATE COMP "SD_1" SITE "Y1"; + LOCATE COMP "SD_2" SITE "Y6"; + LOCATE COMP "SD_3" SITE "Y3"; + LOCATE COMP "SD_4" SITE "Y8"; + LOCATE COMP "SD_5" SITE "AB2"; + LOCATE COMP "SD_6" SITE "AA6"; + LOCATE COMP "SD_7" SITE "AA8"; + LOCATE COMP "SD_8" SITE "AC2"; + DEFINE PORT GROUP "SD_group" "SD*" ; + IOBUF GROUP "SD_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + +##################################################################### +# LED +##################################################################### + LOCATE COMP "LED_RX_1" SITE "Y4"; + LOCATE COMP "LED_RX_2" SITE "Y5"; + LOCATE COMP "LED_RX_3" SITE "AA1"; + LOCATE COMP "LED_RX_4" SITE "AB1"; + LOCATE COMP "LED_RX_5" SITE "Y7"; + LOCATE COMP "LED_RX_6" SITE "AB3"; + LOCATE COMP "LED_RX_7" SITE "AB4"; + LOCATE COMP "LED_RX_8" SITE "AA9"; + DEFINE PORT GROUP "LEDRX_group" "LED_RX*" ; + IOBUF GROUP "LEDRX_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "LED_NC_1" SITE "W2"; + LOCATE COMP "LED_NC_2" SITE "Y2"; + LOCATE COMP "LED_NC_3" SITE "AA2"; + LOCATE COMP "LED_NC_4" SITE "Y9"; + LOCATE COMP "LED_NC_5" SITE "AA7"; + LOCATE COMP "LED_NC_6" SITE "AA5"; + LOCATE COMP "LED_NC_7" SITE "AB5"; + LOCATE COMP "LED_NC_8" SITE "AC1"; + DEFINE PORT GROUP "LEDNC_group" "LED_NC*" ; + IOBUF GROUP "LEDNC_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "LED_GREEN" SITE "N9"; + LOCATE COMP "LED_ORANGE" SITE "K1"; + LOCATE COMP "LED_RED" SITE "J3"; + LOCATE COMP "LED_YELLOW" SITE "J1"; + IOBUF PORT "LED_GREEN" IO_TYPE=LVCMOS25 PULLMODE=UP ; + IOBUF PORT "LED_ORANGE" IO_TYPE=LVCMOS25 PULLMODE=UP ; + IOBUF PORT "LED_RED" IO_TYPE=LVCMOS25 PULLMODE=UP ; + IOBUF PORT "LED_YELLOW" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +##################################################################### +# Onewire +##################################################################### + LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "Y27"; + IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +##################################################################### +# Inter-FPGA LVDS/LVCMOS +##################################################################### + LOCATE COMP "F5_0" SITE "U26"; + LOCATE COMP "F5_1" SITE "V26"; + LOCATE COMP "F5_2" SITE "V23"; + LOCATE COMP "F5_3" SITE "U23"; + LOCATE COMP "F5_4" SITE "U27"; + LOCATE COMP "F5_5" SITE "U28"; + LOCATE COMP "F5_6" SITE "V25"; + LOCATE COMP "F5_7" SITE "V24"; + LOCATE COMP "F5_8" SITE "W28"; + LOCATE COMP "F5_9" SITE "W27"; + LOCATE COMP "F5_10" SITE "U30"; + LOCATE COMP "F5_11" SITE "V30"; + LOCATE COMP "F5_12" SITE "V29"; + LOCATE COMP "F5_13" SITE "U29"; + LOCATE COMP "F5_14" SITE "W26"; + LOCATE COMP "F5_15" SITE "W25"; + LOCATE COMP "F5_16" SITE "W29"; + LOCATE COMP "F5_17" SITE "W30"; + LOCATE COMP "F5_18" SITE "Y26"; +# LOCATE COMP "F_19" SITE "Y27"; + DEFINE PORT GROUP "F5_group" "F5*" ; + IOBUF GROUP "F5_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + + LOCATE COMP "MESHX_0" SITE "K6"; + LOCATE COMP "MESHX_1" SITE "K5"; + LOCATE COMP "MESHX_2" SITE "L8"; + LOCATE COMP "MESHX_3" SITE "L6"; + LOCATE COMP "MESHX_4" SITE "H3"; + LOCATE COMP "MESHX_5" SITE "H2"; + + LOCATE COMP "MESHY_0" SITE "G5"; + LOCATE COMP "MESHY_1" SITE "G4"; + LOCATE COMP "MESHY_2" SITE "K7"; + LOCATE COMP "MESHY_3" SITE "K8"; + LOCATE COMP "MESHY_4" SITE "E1"; + LOCATE COMP "MESHY_5" SITE "F2"; + + LOCATE COMP "MESHZ_0" SITE "H5"; + LOCATE COMP "MESHZ_1" SITE "H4"; + LOCATE COMP "MESHZ_2" SITE "J5"; + LOCATE COMP "MESHZ_3" SITE "J4"; + LOCATE COMP "MESHZ_4" SITE "G2"; + LOCATE COMP "MESHZ_5" SITE "G1"; + DEFINE PORT GROUP "MESH_group" "MESH*" ; + IOBUF GROUP "MESH_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +##################################################################### +# Unused Locates +##################################################################### +# LOCATE COMP "TXN_1" SITE "B26"; +# LOCATE COMP "TXN_2" SITE "B25"; +# LOCATE COMP "TXN_3" SITE "B23"; +# LOCATE COMP "TXN_4" SITE "B22"; +# LOCATE COMP "TXN_5" SITE "B9"; +# LOCATE COMP "TXN_6" SITE "B8"; +# LOCATE COMP "TXN_7" SITE "B6"; +# LOCATE COMP "TXN_8" SITE "B5"; +# LOCATE COMP "TXP_1" SITE "A26"; +# LOCATE COMP "TXP_2" SITE "A25"; +# LOCATE COMP "TXP_3" SITE "A23"; +# LOCATE COMP "TXP_4" SITE "A22"; +# LOCATE COMP "TXP_5" SITE "A9"; +# LOCATE COMP "TXP_6" SITE "A8"; +# LOCATE COMP "TXP_7" SITE "A6"; +# LOCATE COMP "TXP_8" SITE "A5"; + +# LOCATE COMP "RXN_1" SITE "B29"; +# LOCATE COMP "RXN_2" SITE "B28"; +# LOCATE COMP "RXN_3" SITE "B20"; +# LOCATE COMP "RXN_4" SITE "B19"; +# LOCATE COMP "RXN_5" SITE "B12"; +# LOCATE COMP "RXN_6" SITE "B11"; +# LOCATE COMP "RXN_7" SITE "B3"; +# LOCATE COMP "RXN_8" SITE "B2"; +# LOCATE COMP "RXP_1" SITE "A29"; +# LOCATE COMP "RXP_2" SITE "A28"; +# LOCATE COMP "RXP_3" SITE "A20"; +# LOCATE COMP "RXP_4" SITE "A19"; +# LOCATE COMP "RXP_5" SITE "A12"; +# LOCATE COMP "RXP_6" SITE "A11"; +# LOCATE COMP "RXP_7" SITE "A3"; +# LOCATE COMP "RXP_8" SITE "A2"; + +# LOCATE COMP "S100_1TO5_OUTN" SITE "AJ9"; +# LOCATE COMP "S125_1TO5_INP" SITE "AK29"; +# LOCATE COMP "S100_1TO5_OUTP" SITE "AK9"; +# LOCATE COMP "S125_1TO5_INN" SITE "AJ29"; +# LOCATE COMP "S125_1TO5_OUTN" SITE "AJ26"; +# LOCATE COMP "S100_1TO5_INN" SITE "AJ12"; +# LOCATE COMP "S100_1TO5_INP" SITE "AK12"; +# LOCATE COMP "S125_1TO5_OUTP" SITE "AK26"; + +# LOCATE COMP "LLC_INN3_FPGA" SITE "AJ2"; +# LOCATE COMP "LLC_INN2_FPGA" SITE "AJ3"; +# LOCATE COMP "LLC_INN1_FPGA" SITE "AJ11"; +# LOCATE COMP "LLC_INP1_FPGA" SITE "AK11"; +# LOCATE COMP "LLC_INP2_FPGA" SITE "AK3"; +# LOCATE COMP "LLC_INP3_FPGA" SITE "AK2"; +# LOCATE COMP "LLC_OUTN1_FPGA" SITE "AJ8"; +# LOCATE COMP "LLC_OUTN2_FPGA" SITE "AJ6"; +# LOCATE COMP "LLC_OUTN3_FPGA" SITE "AJ5"; +# LOCATE COMP "LLC_OUTP1_FPGA" SITE "AK8"; +# LOCATE COMP "LLC_OUTP2_FPGA" SITE "AK6"; +# LOCATE COMP "LLC_OUTP3_FPGA" SITE "AK5"; + +# LOCATE COMP "LRC_INN2_FPGA" SITE "AJ20"; +# LOCATE COMP "LRC_INP2_FPGA" SITE "AK20"; +# LOCATE COMP "LRC_OUTN2_FPGA" SITE "AJ23"; +# LOCATE COMP "LRC_OUTP2_FPGA" SITE "AK23"; + +# LOCATE COMP "DONE_FPGA" SITE "AF27"; +# LOCATE COMP "INITN_FPGA" SITE "AC24"; +# LOCATE COMP "JTAG_TCK" SITE "AE2"; +# LOCATE COMP "JTAG_TDI" SITE "AE1"; +# LOCATE COMP "JTAG_TMS" SITE "AF2"; + +# LOCATE COMP "S_F4TOF1_INP" SITE "AK25"; +# LOCATE COMP "S_F1TOF2_INP" SITE "AK19"; +# LOCATE COMP "S_F1TOF2_INN" SITE "AJ19"; +# LOCATE COMP "S_F1TOF2_OUTN" SITE "AJ22"; +# LOCATE COMP "S_F4TOF1_OUTN" SITE "AJ28"; +# LOCATE COMP "S_F4TOF1_OUTP" SITE "AK28"; +# LOCATE COMP "S_F1TOF2_OUTP" SITE "AK22"; +# LOCATE COMP "S_F4TOF1_INN" SITE "AJ25"; + +# LOCATE COMP "SPI_CLK_FPGA" SITE "AG29"; +# LOCATE COMP "SPI_CS_FPGA" SITE "AA22"; +# LOCATE COMP "SPI_FAST_FPGA" SITE "AF29"; +# LOCATE COMP "SPI_IN_FPGA" SITE "AA23"; +# LOCATE COMP "SPI_OUT_FPGA" SITE "AD30"; + +# LOCATE COMP "TDO_F_1" SITE "AF1"; \ No newline at end of file diff --git a/pinout/mdchub_fpga5.lpf b/pinout/mdchub_fpga5.lpf new file mode 100644 index 0000000..5c2e29e --- /dev/null +++ b/pinout/mdchub_fpga5.lpf @@ -0,0 +1,389 @@ +##################################################################### +# Default +##################################################################### + IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + COMMERCIAL ; + BLOCK RESETPATHS ; + BLOCK ASYNCPATHS ; + +##################################################################### +# Clocks & Resets +##################################################################### + + LOCATE COMP "RESET_IN" SITE "AD1"; + IOBUF PORT "RESET_IN" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "CLK_100_IN" SITE "P28"; + IOBUF PORT "CLK_100_IN" IO_TYPE=LVDS25 PULLMODE=NONE ; + + LOCATE COMP "CLK_125_IN" SITE "T5"; + IOBUF PORT "CLK_125_IN" IO_TYPE=LVDS25 PULLMODE=NONE ; + +##################################################################### +# Test connector +##################################################################### + LOCATE COMP "TEST_LINE_0" SITE "J26"; + LOCATE COMP "TEST_LINE_1" SITE "H26"; + LOCATE COMP "TEST_LINE_2" SITE "H27"; + LOCATE COMP "TEST_LINE_3" SITE "G26"; + LOCATE COMP "TEST_LINE_4" SITE "H23"; + LOCATE COMP "TEST_LINE_5" SITE "H24"; + LOCATE COMP "TEST_LINE_6" SITE "D28"; + LOCATE COMP "TEST_LINE_7" SITE "E28"; + LOCATE COMP "TEST_LINE_8" SITE "G24"; + LOCATE COMP "TEST_LINE_9" SITE "H25"; + LOCATE COMP "TEST_LINE_10" SITE "D27"; + LOCATE COMP "TEST_LINE_11" SITE "E27"; + LOCATE COMP "TEST_LINE_12" SITE "F26"; + LOCATE COMP "TEST_LINE_13" SITE "G25"; + LOCATE COMP "TEST_LINE_14" SITE "F24"; + LOCATE COMP "TEST_LINE_15" SITE "F25"; + + DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; + IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +##################################################################### +# Onewire +##################################################################### + LOCATE COMP "ONEWIRE" SITE "AG19"; + IOBUF PORT "ONEWIRE" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "ONEWIRE_MONITOR_OUT_1" SITE "AB26"; + LOCATE COMP "ONEWIRE_MONITOR_OUT_2" SITE "P2"; + LOCATE COMP "ONEWIRE_MONITOR_OUT_3" SITE "AD1"; + LOCATE COMP "ONEWIRE_MONITOR_OUT_4" SITE "W27"; + DEFINE PORT GROUP "ONEWIRE_MONITOR_group" "ONEWIRE_MONITOR*" ; + IOBUF GROUP "ONEWIRE_MONITOR_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +##################################################################### +# SFP +##################################################################### + LOCATE COMP "GBE_LOS" SITE "AG8"; + LOCATE COMP "GBE_MOD_0" SITE "AF8"; + LOCATE COMP "GBE_MOD_1" SITE "AE15"; + LOCATE COMP "GBE_MOD_2" SITE "AC15"; + LOCATE COMP "GBE_RATE_SEL" SITE "AD15"; + LOCATE COMP "GBE_TXDIS" SITE "AD14"; + LOCATE COMP "GBE_TX_FAULT" SITE "AF12"; + DEFINE PORT GROUP "GBE_group" "GBE*" ; + IOBUF GROUP "GBE_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "TRBNET_LOS" SITE "AG9"; + LOCATE COMP "TRBNET_MOD_0" SITE "AH14"; + LOCATE COMP "TRBNET_MOD_1" SITE "AG12"; + LOCATE COMP "TRBNET_MOD_2" SITE "AG15"; + LOCATE COMP "TRBNET_RATE_SEL" SITE "AG13"; + LOCATE COMP "TRBNET_TXDIS" SITE "AG10"; + LOCATE COMP "TRBNET_TX_FAULT" SITE "AF15"; + DEFINE PORT GROUP "TRB_group" "TRB*" ; + IOBUF GROUP "TRB_group" IO_TYPE=LVTTL33 PULLMODE=UP ; + + + +##################################################################### +# Flash & Reboot Control +##################################################################### + + LOCATE COMP "PROGRAMB_OUT" SITE "AJ14"; + IOBUF PORT "PROGRAMB_OUT" IO_TYPE=LVTTL33 PULLMODE=UP ; + + LOCATE COMP "SPI_CLK_OUT" SITE "AE21"; # LOGIC_SPI_CLK_FPGA + LOCATE COMP "SPI_CS_OUT" SITE "AE20"; # LOGIC_SPI_CS_FPGA + LOCATE COMP "SPI_SI_OUT" SITE "AC23"; # LOGIC_SPI_INP_FPGA + LOCATE COMP "SPI_SO_IN" SITE "AD23"; # LOGIC_SPI_OUT_FPGA + DEFINE PORT GROUP "SPI_group" "SPI*" ; + IOBUF GROUP "SPI_group" IO_TYPE=LVTTL33 PULLMODE=DOWN ; + + +##################################################################### +# Inter-FPGA +##################################################################### + LOCATE COMP "F1_0" SITE "U30"; + LOCATE COMP "F1_1" SITE "V30"; + LOCATE COMP "F1_2" SITE "V29"; + LOCATE COMP "F1_3" SITE "U29"; + LOCATE COMP "F1_4" SITE "W26"; + LOCATE COMP "F1_5" SITE "W25"; + LOCATE COMP "F1_6" SITE "W29"; + LOCATE COMP "F1_7" SITE "W30"; + LOCATE COMP "F1_8" SITE "Y26"; + LOCATE COMP "F1_9" SITE "Y27"; + LOCATE COMP "F1_10" SITE "V22"; + LOCATE COMP "F1_11" SITE "W22"; + LOCATE COMP "F1_12" SITE "Y29"; + LOCATE COMP "F1_13" SITE "Y30"; + LOCATE COMP "F1_14" SITE "Y28"; + LOCATE COMP "F1_15" SITE "AA29"; + LOCATE COMP "F1_16" SITE "Y25"; + LOCATE COMP "F1_17" SITE "Y24"; + LOCATE COMP "F1_18" SITE "AB27"; +# LOCATE COMP "F1_19" SITE "AB26"; + + LOCATE COMP "F2_0" SITE "H3"; + LOCATE COMP "F2_1" SITE "H2"; + LOCATE COMP "F2_2" SITE "J3"; + LOCATE COMP "F2_3" SITE "J2"; + LOCATE COMP "F2_4" SITE "L5"; + LOCATE COMP "F2_5" SITE "L4"; + LOCATE COMP "F2_6" SITE "K2"; + LOCATE COMP "F2_7" SITE "K1"; + LOCATE COMP "F2_8" SITE "M6"; + LOCATE COMP "F2_9" SITE "M5"; + LOCATE COMP "F2_10" SITE "M4"; + LOCATE COMP "F2_11" SITE "M3"; + LOCATE COMP "F2_12" SITE "L3"; + LOCATE COMP "F2_13" SITE "L2"; + LOCATE COMP "F2_14" SITE "L1"; + LOCATE COMP "F2_15" SITE "M2"; + LOCATE COMP "F2_16" SITE "M1"; + LOCATE COMP "F2_17" SITE "N2"; + LOCATE COMP "F2_18" SITE "P3"; +# LOCATE COMP "F2_19" SITE "P2"; + + LOCATE COMP "F3_0" SITE "V1"; + LOCATE COMP "F3_1" SITE "W1"; + LOCATE COMP "F3_2" SITE "W3"; + LOCATE COMP "F3_3" SITE "W4"; + LOCATE COMP "F3_4" SITE "Y1"; + LOCATE COMP "F3_5" SITE "Y2"; + LOCATE COMP "F3_6" SITE "AA1"; + LOCATE COMP "F3_7" SITE "AA2"; + LOCATE COMP "F3_8" SITE "Y9"; + LOCATE COMP "F3_9" SITE "Y8"; + LOCATE COMP "F3_10" SITE "AB2"; + LOCATE COMP "F3_11" SITE "AB3"; + LOCATE COMP "F3_12" SITE "AB4"; + LOCATE COMP "F3_13" SITE "AB5"; + LOCATE COMP "F3_14" SITE "AC1"; + LOCATE COMP "F3_15" SITE "AC2"; + LOCATE COMP "F3_16" SITE "AC7"; + LOCATE COMP "F3_17" SITE "AC6"; + LOCATE COMP "F3_18" SITE "AD2"; +# LOCATE COMP "F3_19" SITE "AD1"; + + LOCATE COMP "F4_0" SITE "R22"; + LOCATE COMP "F4_1" SITE "R23"; + LOCATE COMP "F4_2" SITE "T28"; + LOCATE COMP "F4_3" SITE "T29"; + LOCATE COMP "F4_4" SITE "T22"; + LOCATE COMP "F4_5" SITE "T23"; + LOCATE COMP "F4_6" SITE "R30"; + LOCATE COMP "F4_7" SITE "T30"; + LOCATE COMP "F4_8" SITE "U24"; + LOCATE COMP "F4_9" SITE "U25"; + LOCATE COMP "F4_10" SITE "U26"; + LOCATE COMP "F4_11" SITE "V26"; + LOCATE COMP "F4_12" SITE "V23"; + LOCATE COMP "F4_13" SITE "U23"; + LOCATE COMP "F4_14" SITE "U27"; + LOCATE COMP "F4_15" SITE "U28"; + LOCATE COMP "F4_16" SITE "V25"; + LOCATE COMP "F4_17" SITE "V24"; + LOCATE COMP "F4_18" SITE "W28"; +# LOCATE COMP "F4_19" SITE "W27"; + DEFINE PORT GROUP "F_group" "F*" ; + IOBUF GROUP "F_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN ; + +##################################################################### +# LED +##################################################################### + LOCATE COMP "LED_GBE_OK" SITE "AC30"; + LOCATE COMP "LED_GBE_TX" SITE "AA30"; + LOCATE COMP "LED_GBE_RX" SITE "AB30"; + LOCATE COMP "LED_TRBNET_OK" SITE "AC27"; + LOCATE COMP "LED_TRBNET_RX" SITE "AC28"; + LOCATE COMP "LED_TRBNET_TX" SITE "AC29"; + LOCATE COMP "LED_GREEN" SITE "T26"; + LOCATE COMP "LED_ORANGE" SITE "N30"; + LOCATE COMP "LED_RED" SITE "R29"; + LOCATE COMP "LED_YELLOW" SITE "T27"; + DEFINE PORT GROUP "LED_group" "LED*" ; + IOBUF GROUP "LED_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + + + LOCATE COMP "DIS1_0" SITE "AF10"; + LOCATE COMP "DIS1_1" SITE "AE8"; + LOCATE COMP "DIS1_2" SITE "AE11"; + LOCATE COMP "DIS2_0" SITE "AE13"; + LOCATE COMP "DIS2_1" SITE "AC12"; + LOCATE COMP "DIS2_2" SITE "AG2"; + DEFINE PORT GROUP "DIS_group" "DIS*" ; + IOBUF GROUP "DIS_group" IO_TYPE=LVTTL PULLMODE=DOWN ; + + + +##################################################################### +# Memory JTAG +##################################################################### + LOCATE COMP "MEM_TDO_IN" SITE "E26"; + LOCATE COMP "MEM_TDI_OUT" SITE "D23"; + LOCATE COMP "MEM_TCK_OUT" SITE "D26"; + LOCATE COMP "MEM_TMS_OUT" SITE "E21"; + DEFINE PORT GROUP "MEM_group" "MEM*" ; + IOBUF GROUP "MEM_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + + + +##################################################################### +# RAM +##################################################################### + LOCATE COMP "RAM1_A_0" SITE "J18"; #A_0 + LOCATE COMP "RAM1_A_1" SITE "J19"; #A_1 + LOCATE COMP "RAM1_A_2" SITE "H17"; #AI_1 + LOCATE COMP "RAM1_A_3" SITE "J17"; #AI_2 + LOCATE COMP "RAM1_A_4" SITE "F18"; #AI_3 + LOCATE COMP "RAM1_A_5" SITE "F17"; #AI_4 + LOCATE COMP "RAM1_A_6" SITE "A16"; #AI_5 + LOCATE COMP "RAM1_A_7" SITE "B16"; #AI_6 + LOCATE COMP "RAM1_A_8" SITE "G17"; #AI_7 + LOCATE COMP "RAM1_A_9" SITE "G16"; #AI_8 + LOCATE COMP "RAM1_A_10" SITE "H16"; #AI_9 + LOCATE COMP "RAM1_A_11" SITE "F16"; #AI_10 + LOCATE COMP "RAM1_A_12" SITE "J16"; #AI_11 + LOCATE COMP "RAM1_A_13" SITE "G15"; #AI_12 + LOCATE COMP "RAM1_A_14" SITE "C16"; #AI_13 + LOCATE COMP "RAM1_A_15" SITE "D16"; #AI_14 + LOCATE COMP "RAM1_A_16" SITE "J15"; #AI_15 + LOCATE COMP "RAM1_A_17" SITE "H15"; #AI_16 + LOCATE COMP "RAM1_A_18" SITE "A15"; #AI_17 + LOCATE COMP "RAM1_A_19" SITE "B15"; #AI_18 + + LOCATE COMP "RAM1_ADSCB" SITE "J14"; + LOCATE COMP "RAM1_ADSPB" SITE "F14"; + LOCATE COMP "RAM1_ADVB" SITE "G14"; + LOCATE COMP "RAM1_CEB" SITE "C14"; + LOCATE COMP "RAM1_CLK" SITE "E16"; + LOCATE COMP "RAM1_GWB" SITE "F15"; + LOCATE COMP "RAM1_OEB" SITE "E15"; + + LOCATE COMP "RAM1_DQ_0" SITE "E23"; # RAM1_DQA_1 + LOCATE COMP "RAM1_DQ_1" SITE "G22"; # RAM1_DQA_2 + LOCATE COMP "RAM1_DQ_2" SITE "D22"; # RAM1_DQA_3 + LOCATE COMP "RAM1_DQ_3" SITE "F21"; # RAM1_DQA_4 + LOCATE COMP "RAM1_DQ_4" SITE "G18"; # RAM1_DQA_5 + LOCATE COMP "RAM1_DQ_5" SITE "H18"; # RAM1_DQA_6 + LOCATE COMP "RAM1_DQ_6" SITE "D20"; # RAM1_DQA_7 + LOCATE COMP "RAM1_DQ_7" SITE "D21"; # RAM1_DQA_8 + LOCATE COMP "RAM1_DQ_8" SITE "E20"; # RAM1_DQB_1 + LOCATE COMP "RAM1_DQ_9" SITE "E19"; # RAM1_DQB_2 + LOCATE COMP "RAM1_DQ_10" SITE "D19"; # RAM1_DQB_3 + LOCATE COMP "RAM1_DQ_11" SITE "E18"; # RAM1_DQB_4 + LOCATE COMP "RAM1_DQ_12" SITE "D18"; # RAM1_DQB_5 + LOCATE COMP "RAM1_DQ_13" SITE "C17"; # RAM1_DQB_6 + LOCATE COMP "RAM1_DQ_14" SITE "A17"; # RAM1_DQB_7 + LOCATE COMP "RAM1_DQ_15" SITE "B17"; # RAM1_DQB_8 + LOCATE COMP "RAM1_DQ_16" SITE "C15"; # RAM1_DQPA" + LOCATE COMP "RAM1_DQ_17" SITE "D15"; # RAM1_DQPB" + + + LOCATE COMP "RAM2_A_0" SITE "L29"; #A_0 + LOCATE COMP "RAM2_A_1" SITE "L28"; #A_1 + LOCATE COMP "RAM2_A_2" SITE "L27"; #AI_1 + LOCATE COMP "RAM2_A_3" SITE "H29"; #AI_2 + LOCATE COMP "RAM2_A_4" SITE "G29"; #AI_3 + LOCATE COMP "RAM2_A_5" SITE "L22"; #AI_4 + LOCATE COMP "RAM2_A_6" SITE "M22"; #AI_5 + LOCATE COMP "RAM2_A_7" SITE "F30"; #AI_6 + LOCATE COMP "RAM2_A_8" SITE "F29"; #AI_7 + LOCATE COMP "RAM2_A_9" SITE "E30"; #AI_8 + LOCATE COMP "RAM2_A_10" SITE "E29"; #AI_9 + LOCATE COMP "RAM2_A_11" SITE "L25"; #AI_10 + LOCATE COMP "RAM2_A_12" SITE "L26"; #AI_11 + LOCATE COMP "RAM2_A_13" SITE "H28"; #AI_12 + LOCATE COMP "RAM2_A_14" SITE "J28"; #AI_13 + LOCATE COMP "RAM2_A_15" SITE "G28"; #AI_14 + LOCATE COMP "RAM2_A_16" SITE "G27"; #AI_15 + LOCATE COMP "RAM2_A_17" SITE "L24"; #AI_16 + LOCATE COMP "RAM2_A_18" SITE "L23"; #AI_17 + LOCATE COMP "RAM2_A_19" SITE "D30"; #AI_18 + + LOCATE COMP "RAM2_ADSCB" SITE "G30"; + LOCATE COMP "RAM2_ADSPB" SITE "M25"; + LOCATE COMP "RAM2_ADVB" SITE "H30"; + LOCATE COMP "RAM2_CEB" SITE "M27"; + LOCATE COMP "RAM2_CLK" SITE "N25"; + LOCATE COMP "RAM2_GWB" SITE "N26"; + LOCATE COMP "RAM2_OEB" SITE "M28"; + + LOCATE COMP "RAM2_DQ_0" SITE "M30"; # RAM1_DQA_1 + LOCATE COMP "RAM2_DQ_1" SITE "M29"; # RAM1_DQA_2 + LOCATE COMP "RAM2_DQ_2" SITE "P23"; # RAM1_DQA_3 + LOCATE COMP "RAM2_DQ_3" SITE "P24"; # RAM1_DQA_4 + LOCATE COMP "RAM2_DQ_4" SITE "R26"; # RAM1_DQA_5 + LOCATE COMP "RAM2_DQ_5" SITE "P27"; # RAM1_DQA_6 + LOCATE COMP "RAM2_DQ_6" SITE "P25"; # RAM1_DQA_7 + LOCATE COMP "RAM2_DQ_7" SITE "P26"; # RAM1_DQA_8 + LOCATE COMP "RAM2_DQ_8" SITE "K30"; # RAM1_DQB_1 + LOCATE COMP "RAM2_DQ_9" SITE "K29"; # RAM1_DQB_2 + LOCATE COMP "RAM2_DQ_10" SITE "N22"; # RAM1_DQB_3 + LOCATE COMP "RAM2_DQ_11" SITE "P22"; # RAM1_DQB_4 + LOCATE COMP "RAM2_DQ_12" SITE "J30"; # RAM1_DQB_5 + LOCATE COMP "RAM2_DQ_13" SITE "J29"; # RAM1_DQB_6 + LOCATE COMP "RAM2_DQ_14" SITE "N24"; # RAM1_DQB_7 + LOCATE COMP "RAM2_DQ_15" SITE "N23"; # RAM1_DQB_8 + LOCATE COMP "RAM2_DQ_16" SITE "M26"; # RAM1_DQPA" + LOCATE COMP "RAM2_DQ_17" SITE "L30"; # RAM1_DQPB" + + DEFINE PORT GROUP "ram_group" "RAM*" ; + IOBUF GROUP "ram_group" IO_TYPE=LVCMOS25 PULLMODE=UP ; + +##################################################################### +# Unused Locates +##################################################################### +# LOCATE COMP "JTAG_TCK" SITE "AE2"; +# LOCATE COMP "JTAG_TMS" SITE "AF2"; +# LOCATE COMP "INITN" SITE "AC24"; +# LOCATE COMP "GBE_RXN" SITE "B29"; +# LOCATE COMP "GBE_RXP" SITE "A29"; +# LOCATE COMP "GBE_TXN" SITE "B26"; +# LOCATE COMP "GBE_TXP" SITE "A26"; +# LOCATE COMP "TRBNET_RXN" SITE "AJ29"; +# LOCATE COMP "TRBNET_RXP" SITE "AK29"; +# LOCATE COMP "TRBNET_TXN" SITE "AJ26"; +# LOCATE COMP "TRBNET_TXP" SITE "AK26"; +# LOCATE COMP "S100_1TO5_OUTN" SITE "AJ2"; +# LOCATE COMP "S125_1TO5_INP" SITE "A9"; +# LOCATE COMP "S100_3TO5_INN" SITE "AJ8"; +# LOCATE COMP "S100_1TO5_OUTP" SITE "AK2"; +# LOCATE COMP "S100_3TO5_OUTP" SITE "AK11"; +# LOCATE COMP "S100_4TO5_INN" SITE "AJ9"; +# LOCATE COMP "S100_4TO5_OUTN" SITE "AJ12"; +# LOCATE COMP "S100_3TO5_INP" SITE "AK8"; +# LOCATE COMP "S125_1TO5_OUTN" SITE "B12"; +# LOCATE COMP "S100_1TO5_INN" SITE "AJ5"; +# LOCATE COMP "S125_4TO5_OUTP" SITE "A2"; +# LOCATE COMP "S125_3TO5_OUTN" SITE "B3"; +# LOCATE COMP "S125_3TO5_INP" SITE "A6"; +# LOCATE COMP "S100_1TO5_INP" SITE "AK5"; +# LOCATE COMP "S125_2TO5_INN" SITE "B8"; +# LOCATE COMP "S100_4TO5_INP" SITE "AK9"; +# LOCATE COMP "S100_2TO5_OUTN" SITE "AJ3"; +# LOCATE COMP "S100_2TO5_INN" SITE "AJ6"; +# LOCATE COMP "S125_4TO5_INN" SITE "B5"; +# LOCATE COMP "S125_2TO5_INP" SITE "A8"; +# LOCATE COMP "S125_2TO5_OUTN" SITE "B11"; +# LOCATE COMP "S100_2TO5_OUTP" SITE "AK3"; +# LOCATE COMP "S125_4TO5_INP" SITE "A5"; +# LOCATE COMP "S100_3TO5_OUTN" SITE "AJ11"; +# LOCATE COMP "S100_4TO5_OUTP" SITE "AK12"; +# LOCATE COMP "S125_1TO5_INN" SITE "B9"; +# LOCATE COMP "S100_2TO5_INP" SITE "AK6"; +# LOCATE COMP "S125_4TO5_OUTN" SITE "B2"; +# LOCATE COMP "S125_1TO5_OUTP" SITE "A12"; +# LOCATE COMP "S125_3TO5_OUTP" SITE "A3"; +# LOCATE COMP "S125_2TO5_OUTP" SITE "A11"; +# LOCATE COMP "S125_3TO5_INN" SITE "B6"; +# LOCATE COMP "SPI_CLK" SITE "AG29"; +# LOCATE COMP "SPI_CS" SITE "AA22"; +# LOCATE COMP "SPI_FAST" SITE "AF29"; +# LOCATE COMP "SPI_IN" SITE "AA23"; +# LOCATE COMP "SPI_OUT" SITE "AD30"; +# LOCATE COMP "TDO_F_4" SITE "AE1"; +# LOCATE COMP "TDO_F_5" SITE "AF1"; +# LOCATE COMP "POWER_IN_1" SITE "AG20"; +# LOCATE COMP "POWER_IN_2" SITE "AG21"; +# LOCATE COMP "POWER_IN_3" SITE "AG18"; +# LOCATE COMP "POWER_IN_4" SITE "AJ16"; +# LOCATE COMP "POWER_SCL" SITE "AF21"; +# LOCATE COMP "POWER_SDA" SITE "AG22"; \ No newline at end of file diff --git a/special/spi_databus_memory.vhd b/special/spi_databus_memory.vhd index 2ee9542..1caaae7 100644 --- a/special/spi_databus_memory.vhd +++ b/special/spi_databus_memory.vhd @@ -29,7 +29,10 @@ entity spi_databus_memory is end entity; architecture Behavioral of spi_databus_memory is - + -- Placer Directives + attribute HGROUP : string; + -- for whole architecture + attribute HGROUP of Behavioral : architecture is "SPI_group"; -- Signals type STATES is (SLEEP,RD_RDY,WR_RDY,RD_ACK,WR_ACK,DONE); signal CURRENT_STATE, NEXT_STATE: STATES; -- 2.43.0