From 2f2cdc67c681c8823e22e9412af08e4108a3939b Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 15 May 2014 19:04:24 +0200 Subject: [PATCH] Removed the CompileVersion field in favor of a larger ImplementedFeatures list generic --- trb_net16_endpoint_hades_cts.vhd | 6 ++--- trb_net16_endpoint_hades_full.vhd | 4 ++-- trb_net16_endpoint_sctrl.vhd | 4 ++-- trb_net16_hub_base.vhd | 4 ++-- trb_net16_hub_func.vhd | 8 +++---- trb_net16_hub_streaming_port.vhd | 4 ++-- trb_net16_hub_streaming_port_sctrl.vhd | 4 ++-- trb_net16_hub_streaming_port_sctrl_cts.vhd | 4 ++-- trb_net16_regIO.vhd | 20 ++++++++--------- trb_net_components.vhd | 26 ++++++++++++++++++---- trb_net_std.vhd | 6 +++++ 11 files changed, 57 insertions(+), 33 deletions(-) diff --git a/trb_net16_endpoint_hades_cts.vhd b/trb_net16_endpoint_hades_cts.vhd index b464e95..b7890df 100644 --- a/trb_net16_endpoint_hades_cts.vhd +++ b/trb_net16_endpoint_hades_cts.vhd @@ -34,7 +34,7 @@ entity trb_net16_endpoint_hades_cts is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(15 downto 0) := x"0001"; + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; REGIO_USE_1WIRE_INTERFACE: integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -640,7 +640,7 @@ begin INIT_BOARD_INFO => REGIO_INIT_BOARD_INFO, INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID, COMPILE_TIME => REGIO_COMPILE_TIME, - COMPILE_VERSION => REGIO_COMPILE_VERSION, + INCLUDED_FEATURES => REGIO_INCLUDED_FEATURES, HARDWARE_VERSION => REGIO_HARDWARE_VERSION, CLOCK_FREQ => CLOCK_FREQUENCY ) @@ -781,4 +781,4 @@ begin STAT_DEBUG_1 <= (others => '0'); -end architecture; \ No newline at end of file +end architecture; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index ba5d9c0..1576456 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -43,7 +43,7 @@ entity trb_net16_endpoint_hades_full is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -578,7 +578,7 @@ begin INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID, INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID, COMPILE_TIME => REGIO_COMPILE_TIME, - COMPILE_VERSION => REGIO_COMPILE_VERSION, + INCLUDED_FEATURES => REGIO_INCLUDED_FEATURES, HARDWARE_VERSION => REGIO_HARDWARE_VERSION, CLOCK_FREQ => CLOCK_FREQUENCY ) diff --git a/trb_net16_endpoint_sctrl.vhd b/trb_net16_endpoint_sctrl.vhd index cf987c5..56a2a18 100644 --- a/trb_net16_endpoint_sctrl.vhd +++ b/trb_net16_endpoint_sctrl.vhd @@ -34,7 +34,7 @@ entity trb_net16_endpoint_sctrl is REGIO_INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -569,7 +569,7 @@ begin INIT_UNIQUE_ID => REGIO_INIT_UNIQUE_ID, INIT_ENDPOINT_ID => REGIO_INIT_ENDPOINT_ID, COMPILE_TIME => REGIO_COMPILE_TIME, - COMPILE_VERSION => REGIO_COMPILE_VERSION, + INCLUDED_FEATURES => REGIO_INCLUDED_FEATURES, HARDWARE_VERSION => REGIO_HARDWARE_VERSION, CLOCK_FREQ => CLOCK_FREQUENCY ) diff --git a/trb_net16_hub_base.vhd b/trb_net16_hub_base.vhd index df6aa64..bfb7f47 100644 --- a/trb_net16_hub_base.vhd +++ b/trb_net16_hub_base.vhd @@ -28,7 +28,7 @@ entity trb_net16_hub_base is x"00000000_00000000_00007077_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; @@ -1052,7 +1052,7 @@ end generate; INIT_UNIQUE_ID => INIT_UNIQUE_ID, INIT_ENDPOINT_ID => INIT_ENDPOINT_ID, COMPILE_TIME => COMPILE_TIME, - COMPILE_VERSION => COMPILE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, HARDWARE_VERSION => HARDWARE_VERSION, CLOCK_FREQ => CLOCK_FREQUENCY ) diff --git a/trb_net16_hub_func.vhd b/trb_net16_hub_func.vhd index 37cf57b..12ee9a8 100644 --- a/trb_net16_hub_func.vhd +++ b/trb_net16_hub_func.vhd @@ -101,7 +101,7 @@ package trb_net16_hub_func is x"00000000_00000000_000050FF_00000000" & x"FFFFFFFF_FFFFFFFF_FFFFFFFF_FFFFFFFF"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; @@ -206,7 +206,7 @@ component trb_net16_hub_streaming_port is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -602,7 +602,7 @@ component trb_net16_hub_streaming_port_sctrl is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -712,7 +712,7 @@ component trb_net16_hub_streaming_port_sctrl_cts is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F3C0"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"9000CE00"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0005"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; diff --git a/trb_net16_hub_streaming_port.vhd b/trb_net16_hub_streaming_port.vhd index 073aab0..e76593b 100644 --- a/trb_net16_hub_streaming_port.vhd +++ b/trb_net16_hub_streaming_port.vhd @@ -22,7 +22,7 @@ entity trb_net16_hub_streaming_port is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -230,7 +230,7 @@ begin INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, COMPILE_TIME => COMPILE_TIME, - COMPILE_VERSION => COMPILE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, HARDWARE_VERSION => HARDWARE_VERSION, HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, CLOCK_FREQUENCY => CLOCK_FREQUENCY, diff --git a/trb_net16_hub_streaming_port_sctrl.vhd b/trb_net16_hub_streaming_port_sctrl.vhd index 2b27288..3d77640 100644 --- a/trb_net16_hub_streaming_port_sctrl.vhd +++ b/trb_net16_hub_streaming_port_sctrl.vhd @@ -35,7 +35,7 @@ entity trb_net16_hub_streaming_port_sctrl is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F004"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -264,7 +264,7 @@ begin INIT_ADDRESS => INIT_ADDRESS, INIT_UNIQUE_ID => INIT_UNIQUE_ID, COMPILE_TIME => COMPILE_TIME, - COMPILE_VERSION => COMPILE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, HARDWARE_VERSION => HARDWARE_VERSION, HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, CLOCK_FREQUENCY => CLOCK_FREQUENCY, diff --git a/trb_net16_hub_streaming_port_sctrl_cts.vhd b/trb_net16_hub_streaming_port_sctrl_cts.vhd index 3620663..4b537ff 100644 --- a/trb_net16_hub_streaming_port_sctrl_cts.vhd +++ b/trb_net16_hub_streaming_port_sctrl_cts.vhd @@ -51,7 +51,7 @@ entity trb_net16_hub_streaming_port_sctrl_cts is INIT_ADDRESS : std_logic_vector(15 downto 0) := x"F3C0"; INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := (others => '0'); COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"9000CE00"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0005"; BROADCAST_BITMASK : std_logic_vector(7 downto 0) := x"7E"; @@ -426,7 +426,7 @@ begin INIT_UNIQUE_ID => INIT_UNIQUE_ID, INIT_CTRL_REGS => INIT_CTRL_REGS, COMPILE_TIME => COMPILE_TIME, - COMPILE_VERSION => COMPILE_VERSION, + INCLUDED_FEATURES => INCLUDED_FEATURES, HARDWARE_VERSION => HARDWARE_VERSION, HUB_CTRL_BROADCAST_BITMASK => BROADCAST_BITMASK, CLOCK_FREQUENCY => CLOCK_FREQUENCY, diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index 779375b..0777d40 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -20,13 +20,13 @@ entity trb_net16_regIO is USED_CTRL_REGS : std_logic_vector(2**(4)-1 downto 0) := (others => '1'); --set to 0 for each unused bit in a register USED_CTRL_BITMASK : std_logic_vector(2**(4)*32-1 downto 0) := (others => '1'); - USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port - INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; - INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; - INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; - INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; + USE_DAT_PORT : integer range 0 to 1 := c_YES; --internal data port + INIT_ADDRESS : std_logic_vector(15 downto 0) := x"FFFF"; + INIT_UNIQUE_ID : std_logic_vector(63 downto 0) := x"1000_2000_3654_4876"; + INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; + INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; --not used any more! - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); @@ -931,12 +931,12 @@ begin generic map( INIT0 => COMPILE_TIME_LIB(15 downto 0), INIT1 => COMPILE_TIME_LIB(31 downto 16), - INIT2 => COMPILE_VERSION(15 downto 0), - INIT3 => COMPILE_VERSION(31 downto 16), + INIT2 => INCLUDED_FEATURES(15 downto 0), + INIT3 => INCLUDED_FEATURES(31 downto 16), INIT4 => HARDWARE_VERSION(15 downto 0), INIT5 => HARDWARE_VERSION(31 downto 16), - INIT6 => COMPILE_VERSION(47 downto 32), - INIT7 => COMPILE_VERSION(63 downto 48) + INIT6 => INCLUDED_FEATURES(47 downto 32), + INIT7 => INCLUDED_FEATURES(63 downto 48) ) port map( CLK => CLK, diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 60d623a..b9089c9 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -506,6 +506,24 @@ package trb_net_components is DEBUG_OUT : out std_logic_vector (31 downto 0) ); end component; + + +component bus_register_handler is + generic ( + BUS_LENGTH : integer range 0 to 64 := 2); + port ( + RESET : in std_logic; + CLK : in std_logic; +-- + DATA_IN : in std_logic_vector_array_32(0 to BUS_LENGTH); + READ_EN_IN : in std_logic; + WRITE_EN_IN : in std_logic; + ADDR_IN : in std_logic_vector(6 downto 0); + DATA_OUT : out std_logic_vector(31 downto 0); + DATAREADY_OUT : out std_logic; + UNKNOWN_ADDR_OUT : out std_logic + ); +end component; component trb_net_CRC is port( @@ -615,7 +633,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -746,7 +764,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -886,7 +904,7 @@ package trb_net_components is REGIO_INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"0000_0000"; REGIO_INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; REGIO_COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - REGIO_COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + REGIO_INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); REGIO_HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"50000000"; REGIO_USE_1WIRE_INTERFACE : integer := c_YES; --c_YES,c_NO,c_MONITOR REGIO_USE_VAR_ENDPOINT_ID : integer range c_NO to c_YES := c_NO; @@ -2554,7 +2572,7 @@ package trb_net_components is INIT_BOARD_INFO : std_logic_vector(31 downto 0) := x"1111_2222"; INIT_ENDPOINT_ID : std_logic_vector(15 downto 0) := x"0001"; COMPILE_TIME : std_logic_vector(31 downto 0) := x"00000000"; - COMPILE_VERSION : std_logic_vector(63 downto 0) := (others => '0'); + INCLUDED_FEATURES : std_logic_vector(63 downto 0) := (others => '0'); HARDWARE_VERSION : std_logic_vector(31 downto 0) := x"12345678"; CLOCK_FREQ : integer range 1 to 200 := 100 --MHz ); diff --git a/trb_net_std.vhd b/trb_net_std.vhd index 58921a9..df73da5 100644 --- a/trb_net_std.vhd +++ b/trb_net_std.vhd @@ -149,6 +149,12 @@ package trb_net_std is --constant VERSION_NUMBER_TIME : std_logic_vector(31 downto 0) := conv_std_logic_vector(1234567890,32); + type std_logic_vector_array_36 is array (integer range <>) of std_logic_vector(35 downto 0); + type std_logic_vector_array_32 is array (integer range <>) of std_logic_vector(31 downto 0); + type std_logic_vector_array_24 is array (integer range <>) of std_logic_vector(23 downto 0); + type std_logic_vector_array_11 is array (integer range <>) of std_logic_vector(10 downto 0); + type std_logic_vector_array_8 is array (integer range <>) of std_logic_vector(7 downto 0); + --function declarations -- 2.43.0