From 2f851285b98d903e7dd06f237959273fbd0827eb Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Sat, 20 Jan 2024 10:58:23 +0100 Subject: [PATCH] changed almost nothing, but now deserializer works.. --- vldb/code/gbt_core.vhd | 64 +++++++++++++++++++++--------------- vldb/par.p2t | 2 +- vldb/testbench/testbench.tcl | 19 ++++++----- 3 files changed, 50 insertions(+), 35 deletions(-) diff --git a/vldb/code/gbt_core.vhd b/vldb/code/gbt_core.vhd index 8943b65..85f268a 100644 --- a/vldb/code/gbt_core.vhd +++ b/vldb/code/gbt_core.vhd @@ -57,6 +57,8 @@ architecture arch of gbt_core is signal gbtsc_rx_error_o : std_logic_vector(7 downto 0); --! Reply: error field (According to the SCA manual) signal gbtsc_rx_data_o : std_logic_vector(31 downto 0); --! Reply: data field (According to the SCA manual) signal sync_reg : std_logic_vector(79 downto 0); -- register for syncing + signal sync_reg_done_100 : std_logic := '0'; + signal sync_reg_done_40 : std_logic := '0'; -- EC line signal hdlc_from_gbtsc : std_logic_vector(1 downto 0) := "11"; --! (TX) Array of bits to be mapped to the TX GBT-Frame @@ -151,11 +153,13 @@ begin counter(0) <= counter(0) xor gbtsc_start_reset_cmd_i; counter(2) <= counter(2) xor gbtsc_start_connect_cmd_i; counter(4) <= counter(4) xor gbtsc_start_command_i; + counter(6) <= counter(6) xor sync_reg_done_40; counter(7) <= counter(7) xor gbtsc_rx_received_o; else counter(0) <= '0'; counter(2) <= '0'; counter(4) <= '0'; + counter(6) <= '0'; counter(7) <= '0'; end if; end process; @@ -168,9 +172,6 @@ begin counter(5) <= counter(5) xor gbtsc_go; end process; - -- 1 means off for LED - counter(6) <= '1'; - TESTOUT <= std_logic_vector(counter(7 downto 0)); @@ -178,7 +179,9 @@ begin begin wait until rising_edge(CLK); if gbtsc_rx_received_o = '1' then - sync_reg <= gbtsc_rx_address_o & gbtsc_rx_transID_o & gbtsc_rx_channel_o & gbtsc_rx_len_o & gbtsc_rx_data_o & gbtsc_rx_control_o & gbtsc_rx_error_o; + sync_reg <= gbtsc_rx_address_o & gbtsc_rx_control_o & gbtsc_rx_transID_o & gbtsc_rx_channel_o & gbtsc_rx_error_o & gbtsc_rx_len_o & gbtsc_rx_data_o; + elsif gbtsc_rx_received_o = '0' and sync_reg_done_40 = '1' then + sync_reg <= (others => '0'); end if; end process; @@ -187,7 +190,6 @@ begin hdlcser_proc: process(CLK_80) begin if rising_edge(CLK_80) then - -- if rising_edge(CLK) or CLK = '1' then if CLK = '1' then ELINK_TX <= hdlc_from_gbtsc(1); else @@ -220,23 +222,23 @@ begin gbtsc_reset_go <= '0'; gbtsc_connect_go <= '0'; gbtsc_go <= '0'; + sync_reg_done_100 <= '0'; if BUS_RX.write = '1' then BUS_TX.ack <= '1'; if BUS_RX.addr(3 downto 0) = x"0" then - gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); - -- gbtsc_sca_enable_i <= BUS_RX.data(8); - gbtsc_reset_go <= BUS_RX.data(9); - gbtsc_connect_go <= BUS_RX.data(10); - gbtsc_go <= BUS_RX.data(11); + gbtsc_tx_address_i <= BUS_RX.data(7 downto 0); -- hdlc Address elsif BUS_RX.addr(3 downto 0) = x"1" then - gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); - gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); - -- gbtsc_tx_len_i <= BUS_RX.data(23 downto 16); - gbtsc_tx_command_i <= BUS_RX.data(31 downto 24); + gbtsc_reset_go <= BUS_RX.data(0); -- gbtsca RESET + gbtsc_connect_go <= BUS_RX.data(1); -- gbtsca CONNECT + gbtsc_go <= BUS_RX.data(2); -- gbtsca Start Command elsif BUS_RX.addr(3 downto 0) = x"2" then - gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); + gbtsc_tx_transID_i <= BUS_RX.data(7 downto 0); -- gbtsca TransID + gbtsc_tx_channel_i <= BUS_RX.data(15 downto 8); -- gbtsca Channel + gbtsc_tx_command_i <= BUS_RX.data(23 downto 16); -- gbtsca Command + elsif BUS_RX.addr(3 downto 0) = x"3" then + gbtsc_tx_data_i <= BUS_RX.data(31 downto 0); -- gbtsca Data else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; @@ -245,17 +247,17 @@ begin elsif BUS_RX.read = '1' then BUS_TX.ack <= '1'; - if BUS_RX.addr(3 downto 0) = x"0" then - BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); - elsif BUS_RX.addr(3 downto 0) = x"1" then - BUS_TX.data( 7 downto 0 ) <= sync_reg(71 downto 64); - BUS_TX.data(15 downto 8 ) <= sync_reg(63 downto 56); - BUS_TX.data(23 downto 16) <= sync_reg(55 downto 48); - elsif BUS_RX.addr(3 downto 0) = x"2" then - BUS_TX.data(31 downto 0) <= sync_reg(47 downto 16); - elsif BUS_RX.addr(3 downto 0) = x"3" then - BUS_TX.data(7 downto 0) <= sync_reg(15 downto 8); - BUS_TX.data(15 downto 8) <= sync_reg(7 downto 0); + if BUS_RX.addr(3 downto 0) = x"a" then + BUS_TX.data(7 downto 0) <= sync_reg(79 downto 72); -- hdlc Address + BUS_TX.data(15 downto 8) <= sync_reg(71 downto 64); -- hdlc Control + elsif BUS_RX.addr(3 downto 0) = x"b" then + BUS_TX.data( 7 downto 0 ) <= sync_reg(63 downto 56); -- gbtsca TransID + BUS_TX.data(15 downto 8 ) <= sync_reg(55 downto 48); -- gbtsca Channel + BUS_TX.data(23 downto 16) <= sync_reg(47 downto 40); -- gbtsca Error + BUS_TX.data(31 downto 24) <= sync_reg(39 downto 32); -- gbtsca Length + elsif BUS_RX.addr(3 downto 0) = x"c" then + BUS_TX.data(31 downto 0) <= sync_reg(31 downto 0); -- gbtsca Data + sync_reg_done_100 <= '1'; else BUS_TX.ack <= '0'; BUS_TX.unknown <= '1'; @@ -295,5 +297,15 @@ begin PULSE_B_OUT => gbtsc_start_connect_cmd_i ); + THE_SYNC_REG_SYNC : entity work.pulse_sync + port map( + CLK_A_IN => CLK_SYS, + RESET_A_IN => RESET, + PULSE_A_IN => sync_reg_done_100, + CLK_B_IN => CLK, + RESET_B_IN => RESET, + PULSE_B_OUT => sync_reg_done_40 + ); + end architecture; diff --git a/vldb/par.p2t b/vldb/par.p2t index bb6004c..90538cf 100644 --- a/vldb/par.p2t +++ b/vldb/par.p2t @@ -4,7 +4,7 @@ #-m nodelist.txt # Controlled by the compile.pl script. #-n 1 # Controlled by the compile.pl script. -s 10 --t 49 +-t 48 -c 2 -e 2 -i 10 diff --git a/vldb/testbench/testbench.tcl b/vldb/testbench/testbench.tcl index 92d1364..5dce9b5 100644 --- a/vldb/testbench/testbench.tcl +++ b/vldb/testbench/testbench.tcl @@ -189,28 +189,31 @@ proc send_command_bus {} { force -freeze sim:/tb_gbt_core/bus_rx.write 0 0 force -freeze sim:/tb_gbt_core/bus_rx.read 0 0 - #set channel, command, etc. - set addr 0x0001 - set data 0x02000001 + set addr 0x0000 + set data 0x00 force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 500 ns force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 500 ns force -freeze sim:/tb_gbt_core/bus_rx.write 1 500 ns - #set data set addr 0x0002 - set data 0x0000ff00 + set data 0x001301 force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 510 ns force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 510 ns force -freeze sim:/tb_gbt_core/bus_rx.write 1 510 ns - #start - set addr 0x0000 + set addr 0x0003 set data 0x00000800 force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 520 ns force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 520 ns force -freeze sim:/tb_gbt_core/bus_rx.write 1 520 ns - force -freeze sim:/tb_gbt_core/bus_rx.write 0 530 ns + set addr 0x0001 + set data 0x4 + force -freeze sim:/tb_gbt_core/bus_rx.addr 8'h$addr 530 ns + force -freeze sim:/tb_gbt_core/bus_rx.data 8'h$data 530 ns + force -freeze sim:/tb_gbt_core/bus_rx.write 1 530 ns + + force -freeze sim:/tb_gbt_core/bus_rx.write 0 540 ns # run -all run 5000ns -- 2.43.0