From 304a4a17095a08743313e7aa54a1ee7e775cd142 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 15 Dec 2021 11:14:57 +0100 Subject: [PATCH] before removing rx_lsm --- media_interfaces/sync/med_sync_control_RS.vhd | 26 ++-- media_interfaces/sync/rx_control_RS.vhd | 136 ++++++++++++++---- media_interfaces/sync/rx_lsm_RS.vhd | 38 ++--- media_interfaces/sync/tx_control_RS.vhd | 12 +- 4 files changed, 132 insertions(+), 80 deletions(-) diff --git a/media_interfaces/sync/med_sync_control_RS.vhd b/media_interfaces/sync/med_sync_control_RS.vhd index af55612..6d76f83 100644 --- a/media_interfaces/sync/med_sync_control_RS.vhd +++ b/media_interfaces/sync/med_sync_control_RS.vhd @@ -93,6 +93,7 @@ architecture med_sync_control_arch of med_sync_control_RS is signal is_wap_zero_i : std_logic; signal debug_tx_control_i : std_logic_vector(31 downto 0); + signal debug_rx_control_i : std_logic_vector(31 downto 0); signal rx_lsm_state : std_logic_vector(3 downto 0); signal link_rx_ready_qsys : std_logic; @@ -206,14 +207,15 @@ begin RX_RST_WORD_OUT => RX_RST_WORD_OUT, -- LINK_RX_READY_IN => link_rx_ready_i, - LINK_TX_READY_IN => LINK_TX_READY_IN, LINK_HALF_DONE_IN => link_half_done_i, LINK_FULL_DONE_IN => link_full_done_i, -- - DEBUG_OUT => DEBUG_RX_CONTROL, + DEBUG_OUT => debug_rx_control_i, STAT_REG_OUT => STAT_RX_CONTROL ); + DEBUG_RX_CONTROL <= debug_rx_control_i; + THE_RX_LSM: rx_lsm_RS port map( LINK_RX_READY_IN => link_rx_ready_i, @@ -336,20 +338,14 @@ begin ); -- TEST_LINE signals - DEBUG_OUT(3 downto 0) <= rx_fsm_state; - DEBUG_OUT(4) <= RX_LOS_IN; - DEBUG_OUT(5) <= RX_CDR_LOL_IN; - DEBUG_OUT(6) <= TX_PLL_LOL_IN; - DEBUG_OUT(7) <= LINK_TX_READY_IN; - DEBUG_OUT(8) <= link_rx_ready_i; - DEBUG_OUT(9) <= is_wap_zero_i; - DEBUG_OUT(10) <= link_half_done_i; + DEBUG_OUT(31 downto 12) <= (others => '0'); DEBUG_OUT(11) <= link_full_done_i; - DEBUG_OUT(15 downto 12) <= debug_tx_control_i(3 downto 0); - DEBUG_OUT(19 downto 16) <= rx_lsm_state; - DEBUG_OUT(20) <= word_sync_rx_i; - DEBUG_OUT(21) <= word_sync_tx_i; - DEBUG_OUT(31 downto 22) <= (others => '0'); + DEBUG_OUT(10) <= link_half_done_i; + DEBUG_OUT(9) <= '0'; + DEBUG_OUT(8) <= link_rx_ready_qsys; + DEBUG_OUT(7) <= link_tx_ready_qsys; + DEBUG_OUT(6 downto 2) <= (others => '0'); + DEBUG_OUT(1 downto 0) <= debug_rx_control_i(1 downto 0); -- DEBUG_OUT <= (others => '0'); -- Some remarks on the SerDes issue: diff --git a/media_interfaces/sync/rx_control_RS.vhd b/media_interfaces/sync/rx_control_RS.vhd index 82aa343..d89be82 100644 --- a/media_interfaces/sync/rx_control_RS.vhd +++ b/media_interfaces/sync/rx_control_RS.vhd @@ -29,8 +29,7 @@ entity rx_control_RS is RX_RST_OUT : out std_logic; RX_RST_WORD_OUT : out std_logic_vector(7 downto 0); -- link status signals - LINK_RX_READY_IN : in std_logic; - LINK_TX_READY_IN : in std_logic; -- unused + LINK_RX_READY_IN : in std_logic; -- used for synchronous reset LINK_HALF_DONE_IN : in std_logic; -- unused LINK_FULL_DONE_IN : in std_logic; -- debug @@ -41,7 +40,8 @@ end entity; architecture rx_control_arch of rx_control_RS is - type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST); + type rx_state_t is (SLEEP, WAIT_1, FIRST, GET_DATA, GET_IDLE, GET_DLM, GET_RST, + GET_UNKNOWN); signal rx_state : rx_state_t; signal rx_state_bits : std_logic_vector(3 downto 0); @@ -76,10 +76,25 @@ architecture rx_control_arch of rx_control_RS is signal link_full_done_qrx : std_logic; signal link_full_done_qsys : std_logic; + signal ce_idle0_ctr : std_logic; + signal rst_idle0_ctr : std_logic; + signal ctr_idle0 : unsigned(4 downto 0); + signal idle0_detected : std_logic; + signal ce_idle1_ctr : std_logic; + signal rst_idle1_ctr : std_logic; + signal ctr_idle1 : unsigned(4 downto 0); + signal idle1_detected : std_logic; + signal rst_link_state : std_logic; + -- attribute syn_keep : boolean; -- attribute syn_preserve : boolean; --- attribute syn_keep of sync_k_i : signal is true; --- attribute syn_preserve of sync_k_i : signal is true; +-- attribute syn_noprune : boolean; +-- attribute syn_keep of idle0_detected : signal is true; +-- attribute syn_preserve of idle0_detected : signal is true; +-- attribute syn_noprune of idle0_detected : signal is true; +-- attribute syn_keep of idle1_detected : signal is true; +-- attribute syn_preserve of idle1_detected : signal is true; +-- attribute syn_noprune of idle1_detected : signal is true; begin @@ -168,18 +183,28 @@ begin ct_fifo_write <= '0'; rx_dlm_i <= '0'; rx_rst_i <= '0'; - sync_k_i <= '0'; + sync_k_i <= '0'; + ce_idle0_ctr <= '0'; + ce_idle1_ctr <= '0'; + rst_idle0_ctr <= '0'; + rst_idle1_ctr <= '0'; + rst_link_state <= '0'; case rx_state is when SLEEP => + -- we wait for a known IDLE komma rx_state_bits <= x"1"; rx_data(7 downto 0) <= reg_rx_data_in; + rst_idle0_ctr <= '1'; + rst_idle1_ctr <= '1'; + rst_link_state <= '1'; if( (reg_rx_k_in = '1') and (reg_rx_data_in = K_IDLE) ) then rx_state <= WAIT_1; sync_k_i <= '1'; end if; when WAIT_1 => + -- and skip the data byte rx_state <= FIRST; when FIRST => @@ -194,39 +219,55 @@ begin rx_state <= GET_DLM; when K_RST => rx_state <= GET_RST; - when others => null; + when others => + rx_state <= GET_UNKNOWN; end case; else rx_state <= GET_DATA; end if; - when GET_IDLE => + when GET_UNKNOWN => rx_state_bits <= x"3"; rx_state <= FIRST; + + when GET_IDLE => + rx_state_bits <= x"4"; + rx_state <= FIRST; next_sop <= '1'; + case reg_rx_data_in is + when D_IDLE0 => + -- first link establishment phase + ce_idle0_ctr <= '1'; + rst_idle1_ctr <= '1'; + when D_IDLE1 => + -- second link establishment phase + ce_idle1_ctr <= '1'; + rst_idle0_ctr <= '1'; + when others => + -- all other cases + rst_idle0_ctr <= '1'; + rst_idle1_ctr <= '1'; + end case; when GET_DATA => - rx_state_bits <= x"4"; - -- rx_state <= FIRST - if reg_rx_k_in = '0' then + rx_state_bits <= x"5"; + rx_state <= FIRST; + if reg_rx_k_in = '0' then next_sop <= '0'; rx_data(15 downto 8)<= reg_rx_data_in; rx_data(16) <= next_sop; rx_data(17) <= '0'; ct_fifo_write <= '1'; - rx_state <= FIRST; - else -- not needed? - rx_state <= FIRST; -- not needed? end if; when GET_DLM => - rx_state_bits <= x"5"; + rx_state_bits <= x"6"; rx_dlm_i <= '1'; rx_dlm_word_i <= reg_rx_data_in; rx_state <= FIRST; when GET_RST => - rx_state_bits <= x"6"; + rx_state_bits <= x"7"; rx_rst_i <= '1'; rx_rst_word_i <= reg_rx_data_in; rx_state <= FIRST; @@ -244,6 +285,52 @@ begin reg_rx_data_in <= RX_DATA_IN when rising_edge(CLK_RXI); reg_rx_k_in <= RX_K_IN when rising_edge(CLK_RXI); +-- Counter for link establishment + THE_CTR_IDLE0_PROC: process( CLK_RXI ) + begin + if( rising_edge(CLK_RXI) ) then + if ( rst_idle0_ctr = '1' ) then + ctr_idle0 <= (others => '0'); + elsif( ce_idle0_ctr = '1' ) then + ctr_idle0 <= ctr_idle0 + 1 ; + end if; + end if; + end process THE_CTR_IDLE0_PROC; + + THE_CTR_IDLE1_PROC: process( CLK_RXI ) + begin + if( rising_edge(CLK_RXI) ) then + if ( rst_idle1_ctr = '1' ) then + ctr_idle1 <= (others => '0'); + elsif( ce_idle1_ctr = '1' ) then + ctr_idle1 <= ctr_idle1 + 1 ; + end if; + end if; + end process THE_CTR_IDLE1_PROC; + +-- IDLE detection for link establishment + THE_IDLE0_DETECTED_PROC: process( CLK_RXI ) + begin + if( rising_edge(CLK_RXI) ) then + if ( rst_link_state = '1' ) then + idle0_detected <= '0'; + elsif ( (ctr_idle0(ctr_idle0'left) = '1') and (ce_idle0_ctr = '1') ) then + idle0_detected <= '1'; + end if; + end if; + end process THE_IDLE0_DETECTED_PROC; + + THE_IDLE1_DETECTED_PROC: process( CLK_RXI ) + begin + if( rising_edge(CLK_RXI) ) then + if ( rst_link_state = '1' ) then + idle1_detected <= '0'; + elsif ( (ctr_idle1(ctr_idle1'left) = '1') and (ce_idle1_ctr = '1') ) then + idle1_detected <= '1'; + end if; + end if; + end process THE_IDLE1_DETECTED_PROC; + ---------------------------------------------------------------------- -- Signals out ---------------------------------------------------------------------- @@ -267,19 +354,8 @@ begin STAT_REG_OUT(17) <= '0'; STAT_REG_OUT(31 downto 18) <= (others => '0'); - DEBUG_OUT(3 downto 0) <= rx_state_bits; - DEBUG_OUT(4) <= '0'; - DEBUG_OUT(5) <= ct_fifo_afull; - DEBUG_OUT(6) <= ct_fifo_empty; - DEBUG_OUT(7) <= ct_fifo_write; - DEBUG_OUT(15 downto 8) <= rx_data(7 downto 0); - DEBUG_OUT(16) <= reg_rx_k_in; - DEBUG_OUT(17) <= '0'; - DEBUG_OUT(18) <= '0'; - DEBUG_OUT(19) <= '1' when rx_state_bits = x"f" else '0'; - --DEBUG_OUT(16) <= rx_data(16); - DEBUG_OUT(31 downto 20) <= (others => '0'); - -- DEBUG_OUT(23 downto 16) <= rx_data(7 downto 0); - -- DEBUG_OUT(31 downto 24) <= ct_fifo_data_out(7 downto 0); + DEBUG_OUT(0) <= idle0_detected when rising_edge(CLK_RXI); + DEBUG_OUT(1) <= idle1_detected when rising_edge(CLK_RXI); + DEBUG_OUT(31 downto 2) <= (others => '0'); end architecture; diff --git a/media_interfaces/sync/rx_lsm_RS.vhd b/media_interfaces/sync/rx_lsm_RS.vhd index 85c4757..d9ab08c 100644 --- a/media_interfaces/sync/rx_lsm_RS.vhd +++ b/media_interfaces/sync/rx_lsm_RS.vhd @@ -19,7 +19,7 @@ end entity; architecture rx_lsm_arch of rx_lsm_RS is - type statetype is ( IDLE, K1F, D1F, K2F, D2FT, D2FS ); + type statetype is ( IDLE, KF, DFT, DFS ); signal CURRENT_STATE : statetype; -- current state of lsm signal NEXT_STATE : statetype; -- next state of lsm @@ -127,51 +127,35 @@ begin reset_ctr_t <= '1'; reset_ctr_s <= '1'; if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then - NEXT_STATE <= K1F; + NEXT_STATE <= KF; else NEXT_STATE <= IDLE; end if; - when K1F => + when KF => STATE_OUT <= x"1"; - if( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE1) ) then - NEXT_STATE <= D1F; - else - NEXT_STATE <= IDLE; - end if; - - when D1F => - STATE_OUT <= x"2"; - if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then - NEXT_STATE <= K2F; - else - NEXT_STATE <= IDLE; - end if; - - when K2F => - STATE_OUT <= x"3"; if ( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE1) ) then - NEXT_STATE <= D2FS; + NEXT_STATE <= DFS; ce_ctr_s <= '1'; elsif( (RX_K_IN = '0') and (RX_DATA_IN = D_IDLE0) ) then - NEXT_STATE <= D2FT; + NEXT_STATE <= DFT; ce_ctr_t <= '1'; else NEXT_STATE <= IDLE; end if; - when D2FT => - STATE_OUT <= x"4"; + when DFT => + STATE_OUT <= x"2"; if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then - NEXT_STATE <= K1F; + NEXT_STATE <= KF; else NEXT_STATE <= IDLE; end if; - when D2FS => - STATE_OUT <= x"5"; + when DFS => + STATE_OUT <= x"3"; if( (RX_K_IN = '1') and (RX_DATA_IN = K_IDLE) ) then - NEXT_STATE <= K1F; + NEXT_STATE <= KF; else NEXT_STATE <= IDLE; end if; diff --git a/media_interfaces/sync/tx_control_RS.vhd b/media_interfaces/sync/tx_control_RS.vhd index 607d809..e20c766 100644 --- a/media_interfaces/sync/tx_control_RS.vhd +++ b/media_interfaces/sync/tx_control_RS.vhd @@ -88,7 +88,6 @@ architecture arch of tx_control_RS is signal save_eop : std_logic; signal load_sop : std_logic; signal load_eop : std_logic; - signal toggle_idle : std_logic; signal send_steady_idle_int : std_logic; signal word_sync_i : std_logic; @@ -260,26 +259,25 @@ begin -- TX control state machine ---------------------------------------------------------------------- - THE_DATA_CONTROL_FSM : process(CLK_TXI, link_tx_ready_qtx, RESET) + THE_DATA_CONTROL_FSM : process(CLK_TXI, RESET) begin if( RESET = '1' ) then current_state <= IDLE; TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; word_sync_i <= '0'; - toggle_idle <= '1'; else if( rising_edge(CLK_TXI) ) then TX_K_OUT <= '0'; word_sync_i <= '0'; debug_sending_dlm <= '0'; debug_sending_rst <= '0'; + case current_state is when IDLE => TX_K_OUT <= '1'; TX_DATA_OUT <= K_NULL; word_sync_i <= '0'; - toggle_idle <= '1'; if( link_tx_ready_qtx = '1' ) then current_state <= SEND_IDLE_L; else @@ -297,12 +295,10 @@ begin when SEND_IDLE_H => word_sync_i <= '1'; - if( (send_steady_idle_int = '1') or (toggle_idle = '1') ) then + if( send_steady_idle_int = '1' ) then TX_DATA_OUT <= D_IDLE1; - toggle_idle <= send_steady_idle_int; else TX_DATA_OUT <= D_IDLE0; - toggle_idle <= '1'; end if; when SEND_DATA_L => @@ -429,7 +425,7 @@ send_dlm_word_i <= SEND_DLM_WORD_IN when rising_edge(CLK_TXI); DEBUG_OUT(29) <= debug_sending_rst when rising_edge(CLK_TXI); DEBUG_OUT(28 downto 6) <= (others => '0'); DEBUG_OUT(5) <= send_steady_idle_int when rising_edge(CLK_TXI); - DEBUG_OUT(4) <= toggle_idle when rising_edge(CLK_TXI); + DEBUG_OUT(4) <= '0'; --toggle_idle when rising_edge(CLK_TXI); DEBUG_OUT(3 downto 0) <= state_bits when rising_edge(CLK_TXI); process(CLK_SYS) -- 2.43.0