From 306ca5e23169be687ca5431a91af879c5c1c3779 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 8 Jul 2009 10:18:55 +0000 Subject: [PATCH] *** empty log message *** --- pinout/TRB_HUB2_FPGA1.lpf | 11 +- pinout/TRB_HUB2_FPGA2.lpf | 49 +++----- trb_net16_api_ipu_streaming.vhd | 215 ++++++++++++++++++++++++++++++-- trb_net16_hub_ipu_logic.vhd | 4 +- trb_net16_ibuf.vhd | 5 + trb_net16_ipudata.vhd | 50 ++++++-- trb_net16_trigger.vhd | 2 + trb_net_components.vhd | 35 +++++- 8 files changed, 308 insertions(+), 63 deletions(-) diff --git a/pinout/TRB_HUB2_FPGA1.lpf b/pinout/TRB_HUB2_FPGA1.lpf index 919c1c5..c509eb6 100755 --- a/pinout/TRB_HUB2_FPGA1.lpf +++ b/pinout/TRB_HUB2_FPGA1.lpf @@ -10,13 +10,12 @@ BLOCK ASYNCPATHS ; # LOCATE COMP "CLK100_N" SITE "M30"; IOBUF PORT "CLK100_P" IO_TYPE=LVDS25 PULLMODE=NONE ; - LOCATE COMP "CLK_F2_TO_F1_P" SITE "N1"; + LOCATE COMP "CLK_F2_TO_F1" SITE "N1"; # LOCATE COMP "CLK_F2_TO_F1_N" SITE "P1"; - IOBUF PORT "CLK_F2_TO_F1_P" IO_TYPE=LVDS25 PULLMODE=NONE ; + IOBUF PORT "CLK_F2_TO_F1" IO_TYPE=LVDS25 PULLMODE=NONE ; - LOCATE COMP "CLK_F1_TO_F2_P" SITE "M1"; -# LOCATE COMP "CLK_F1_TO_F2_N" SITE "N2"; - IOBUF PORT "CLK_F1_TO_F2_P" IO_TYPE=LVDS25 PULLMODE=NONE ; + LOCATE COMP "CLK_F1_TO_F2" SITE "M1"; + IOBUF PORT "CLK_F1_TO_F2" IO_TYPE=LVDS25 PULLMODE=NONE ; @@ -410,7 +409,7 @@ BLOCK ASYNCPATHS ; # Connection to Onewire ######################################### LOCATE COMP "ONEWIRE" SITE "H1"; #To temperature sensor patch - IOBUF PORT "ONEWIRE" IO_TYPE=LVCMOS PULLMODE=UP; + IOBUF PORT "ONEWIRE" IO_TYPE=LVCMOS25 PULLMODE=UP; LOCATE COMP "ONEWIRE_MONITOR" SITE "T3"; #1wire-line to FPGA2 diff --git a/pinout/TRB_HUB2_FPGA2.lpf b/pinout/TRB_HUB2_FPGA2.lpf index eafe686..3da0075 100755 --- a/pinout/TRB_HUB2_FPGA2.lpf +++ b/pinout/TRB_HUB2_FPGA2.lpf @@ -1,28 +1,15 @@ -COMMERCIAL ; -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -######################################### -# Constraints -######################################### - IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; - - FREQUENCY PORT CLK_F1_TO_F2_P 100.000000 MHz ; - FREQUENCY PORT CLK_F2_TO_F1_P 100.000000 MHz ; - - LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_1/THE_SERDES/PCSC_INST" SITE "LLPCS" ; - LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_2/THE_SERDES/PCSC_INST" SITE "LRPCS" ; - LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_3/THE_SERDES/PCSC_INST" SITE "URPCS" ; - LOCATE COMP "THE_HUB2_FPGA2/THE_MEDIA_INTERFACE_4/THE_SERDES/PCSC_INST" SITE "ULPCS" ; +IOBUF ALLPORTS IO_TYPE=LVTTL33 PULLMODE=DOWN ; ######################################### # Clock & Reset ######################################### - LOCATE COMP "CLK_F2_TO_F1_P" SITE "AC30"; - LOCATE COMP "CLK_F2_TO_F1_N" SITE "AC29"; - LOCATE COMP "CLK_F1_TO_F2_P" SITE "N1"; - LOCATE COMP "CLK_F1_TO_F2_N" SITE "P1"; + LOCATE COMP "CLK_F2_TO_F1" SITE "AC30"; + LOCATE COMP "CLK_F1_TO_F2" SITE "N1"; + + IOBUF PORT "CLK_F1_TO_F2" IO_TYPE=LVDS25 PULLMODE=NONE ; + IOBUF PORT "CLK_F2_TO_F1" IO_TYPE=LVDS25 PULLMODE=NONE ; LOCATE COMP "ADDON_RESET" SITE "C17"; LOCATE COMP "RESET_N" SITE "B17"; @@ -144,8 +131,8 @@ BLOCK ASYNCPATHS ; LOCATE COMP "ADO_TTL_44" SITE "AF18"; LOCATE COMP "ADO_TTL_45" SITE "AJ15"; LOCATE COMP "ADO_TTL_46" SITE "AG16"; #occupied by 1-wire monitor - DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ; - IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# DEFINE PORT GROUP "ado_ttl_group" "ADO_TTL*" ; + ######################################### @@ -305,8 +292,8 @@ BLOCK ASYNCPATHS ; LOCATE COMP "FS_PE_14" SITE "E13"; LOCATE COMP "FS_PE_15" SITE "J12"; LOCATE COMP "FS_PE_16" SITE "H10"; - DEFINE PORT GROUP "fs_pe_group" "FS_PE*" ; - IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# DEFINE PORT GROUP "fs_pe_group" "FS_PE*" ; +# IOBUF GROUP "ado_ttl_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; ######################################### # LED @@ -319,8 +306,8 @@ BLOCK ASYNCPATHS ; LOCATE COMP "SFP_LED_ORANGE_18" SITE "AH17"; LOCATE COMP "SFP_LED_ORANGE_19" SITE "D23"; LOCATE COMP "SFP_LED_ORANGE_20" SITE "D26"; - DEFINE PORT GROUP "sfp_led_group" "SFP_LED*" ; - IOBUF GROUP "sfp_led_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; +# DEFINE PORT GROUP "sfp_led_group" "SFP_LED*" ; +# IOBUF GROUP "sfp_led_group" IO_TYPE=LVTTL33 PULLMODE=NONE ; ######################################### # SFP Control Signals @@ -347,11 +334,11 @@ BLOCK ASYNCPATHS ; DEFINE PORT GROUP "sfp_los_group" "SFP_LOS*" ; IOBUF GROUP "sfp_los_group" IO_TYPE=LVTTL33 PULLMODE=UP ; - LOCATE COMP "TX_DIS_17" SITE "AF19"; - LOCATE COMP "TX_DIS_18" SITE "AE20"; - LOCATE COMP "TX_DIS_19" SITE "AD18"; - LOCATE COMP "TX_DIS_20" SITE "AC20"; - DEFINE PORT GROUP "tx_dis_group" "TX_DIS*" ; + LOCATE COMP "SFP_DIS_17" SITE "AF19"; + LOCATE COMP "SFP_DIS_18" SITE "AE20"; + LOCATE COMP "SFP_DIS_19" SITE "AD18"; + LOCATE COMP "SFP_DIS_20" SITE "AC20"; + DEFINE PORT GROUP "tx_dis_group" "SFP_DIS*" ; IOBUF GROUP "tx_dis_group" IO_TYPE=LVTTL33 PULLMODE=UP ; #not supported by transceivers @@ -366,7 +353,7 @@ BLOCK ASYNCPATHS ; # Onewire Monitor ######################################### LOCATE COMP "ONEWIRE_MONITOR_IN" SITE "AG16"; #former ADO_TTL(46) - IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVTTL33 PULLMODE=UP DRIVE=12 ; + IOBUF PORT "ONEWIRE_MONITOR_IN" IO_TYPE=LVTTL33 PULLMODE=UP ; ######################################### # Test Connectors diff --git a/trb_net16_api_ipu_streaming.vhd b/trb_net16_api_ipu_streaming.vhd index 2c2d15c..6a4e8a9 100644 --- a/trb_net16_api_ipu_streaming.vhd +++ b/trb_net16_api_ipu_streaming.vhd @@ -7,31 +7,33 @@ entity trb_net16_api_ipu_streaming is -- Internal direction port - FEE_INIT_DATAREADY_OUT : out std_logic; FEE_INIT_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_INIT_DATAREADY_OUT : out std_logic; FEE_INIT_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); FEE_INIT_READ_IN : in std_logic; - FEE_REPLY_DATAREADY_IN : in std_logic; FEE_REPLY_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + FEE_REPLY_DATAREADY_IN : in std_logic; FEE_REPLY_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); FEE_REPLY_READ_OUT : out std_logic; - CTS_INIT_DATAREADY_IN : in std_logic; CTS_INIT_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_INIT_DATAREADY_IN : in std_logic; CTS_INIT_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); CTS_INIT_READ_OUT : out std_logic; - CTS_REPLY_DATAREADY_OUT : out std_logic; CTS_REPLY_DATA_OUT : out std_logic_vector (c_DATA_WIDTH-1 downto 0); + CTS_REPLY_DATAREADY_OUT : out std_logic; CTS_REPLY_PACKET_NUM_OUT : out std_logic_vector (c_NUM_WIDTH-1 downto 0); CTS_REPLY_READ_IN : in std_logic; - IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); - IPU_CODE_OUT : out std_logic_vector (7 downto 0); - IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); - IPU_START_READOUT_OUT: out std_logic; + --Event information coming from CTS + IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); + IPU_CODE_OUT : out std_logic_vector (7 downto 0); + IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_START_READOUT_OUT : out std_logic; + --Answer sent to CTS APL_CTS_DATA_IN : in std_logic_vector (c_DATA_WIDTH-1 downto 0); APL_CTS_PACKET_NUM_IN : in std_logic_vector (c_NUM_WIDTH-1 downto 0); APL_CTS_DATAREADY_IN : in std_logic; @@ -50,10 +52,199 @@ entity trb_net16_api_ipu_streaming is APL_FEE_READ_IN : in std_logic; -- APL Control port - APL_RUN_OUT : out std_logic; - APL_MY_ADDRESS_IN : in std_logic_vector (15 downto 0); - + APL_CTS_RUN_OUT : out std_logic; + APL_FEE_RUN_OUT : out std_logic; + MY_ADDRESS_IN : in std_logic_vector (15 downto 0); + CTRL_SEQNR_RESET : in std_logic; ); -end entity; \ No newline at end of file +end entity; + +architecture trb_net16_api_ipu_streaming_arch of trb_net16_api_ipu_streaming is + + signal APL_CTS_TARGET_ADDRESS : std_logic_vector(15 downto 0); + signal APL_CTS_DATA_OUT : std_logic_vector(15 downto 0); + signal APL_CTS_PACKET_NUM_OUT : std_logic_vector(2 downto 0); + signal APL_CTS_DATAREADY_OUT : std_logic; + signal APL_CTS_READ_IN : std_logic; + signal APL_CTS_SEQNR_OUT : std_logic_vector(7 downto 0); + + signal APL_FEE_DTYPE_IN : std_logic_vector(3 downto 0); + signal APL_FEE_ERROR_PATTERN_IN : std_logic_vector(31 downto 0); + signal APL_FEE_SEND_IN : std_logic; + + + + +begin + +------------------------------------------------------------------------------- +--Application Interface, receiving request from CTS +------------------------------------------------------------------------------- + THE_CTS_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_PASSIVE, + FIFO_TO_INT_DEPTH => FIFO_BRAM, + FIFO_TO_APL_DEPTH => FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(1), + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS=> c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => APL_CTS_DATA_IN, + APL_PACKET_NUM_IN => APL_CTS_PACKET_NUM_IN, + APL_DATAREADY_IN => APL_CTS_DATAREADY_IN, + APL_READ_OUT => APL_CTS_READ_OUT, + APL_SHORT_TRANSFER_IN => APL_CTS_SHORT_TRANSFER_IN, + APL_DTYPE_IN => APL_CTS_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_CTS_ERROR_PATTERN_IN, + APL_SEND_IN => APL_CTS_SEND_IN, + APL_TARGET_ADDRESS_IN => APL_CTS_TARGET_ADDRESS, + -- Receiver port + APL_DATA_OUT => APL_CTS_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_CTS_PACKET_NUM_OUT, + APL_TYP_OUT => open, + APL_DATAREADY_OUT => APL_CTS_DATAREADY_OUT, + APL_READ_IN => APL_CTS_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_CTS_RUN_OUT, + APL_MY_ADDRESS_IN => MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_CTS_SEQNR_OUT, + APL_LENGTH_IN => APL_CTS_LENGTH_IN, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => CTS_REPLY_DATAREADY_OUT, + INT_MASTER_DATA_OUT => CTS_REPLY_DATA_OUT, + INT_MASTER_PACKET_NUM_OUT=> CTS_REPLY_PACKET_NUM_OUT, + INT_MASTER_READ_IN => CTS_REPLY_READ_IN, + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => '0', + INT_SLAVE_DATAREADY_OUT => '0' + INT_SLAVE_DATA_OUT => (others => '0'), + INT_SLAVE_PACKET_NUM_OUT => (others => '0'), + INT_SLAVE_READ_IN => '0', + INT_SLAVE_DATAREADY_IN => CTS_INIT_DATAREADY_IN, + INT_SLAVE_DATA_IN => CTS_INIT_DATA_IN, + INT_SLAVE_PACKET_NUM_IN=> CTS_INIT_PACKET_NUM_IN, + INT_SLAVE_READ_OUT => CTS_INIT_READ_OUT, + -- Status and control port + CTRL_SEQNR_RESET => CTRL_SEQNR_RESET, + STAT_FIFO_TO_INT => open, + STAT_FIFO_TO_APL => open + ); + + + + +------------------------------------------------------------------------------- +--Application Interface, sending request to FEE +------------------------------------------------------------------------------- + + THE_FEE_API: trb_net16_api_base + generic map ( + API_TYPE => c_API_ACTIVE, + FIFO_TO_INT_DEPTH => FIFO_BRAM, + FIFO_TO_APL_DEPTH => FIFO_BRAM, + FORCE_REPLY => cfg_FORCE_REPLY(1), + USE_VENDOR_CORES => c_YES, + SECURE_MODE_TO_APL => c_YES, + SECURE_MODE_TO_INT => c_YES, + APL_WRITE_ALL_WORDS=> c_YES, + BROADCAST_BITMASK => x"FF" + ) + port map ( + -- Misc + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + -- APL Transmitter port + APL_DATA_IN => (others => '0'), + APL_PACKET_NUM_IN => (others => '0'), + APL_DATAREADY_IN => '0', + APL_READ_OUT => open, + APL_SHORT_TRANSFER_IN => '1', + APL_DTYPE_IN => APL_FEE_DTYPE_IN, + APL_ERROR_PATTERN_IN => APL_FEE_ERROR_PATTERN_IN, + APL_SEND_IN => APL_FEE_SEND_IN, + APL_TARGET_ADDRESS_IN => (others => '1'), + -- Receiver port + APL_DATA_OUT => APL_FEE_DATA_OUT, + APL_PACKET_NUM_OUT=> APL_FEE_PACKET_NUM_OUT, + APL_TYP_OUT => APL_FEE_TYP_OUT, + APL_DATAREADY_OUT => APL_FEE_DATAREADY_OUT, + APL_READ_IN => APL_FEE_READ_IN, + -- APL Control port + APL_RUN_OUT => APL_FEE_RUN_OUT, + APL_MY_ADDRESS_IN => MY_ADDRESS_IN, + APL_SEQNR_OUT => APL_FEE_SEQNR_OUT, + APL_LENGTH_IN => APL_FEE_LENGTH_IN, + -- Internal direction port + INT_MASTER_DATAREADY_OUT => FEE_INIT_DATAREADY_OUT, + INT_MASTER_DATA_OUT => FEE_INIT_DATA_OUT, + INT_MASTER_PACKET_NUM_OUT=> FEE_INIT_PACKET_NUM_OUT, + INT_MASTER_READ_IN => FEE_INIT_READ_IN, + INT_MASTER_DATAREADY_IN => '0', + INT_MASTER_DATA_IN => (others => '0'), + INT_MASTER_PACKET_NUM_IN => (others => '0'), + INT_MASTER_READ_OUT => '0', + INT_SLAVE_DATAREADY_OUT => '0' + INT_SLAVE_DATA_OUT => (others => '0'), + INT_SLAVE_PACKET_NUM_OUT => (others => '0'), + INT_SLAVE_READ_IN => '0', + INT_SLAVE_DATAREADY_IN => FEE_REPLY_DATAREADY_IN, + INT_SLAVE_DATA_IN => FEE_REPLY_DATA_IN, + INT_SLAVE_PACKET_NUM_IN=> FEE_REPLY_PACKET_NUM_IN, + INT_SLAVE_READ_OUT => FEE_REPLY_READ_OUT, + -- Status and control port + CTRL_SEQNR_RESET => CTRL_SEQNR_RESET, + STAT_FIFO_TO_INT => open, + STAT_FIFO_TO_APL => open + ); + +------------------------------------------------------------------------------- +--Reading CTS data, forwarding to FEE +------------------------------------------------------------------------------- + + + PROC_FSM_FORWARD_CTS_REQUEST : process(CLK) + begin + APL_CTS_READ_IN <= '1'; + APL_FEE_SEND_IN <= '0'; + if APL_CTS_DATAREADY_OUT = '1' then + case APL_CTS_PACKET_NUM_OUT is + when c_F1 => + APL_FEE_ERROR_PATTERN_IN(31 downto 16) <= APL_CTS_DATA_OUT; + when c_F2 => + APL_FEE_ERROR_PATTERN_IN(15 downto 0) <= APL_CTS_DATA_OUT; + when c_F3 => + APL_FEE_SEQNR_IN <= APL_CTS_DATA_OUT(11 downto 4); + APL_FEE_DTYPE_IN <= APL_CTS_DATA_OUT(3 downto 0); + APL_FEE_SEND_IN <= '1'; + IPU_START_READOUT_OUT <= '1'; + when others => + null; + end case; + end if; + if APL_CTS_RUN_OUT = '0' then + IPU_START_READOUT_OUT <= '0'; + end if; + end process; + + IPU_NUMBER_OUT <= APL_FEE_ERROR_PATTERN_IN(15 downto 0); + IPU_CODE_OUT <= APL_FEE_ERROR_PATTERN_IN(23 downto 16); + IPU_INFORMATION_OUT <= APL_FEE_ERROR_PATTERN_IN(31 downto 24); + + + + +end architecture; \ No newline at end of file diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index c1cc8bb..d9f5517 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -671,8 +671,8 @@ begin begin if rising_edge(CLK) then if RESET = '1' or reply_data_counter_reset = '1' then - reply_data_counter <= (others => '0'); - elsif last_comb_REPLY_POOL_DATAREADY = '1' and (packet_counter = c_F1 or packet_counter = c_F3) then + reply_data_counter <= (others => '1'); + elsif last_comb_REPLY_POOL_DATAREADY = '1' and (packet_counter = c_F0 or packet_counter = c_F2) then reply_data_counter <= reply_data_counter + 1; end if; end if; diff --git a/trb_net16_ibuf.vhd b/trb_net16_ibuf.vhd index 7d97f64..f07d73e 100644 --- a/trb_net16_ibuf.vhd +++ b/trb_net16_ibuf.vhd @@ -120,6 +120,11 @@ architecture trb_net16_ibuf_arch of trb_net16_ibuf is attribute syn_keep of reg_med_data_in : signal is true; attribute syn_keep of reg_med_dataready_in : signal is true; attribute syn_keep of reg_med_packet_num_in : signal is true; + attribute syn_keep of saved_packet_type : signal is true; + attribute syn_preserve of reg_med_data_in : signal is true; + attribute syn_preserve of reg_med_dataready_in : signal is true; + attribute syn_preserve of reg_med_packet_num_in : signal is true; + attribute syn_preserve of saved_packet_type : signal is true; begin diff --git a/trb_net16_ipudata.vhd b/trb_net16_ipudata.vhd index 1fe03ba..ca56ad5 100644 --- a/trb_net16_ipudata.vhd +++ b/trb_net16_ipudata.vhd @@ -36,6 +36,7 @@ entity trb_net16_ipudata is --Information received with request IPU_NUMBER_OUT : out std_logic_vector (15 downto 0); IPU_INFORMATION_OUT : out std_logic_vector (7 downto 0); + IPU_READOUT_TYPE_OUT : out std_logic_vector (3 downto 0); --start strobe IPU_START_READOUT_OUT: out std_logic; --detector data, equipped with DHDR @@ -80,13 +81,14 @@ architecture trb_net16_ipudata_arch of trb_net16_ipudata is signal ipu_read_before : std_logic; signal second_word_waiting : std_logic; signal last_second_word_waiting : std_logic; + signal make_compare : std_logic; + signal mismatch_number : std_logic; + signal mismatch_random : std_logic; + signal mismatch_type : std_logic; + signal mismatch_length : std_logic; begin - IPU_NUMBER_OUT <= buf_NUMBER; - IPU_START_READOUT_OUT <= buf_START_READOUT; - IPU_READ_OUT <= buf_IPU_READ; - IPU_INFORMATION_OUT <= buf_INFORMATION; PROC_STATE_MACHINE : process(CLK) begin @@ -102,11 +104,11 @@ begin else buf_API_READ_OUT <= '1'; first_ipu_read <= '0'; - --make_compare <= '0'; + make_compare <= '0'; + update_buffers <= '0'; case state is when START => buf_API_SEND_OUT <= '0'; - update_buffers <= '0'; buf_START_READOUT <= '0'; if API_DATAREADY_IN = '1' and buf_API_READ_OUT = '1' and API_TYP_IN = TYPE_TRM then case API_PACKET_NUM_IN is @@ -131,10 +133,9 @@ begin end if; when MAKE_DHDR => -- send DHDR packet - update_buffers <= '0'; buf_API_SEND_OUT <= '1'; buf_API_DATAREADY_OUT <= '1'; - --make_compare <= '1'; + make_compare <= '1'; if buf_API_DATAREADY_OUT = '1' and API_READ_IN = '1' then dhdr_counter <= dhdr_counter + 1; case dhdr_counter is @@ -190,7 +191,12 @@ begin end process; buf_IPU_READ <= '1' when API_READ_IN = '1' and waiting_word = '0' and second_word_waiting = '0' and (state = READING or first_ipu_read = '1') else '0'; --- + + +--------------------------------------------------------------------- +--second half of 32bit word has to be sent +--------------------------------------------------------------------- + PROC_second_word : process(waiting_word, buf_API_DATAREADY_OUT, API_READ_IN, last_second_word_waiting, RESET) begin if RESET = '1' then @@ -215,6 +221,10 @@ begin end if; end process; + +--------------------------------------------------------------------- +--store length and error pattern input +--------------------------------------------------------------------- PROC_buffer_inputs : process(CLK) begin if rising_edge(CLK) then @@ -228,6 +238,9 @@ begin end if; end process; +--------------------------------------------------------------------- +--store ipu data +--------------------------------------------------------------------- PROC_store_IPU_input : process(CLK) begin if rising_edge(CLK) then @@ -241,6 +254,9 @@ begin end if; end process; +--------------------------------------------------------------------- +--User finished readout yet? +--------------------------------------------------------------------- PROC_get_end_of_data : process(CLK) begin if rising_edge(CLK) then @@ -252,6 +268,9 @@ begin end if; end process; +--------------------------------------------------------------------- +--Gen. Packet Number +--------------------------------------------------------------------- PROC_packet_num : process(CLK) begin if rising_edge(CLK) then @@ -266,6 +285,10 @@ begin end if; end process; +--------------------------------------------------------------------- +--Connect Outputs +--------------------------------------------------------------------- + API_ERROR_PATTERN_OUT <= buf_IPU_ERROR_PATTERN_IN; API_LENGTH_OUT <= buf_IPU_LENGTH_IN+2; API_READ_OUT <= buf_API_READ_OUT; @@ -276,8 +299,15 @@ begin API_SHORT_TRANSFER_OUT<= '0'; API_DTYPE_OUT <= buf_TYPE; + IPU_NUMBER_OUT <= buf_NUMBER; + IPU_START_READOUT_OUT <= buf_START_READOUT; + IPU_READ_OUT <= buf_IPU_READ; + IPU_INFORMATION_OUT <= buf_INFORMATION; + IPU_READOUT_TYPE_OUT <= buf_TYPE; - +--------------------------------------------------------------------- +--Debugging +--------------------------------------------------------------------- STAT_DEBUG <= (others => '0'); state_bits(0) <= '1' when state = START else '0'; diff --git a/trb_net16_trigger.vhd b/trb_net16_trigger.vhd index a00e8d8..2233022 100644 --- a/trb_net16_trigger.vhd +++ b/trb_net16_trigger.vhd @@ -90,6 +90,7 @@ begin reg_TRG_INFORMATION_OUT, reg_TRG_RECEIVED_OUT, INT_PACKET_NUM_IN, INT_DATA_IN, buf_INT_DATA_OUT, TRG_RELEASE_IN, send_trm, buf_INT_DATAREADY_OUT) begin + next_seqnr <= (others => '0'); if USE_TRG_PORT = 1 then next_TRG_TYPE_OUT <= reg_TRG_TYPE_OUT; next_TRG_CODE_OUT <= reg_TRG_CODE_OUT; @@ -97,6 +98,7 @@ begin next_TRG_CODE_OUT <= reg_TRG_CODE_OUT; next_TRG_INFORMATION_OUT <= reg_TRG_INFORMATION_OUT; next_TRG_RECEIVED_OUT <= reg_TRG_RECEIVED_OUT; + next_seqnr <= (others => '0'); if saved_packet_type = TYPE_TRM then if INT_PACKET_NUM_IN = c_F1 then next_TRG_INFORMATION_OUT <= INT_DATA_IN(15 downto 8); diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 2706eed..a2eb275 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -139,6 +139,28 @@ package trb_net_components is + component ddr_off is + port ( + Clk: in std_logic; + Data: in std_logic_vector(1 downto 0); + Q: out std_logic_vector(0 downto 0) + ); + end component; + + + + component dll_in100_out100 is + port ( + clk: in std_logic; + aluhold: in std_logic; + clkop: out std_logic; + clkos: out std_logic; + lock: out std_logic + ); + end component; + + + component trb_net16_dummy_fifo is @@ -730,7 +752,8 @@ package trb_net_components is component trb_net16_med_ecp_sfp is generic( - SERDES_NUM : integer range 0 to 3 := 0 + SERDES_NUM : integer range 0 to 3 := 0; + EXT_CLOCK : integer range 0 to 1 := c_NO ); port( CLK : in std_logic; -- SerDes clock @@ -757,6 +780,7 @@ package trb_net_components is SD_REFCLK_N_IN : in std_logic; SD_PRSNT_N_IN : in std_logic; -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) SD_LOS_IN : in std_logic; -- SFP Loss Of Signal ('0' = OK, '1' = no signal) + SD_TXDIS_OUT : out std_logic; -- SFP disable -- Status and control port STAT_OP : out std_logic_vector (15 downto 0); CTRL_OP : in std_logic_vector (15 downto 0); @@ -800,6 +824,7 @@ package trb_net_components is SD_REFCLK_N_IN : in std_logic; SD_PRSNT_N_IN : in std_logic_vector(3 downto 0); SD_LOS_IN : in std_logic_vector(3 downto 0); + SD_TXDIS_OUT : out std_logic_vector(3 downto 0); -- Status and control port STAT_OP : out std_logic_vector (4*16-1 downto 0); CTRL_OP : in std_logic_vector (4*16-1 downto 0); @@ -951,7 +976,13 @@ package trb_net_components is - + component pll_in100_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic + ); + end component; -- 2.43.0