From 30c340654e6342b2c176a472c17792f9ce7a93fd Mon Sep 17 00:00:00 2001
From: Ingo Froehlich <ingo@nomail.fake>
Date: Thu, 21 Sep 2017 17:56:15 +0200
Subject: [PATCH] flash disabled after boot, IF

---
 machxo3/flash/generic_flash_ctrl.vhd | 33 +++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/machxo3/flash/generic_flash_ctrl.vhd b/machxo3/flash/generic_flash_ctrl.vhd
index b8de49c..70b8627 100644
--- a/machxo3/flash/generic_flash_ctrl.vhd
+++ b/machxo3/flash/generic_flash_ctrl.vhd
@@ -127,7 +127,7 @@ architecture arch of generic_flash_ctrl is
   
 
   type state_type is (IDLE, EnableFLASH1, EnableFLASH2, EnableFLASH3, Start, ReadPage, WaitFlash1, WaitFlash2, ReadRAM, WaitRAM1, WaitRAM2, WaitRAM3, WaitRAM4,
-                      WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI);
+                      WaitRAM2_32, WaitRAM3_32, WaitRAM4_32, WaitRAM5_32, WaitRAM6_32, WriteSPI, DisableFLASH1, DisableFLASH2, DisableFLASH3);
   signal state : state_type := IDLE;
   signal master_running       : std_logic;
   signal master_word_counter  : std_logic_vector(3 downto 0);
@@ -435,7 +435,7 @@ begin
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
         else -- break
           master_DATA_OUT(15 downto 0) <= x"ff" & ram_data_o;
-          state <= IDLE;
+          state <= DisableFLASH1;
         end if;
       when WaitRAM2 =>
         master_ADDR_OUT <= ram_data_o;
@@ -449,7 +449,9 @@ begin
         master_DATA_OUT(15 downto 0) <= ram_data_o & x"00";
         state <= WaitRAM4;
       when WaitRAM3_32 =>
-        master_DATA_OUT(31 downto 0) <= ram_data_o & x"000000";
+        if (DATA_BUS_WIDTH > 31) then
+          master_DATA_OUT(31 downto 0) <= ram_data_o & x"000000";
+        end if;
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
         state <= WaitRAM4_32;
       when WaitRAM4 =>
@@ -457,16 +459,22 @@ begin
         state <= WriteSPI;
         master_WRITE_OUT <= '1';
       when WaitRAM4_32 =>
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 24) & ram_data_o & x"0000";
+        if (DATA_BUS_WIDTH > 31) then
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 24) & ram_data_o & x"0000";
+        end if;
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
         state <= WaitRAM5_32;
       when WaitRAM5_32 =>
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 16) & ram_data_o & x"00";
+        if (DATA_BUS_WIDTH > 31) then
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 16) & ram_data_o & x"00";
+        end if;
         master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 2);
                -- padding bytes
         state <= WaitRAM6_32;
       when WaitRAM6_32 =>
-        master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 8) & ram_data_o;
+        if (DATA_BUS_WIDTH > 31) then
+          master_DATA_OUT(31 downto 0) <= master_DATA_OUT(31 downto 8) & ram_data_o;
+        end if;
         state <= WriteSPI;
         master_WRITE_OUT <= '1';
       when WriteSPI =>
@@ -480,6 +488,19 @@ begin
           state <= ReadRAM;
           master_word_counter <= std_logic_vector(unsigned(master_word_counter) + 1);
         end if;
+      when DisableFLASH1 =>
+        state <= DisableFLASH2;
+        master_flash_command <= "101";
+        master_flash_go <= '1';
+      when DisableFLASH2 =>
+        state <= DisableFLASH3;
+        master_flash_go <= '0';
+      when DisableFLASH3 =>
+        if (flash_busy = '0') then
+           state <= IDLE;
+           master_flash_command <= "000";
+        end if;
+                             
     end case;
   end if;
 end process;
-- 
2.43.0